CMOS数字集成电路的高温电学性能分析

本文给出了ＣＭＯＳ倒相器的高温等效电路，分析了它的高温直流传输特性和瞬态特性，文章还讨论了ＣＭＯＳ静态数字集成电路高温电学特性的分析方法。本文提出了的ＣＭＯＳ数字集成电路的高温学特性模型和实验结果相接近。     

HCMOS集成电路的特性

ＨＣＭＯＳ集成电路的特性曾庆贵本文介绍ＨＣＭＯＳ集成电路的直流特性＄ｉｆ交流特性，并且和ＣＭＯＳ、ＬＳＴＴＬ等电路进行比较。一、功耗ＣＭＯＳ集成随路的最大优点是低功耗。ＨＣＭＯＳ保留了这个特点．它的功耗包括协态功耗和动态功耗。ＨＣＭＯＳ电路的静态功耗...     

HCMOS集成电路的接口和使用

ＨＣＭＯＳ集成电路的接口和使用沈毅使用ＨＣＭＯＳ集成电路的目的，是要充分利用它功耗低和速度高等优点．如果有可能的话，整个系统都应该全部选用ＨＣＭＯＳ器件。如果为了使系统达到最佳性能不得不刀Ｄ人一些其他器件时，即ＨＣＭＯＳ和其他系列器件的混合使用，就会...     

1．5μm全耗尽CMOS／SIMOX门阵列的研制

本文介绍了可用于高速、高性能抗辐照专用集成电路设计的１．５μｍ薄膜全耗尽ＣＭＯＳ／ＳＩＭＯＸ门阵列母版的研制．较为详细地讨论了ＣＭＯＳ／ＳＩＭＯＸ门阵列基本阵列单元、输入／输出单元、单元库的设计技术以及１．５μｍＣＭＯＳ／ＳＩＭＯＸ门阵列工艺开发过程．该门阵列在５Ｖ电源电压时的单级门延迟时间仅为４３０ｐｓ．     

HCMOS模拟开关及多路转换器/信号分离器

ＨＣＭＯＳ模拟开关及多路转换器／信号分离器曾庆贵开关类集成电路在ＣＭＯＳ和ＨＣＭＯＳＩＣ中占有很重要的地位，它和其他工艺的开关相比，ＣＭＯＳ＄拟开关的优点是功耗低，输入电压范围宽、开关于扰ＣＭＯＳ传输门，如图１所示。它的导通电阻Ｒ。。随输入电压Ｖｉ变...     

合并互补BiCMOS集成电路的研究

分析了几种常规ＢｉＣＭＯＳ门电路的特性，对合并互补（ＭＣ）ＢｉＣＭＯＳ集成电路的二输入与非门和１１级环形振荡器进行了实验研究，并与常规ＢｉＣＭＯＳ进行了比较。实验结果说明，ＭＣＢｉＣＭＯＳ具有电路结构简单，芯片面积小，工作速度高，负载能力强和低压工作特性好等优点。     

CMOS专用IC—步进电机分配器

ＣＭＯＳ专用ＩＣ──步进电机分配器毕玉国随着ｃＭＯＳ集成电路设计和制造技术的发展，制造一片新的ＩＣ的周期越来越短，成本也越来越低，加之ＣＭＯＳ工艺ＩＣ本身的优点，要求定制ＣＭＯＳ专用ＩＣ的用户正在增加，使ＣＭＯＳ专用ＩＣ成为ＣＭＯＳ集成电路领域中一个...     

具有优良性能的MCBiCMOS IC结构

本文分析了几种常规ＢｉＣＭＯＳ门电路的特性，对ＭＣＢｉＣＭＯＳ集成电路结构的二输入与非门和１１级环形振荡器进行了实验研究，并与常规ＢｉＣＭＯＳ进行了比较。实验结果说明：ＭＣＢｉＣＭＯＳ具有电路结构简单；芯片面积小；工作速度高，负载能力强和低压工作性能好等优点。     

采用混合模式晶体管(BMHMT)构成低温BiCMOS集成电路

本文介绍采用与ＣＭＯＳ工艺完全相容的双极／ＭＯＳ混合模式晶体管（ＢＭＨＭＴ）构成新型的低温ＢｉＣＭＯＳ集成电路．理论分析表明该电路与ＣＭＯＳ相比，在电压摆幅相同，静态功耗相近的条件下，具有更大的驱动能力，尤其在较低的工作电压下，其特点更加突出．我们用统一的标准和相同芯片面积设计了３９级带负载的ＢｉＣＭＯＳ和ＣＭＯＳ环形振荡器．实验样品经室温和低温平均门延迟时间测试，表明在相同工作电压下ＢｉＣＭＯＳ优于ＣＭＯＳ．若两种电路都采用ＳＯＩ结构，预计ＢｉＣＭＯＳ可以获得更好的结果     

MCBiCMOS门阵列的母片设计

本文介绍ＭＣＢｉＣＭＯＳ门阵列的母片设计技术。由于采用了先进的ＭＣＢｉＣＭＯＳ工艺和设计技术，ＭＣＢｉＣＭＯＳ更适合地制作高性能，大规模的专用集成电路。在２μｍＣＭＯＳ和３μｍ双极相结合的设计规则基础上，我们设计了ＭＣＢｉＣＭＯＳ２０００门门阵列母片，并利用ＭＣＢｉＣＭＯＳ宏单元库，成功地完成了ＣＧＢ２００３     

A novel PWM control for a bi-directional full-bridge DC–DC converter with smooth conversion mode transitions

A novel CMOS integrated pulse-width modulation (PWM) control circuit allowing smooth transitions between conversion modes in full-bridge based bi-directional DC–DC converters operating at high switching frequencies is presented. The novel PWM control circuit is able to drive full-bridge based DC–DC converters performing step-down (i.e. buck) and step-up (i.e. boost) voltage conversion in both directions, thus allowing charging and discharging of the batteries in mobile systems. It provides smooth transitions between buck, buck-boost and boost modes. Additionally, the novel PWM control loop circuit uses a symmetrical triangular carrier, which overcomes the necessity of using an output phasing circuit previously required in PWM controllers based on sawtooth oscillators. The novel PWM control also enables to build bi-directional DC–DC converters operating at high switching frequencies (i.e. up to 10?MHz and above). Finally, the proposed PWM control circuit also allows the use of an average lossless inductor-current sensor for sensing the average load current even at very high switching frequencies. In this article, the proposed PWM control circuit is modelled and the integrated CMOS schematic is given. The corresponding theory is analysed and presented in detail. The circuit simulations realised in the Cadence Spectre software with a commercially available 0.18?µm mixed-signal CMOS technology from UMC are shown. The PWM control circuit was implemented in a monolithic integrated bi-directional CMOS DC–DC converter ASIC prototype. The fabricated prototype was tested experimentally and has shown performances in accordance with the theory.     

FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems

A series FinFET based non-volatile logic gates with multiple logic functions defined by embedded non-volatile states are proposed for the first time and demonstrated in advanced CMOS technology platform. The device channels in the proposed CMOS logic gate is controlled by a metal floating gate coupled by slot contacts uniquely available in the FinFET process employed in this study. The new logic gate with non-volatile states only enable reconfiguration ability in a Boolean computing unit at a gate level aimed for adaptive and specialized systems in the AI era. Furthermore, the extended applications in tunable ring oscillators for multi-functional IOT modules are successfully demonstrated in this study.     

A PWM signal processing core circuit based on a switched currentintegration technique

A highly functional circuit for pulse width modulation (PWM) signal processing is proposed as a core of the A-D merged circuit architecture for time-domain information processing. The core circuit employs a switched-current integration technique as its computing architecture and functions as a linear arithmetic operator, a memory, and also a delaying device of PWM signals. A 0.8-μm CMOS test chip includes 110 transistors plus two capacitors and performs parallel additions and multiplications at the accuracy of 1.2 ns. A cumulative property of the technique allows the circuit to serve as a low-power accumulator that consumes 23% of the energy of the full digital 7-b accumulator. A PWM multiply-accumulate unit and a nonlinear operation unit are also proposed to extend functionality of the circuit. Since the PWM signal carries multibit data in a binary amplitude pulse, these circuits can be favorably applicable to low-voltage and low-power designs in the deep submicrometer era     

基于比较器的四值电流型CMOS加减电路设计

该文通过对电流型CMOS电路的阈值控制引入了多值电流型比较器。与2值逻辑电路相比,多值逻辑电路的单条导线允许更多的信息传输。相较于电压信号,电流信号易实现加、减等算术运算,在多值逻辑的设计上更加方便。同时提出了基于比较器的4值基本单元设计方法,实现了4值取大、取小以及反向器的设计,在此基础上设计实现了加法器和减法器。该设计方法在2值、3值以及n值逻辑上同样适用。实验结果表明所设计的电路具有正确的逻辑功能,较之相关文献电流型CMOS全加器有更低的功耗和更少的晶体管数。     

CPLD在基于PCI总线的功率模块设计中的应用

针对机电一体化开发平台中微处理器模块与功率模块通过PCI总线实现通信．介绍了一种基于复杂可编程逻辑器件（CPLD）的驱动直流电机的脉宽调制（PWM）电路设计。该电路设计可产生三路占空比与频率可调的PWM信号,实现PWM控制直流电机。     

CMOS门电路电磁信息泄漏评估

通过将CMOS工艺中的导线转化为电偶极子模型,提出了一种对CMOS工艺的门电路进行电磁信息泄漏评估的方法.仿真实验采用TSMC0.18μm工艺,实现了基于单轨逻辑以及SABL双轨逻辑的与非门,并用提出的评估方法对门电路的电磁信息泄漏进行评估.仿真结果表明,该评估方法能够对CMOS门电路的电磁信息泄漏程度进行量化评估,同时还表明了双轨门电路电磁信息泄漏弱于单轨门电路.     

Analog logic techniques steer around the noise

CMOS folded source-coupled logic (FSCL) and current-steering logic (CSL), developed to complement conventional CMOS static logic in high-precision mixed-signal applications, are examined. The key feature of FSCL and CSL is the reduction in power-supply noise-current spikes by two orders of magnitude or more compared to conventional CMOS logic. Hence, FSCL and CSL are attractive for the high-speed logic sections of CMOS mixed-mode integrated circuits, while conventional logic is appropriate for the low-speed digital subsections     

Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units

In this paper, a new leading-zero counter (or detector) is presented. New boolean relations for the bits of the leading-zero count are derived that allow their computation to be performed using standard carry-lookahead techniques. Using the proposed approach various design choices can be explored and different circuit topologies can be derived for the design of the leading-zero counting unit. The new circuits can be efficiently implemented either in static or in dynamic logic and require significantly less energy per operation compared to the already known architectures. The integration of the proposed leading-zero counter with the leading-zero anticipation logic is analyzed and the most efficient combination is identified. Finally, a simple yet efficient technique for handling the error of the leading-zero anticipation logic is also presented. The energy-delay behavior of the proposed circuits has been investigated using static and dynamic CMOS implementations in a 130-nm CMOS technology.     

一种CMOS静态双沿顺序脉冲发生器的设计

提出一种基于CMOS技术的静态双沿顺序脉冲发生器结构。他是由以基于CMOS二选一选择器的电平型触发器构成的记忆单元和一个与门阵列组成的转译单元构成的。与门阵列的转译单元使顺序脉冲发生器在时钟上升沿和下降沿处均能输出移位脉冲,从而形成双沿触发的功能。仿真验证其功能正确,且根据分析该结构不仅能够节省芯片面积,还可以大大减小芯片的功耗。     

On-Chip IDDQ testability schemes for detecting multiplefaults in CMOS ICs

In this paper we present two on-chip design-for-testability (DFT) schemes for CMOS ICs. One is for small circuits and the other for large circuits. Both schemes identify a faulty area on a chip with only a small area overhead for the additional circuitry and at most two extra pins. Moreover, if faults occur in different areas, multiple faults can also be detected with the proposed schemes. To demonstrate the ideas, DFT is incorporated in a 4-bit carry look ahead adder/subtractor (CLAAS) as well as a 16-bit arithmetic logic unit (ALU). Simulation results are given