Suppression of the floating-body effect in partially-depleted SOIMOSFETs with SiGe source structure and its mechanism

SiGe layers were formed in source regions of partially-depleted 0.25-μm SOI MOSFETs by Ge implantation, and the floating-body effect was investigated for this SiGe source structure. It is found that the increase of the Ge implantation dosage suppresses kinks in I_d-V_d characteristics and that the kinks disappear for devices with a Ge dose of 3×10¹⁶ cm^-2. The lowering of the drain breakdown voltage and the anomalous decrease of the subthreshold swing are also suppressed with this structure. It is confirmed that this suppression effect originates from the decrease of the current gain for source/channel/drain lateral bipolar transistors (LBJTs) with the SiGe source structure. The temperature dependence of the base current indicates that the decrease of the current gain is ascribed to the bandgap narrowing of the source region     

Temperature dependence of hot-electron-induced degradation in MOSFET's

The temperature dependence of MOSFET degradation due to hot-electron injection has been studied. The slower degradation rate at elevated temperature at fixed stressing bias follows the substrate current level which is reduced mainly by lower localized electric field rather than lower ionization coefficient (both are caused by enhanced phonon scattering). The actual degradation rate at the constant substrate current level is slightly higher at elevated temperatures, indicating an enhanced interface-state generation mechanism. This temperature dependence provides a simple relationship between device degradation and substrate current at various temperatures.     

Evaluation of LDD MOSFET's based on hot-electron-induced degradation

Hot-electron-induced device degradation in LDD MOSFET's is thoroughly studied. Conventional ways to characterize device degradation, i.e., threshold shift and transconductance reduction, are not suitable for LDD MOSFET's due to the nature of degradation in such devices. Using a current-drive degradation criterion, it is shown that LDD MOSFET's have little net advantage over conventional MOSFET's in terms of hot-electron-induced long-term degradation.     

Effect of final annealing on hot-electron-induced MOSFET degradation

The effect of the post metallization final annealing step on hot-electron-induced device degradation in MOSFET's with various drain/source structures has been studied. It is shown that the hydrogen ambient during the final annealing enhances the hot-electron-induced degradation rate. By performing the final annealing in the nitrogen ambient, the device reliability can be significantly improved without sacrificing any of the device performances.     

Relationship between MOSFET degradation and hot-electron-induced interface-state generation

Device degradation due to hot-electron injection in n-channel MOSFET's is mainly caused by mobility degradation and reduced mobile charges in the channel introduced by interface-state generation. With the use of simple gradual-channel approximation (GCA), a linear relationship is derived between the threshold shift, relative transconductance reduction, and the number of interface states generated. This model provides a link between the electrical characteristics of a degraded device and its physical damages and, therefore, is a vital tool in the study of hot-electron-induced device degradation mechanisms.     

Trapped-electron and generated interface-trap effects in hot-electron-induced MOSFET degradation

A new experimental method is proposed to distinguish the electron-trapping effect in the gate oxide from the interface-trap generation effect in hot-electron-induced nMOSFET degradation. In this method, by selecting the appropriate bias conditions, hot electrons and/ or hot holes are intentionally injected into the oxide region above the channel outside the drain layer, which affects MOSFET characteristics such as threshold voltage and transconductance. The negative charges of electrons trapped in the oxide during hot-electron injection are completely compensated for by the positive charges of subsequently injected and trapped holes, and the trapped electron effect in the degradation is eliminated. Using this method, the causes for hot-electron-induced transconductance degradation (Δgm/gm) are analyzed. As the degradation increases, the trapped-electron effect decreases, and the generated interface-trap effect increases. The relationship of (Δgm/gm)_{it}, =A(Δgm/gm) --Bis obtained, where (Δgm/gm)_{it} is gmdegradation due to generated interface-traps, andAandBare fixed numbers. Furthermore φ_{it}/λ (the ratio of the critical value in hot-electron energy for interface-trap generation to the mean free path of hot electrons in Si) is experimentally obtained to be 5.7 × 10⁶eV/cm. Using λ = 9.2 nm [1], a value of φ_{it} = 5.2 eV is derived.     

Improvement of hot-electron-induced degradation in MOS capacitorsby repeated irradiation-then-anneal treatments

Improvement of the SiO₂/Si interface degradation due to hot-electron injections from silicon by repeated irradiation-then-anneal treatments is described. Each treatment includes an irradiation of Co-60 with a total dose of 10⁶ rd (SiO₂) and an anneal in N₂ for 10 min successively. It is found that the sensitivity to hot-electron induced damage decreases gradually as the number of irradiation-then-anneal treatments increases. After three such treatments, the MOS capacitor shows excellent behavior in terms of its hardness to hot-electron-induced degradation     

Clarification of floating-body effects on drive current and shortchannel effect in deep sub-0.25 μm partially depleted SOIMOSFETs

We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 μm floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (V_th) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller V_th-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 μm, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current     

Suppression of hot-electron-induced interface degradation in metal-oxide-semiconductor devices by backsurface argon bombardment

Low-energy (550 eV) argon-ion beam was used to bombard directly the backsurface of polysilicon-gate metal-oxide-semiconductor (MOS) capacitors after the completion of all conventional processing steps. The effects of this extra step on the interface characteristics of the MOS capacitors before and after hot-electron injection were investigated. After the backsurface argon-ion bombardment, the MOS capacitors showed improved interface hardness against hot-electron-induced degradation. A turn-around behavior was observed, indicating that an optimal bombardment time should be used. The physical mechanism involved could possibly be stress compensation at the Si/SiO₂ interface, induced by the backsurface bombardment.     

Hot carrier induced degradation in mesa-isolated n-channel SOIMOSFETs operating in a Bi-MOS mode

A thorough investigation of hot carrier effects is made in mesa-isolated SOI nMOSFETs operating in the Bi-MOS mode (abbreviated as Bi-nMOSFETs). As a result of its unique hybrid operation mechanism, significant reduction of hot carrier induced maximum transconductance degradation and threshold voltage shift in the Bi-nMOSFET is observed in comparison with that in the conventional SOI nMOSFETs. Device lifetime of SOI Bi-nMOSFETs and conventional SOI nMOSFETs was roughly estimated for comparison. In view of the analysis of the degradation mechanism, the devices were stressed under different conditions. The post-stress body current and stress body current in Bi-nMOSFETs as a function of the stress time and stress drain voltage were evaluated as further proofs of the aging reasons. The hot electron injection is found to be the dominant degradation process in the SOI Bi-nMOSFETs. Compared with SOI nMOSFETs, SOI Bi-nMOSFETs show better immunity to the parasitic bipolar transistor action due to the body contact. In addition, the positive body bias can result in lowered hot hole injection into the gate oxide due to the provision of the generated hole leakage path, and thus decreased interface traps     

Characterization of the hot-electron-induced degradation in thin SiO2 gate oxides

With decreasing oxide thickness, some of the established methods to characterize oxide degradation become inapplicable because of limited sensitivity and because of direct tunneling which gives rise to large leakage currents through the oxide. However, new techniques are emerging which could not previously be used on thicker oxides, such as stress-induced leakage current measurements, current noise measurements, hot-electron emission microscopy, ballistic electron emission microscopy and hot-carrier luminescence. Some of these techniques provide unprecedented information on the local current densities with high spatial resolution and can be used to study inhomogeneous degradation in thin oxides at low voltages where homogeneous hot-carrier degradation becomes energetically unfavorable. In Si/SiO₂/poly-Si structures, three different, homogeneous, hot-electron induced degradation processes have been identified, with threshold voltages at 12 V, 7.5 V and about 4 V. These are the generation of holes by impact ionization in the oxide, the injection of holes from the anode, and the release of hydrogen mostly from near the anode, respectively. The released hydrogen is very reactive and is responsible for the generation of many stress-induced defects. The existence of energy thresholds for homogeneous defect generation may limit the use of voltage acceleration for reliability evaluations.     

Low-frequency noise sources in polysilicon emitter BJT's: influenceof hot-electron-induced degradation and post-stress recovery

The noise properties of polysilicon emitter bipolar transistors are studied. The influences of the various chemical treatments and annealing temperatures, prior and after polysilicon deposition, on the noise magnitude are shown. The impact of hot-electron-induced degradation and post-stress recovery on the base and collector current fluctuations are also investigated in order to determine the main noise sources of these devices and to gain insight into the physical mechanisms involved in these processes     

Grasping SOI floating-body effects

It is important to understand what the floating-body effects are and how they affect device and circuit behavior. In this regard, this article qualitatively explains the device physics underlying DC and transient floating-body effects, clearly implying their influence on circuits, and thereby giving good insight into PD/SOI CMOS design issues. The article also notes special but practical device and circuit designs for controlling floating-body effects, showing through simulation how PD/SOI offers a significant performance advantage over bulk silicon in low-voltage applications, thereby conveying an assurance that reliable SOI CMOS design is feasible     

Off-state modulation of SOI floating-body

Off-state modulation of the floating-body potential in partially depleted silicon-on-insulator (PDSOI) transistors from the 90-nm technology generation is observed using pulsed current-voltage (I-V) measurements. Varying the off-value of the gate voltage is shown to either decrease the transient on-current (I/sub on,trans/) of PDSOI devices through gate-to-body leakage or increase I/sub on,trans/ due to gate-induced drain leakage. Dependence of I/sub on,trans/ on off-state gate bias is not observed in bulk devices, PDSOI devices with body contacts, or fully depleted SOI devices, confirming the role of floating-body in the observed effects. Thus, off-state conditions should be accounted for when considering floating-body effects and when using pulsed I-V measurements to study self-heating.     

Analysis of the drain breakdown mechanism in ultra-thin-film SOIMOSFETs

The drain breakdown phenomenon in ultra-thin-film (silicon-on-insulator) SOI MOSFETs has been studied. Two-dimensional simulation revealed that the thinning of the SOI film brings about an increase in the drain electric field due to the two-dimensional effect, causing a significant lowering in the drain breakdown voltage, as has been commonly seen in ultra-thin-film SOI MOSFETs. The simulation also showed that the lowered drain breakdown voltage recovered almost to its original value when the drain SOI thickness was restored, suggesting that the drain structure, rather than the source, plays a major role in determining the drain breakdown voltage. Experiments using an asymmetric device structure supported this hypothesis, showing that the breakdown voltage was mostly dependent on the drain structure, the initial potential barrier height at the source-SOI-body junction being only a minor factor. Transient simulation was also carried out to investigate the detailed breakdown process, showing that holes accumulate near the source-SOI-body junction at a high drain bias, eventually forward-biasing the junction. These results indicate that a careful drain design and/or proper choice of the SOI thickness as well as the supply voltage are quite important for realizing high performance of ultra-thin-film SOI MOSFETs     

Modeling of output snapback characteristics in n-channel SOIMOSFETs

The snapback effect is usually observed in the output characteristics of an n-channel SOI MOSFET with zero gate voltage in which the drain-to-source breakdown voltage is less than the drain-to-body avalanche voltage. It can be attributed to parasitic lateral bipolar actions as well as the MOS feedback mode of operation-a point often overlooked in the literature. An analytical model is developed for predicting the observed output characteristics taking into account both the bipolar and the MOS mechanisms. Results obtained from this model agree well with the experimental I-V curves, and show that, with continuing scaling of device geometries and improvement in SOI materials, the bipolar-induced snapback will become dominant in the future     

Investigation of anomalous leakage current in mesa-isolated SOIMOSFETs

The mechanism of an anomalous leakage current in mesa-isolated SOI NMOSFETs in the short-channel region was analyzed. The enhanced diffusion of the source-drain impurities was observed in the mesa edge region by Energy Dispersive X-ray Spectroscopy (EDX) analysis. Moreover, using high-resolution TEM observation, it was found that there were no crystalline defects in the edge region. The frequency of leakage currents in short-channel MOSFETs was higher than that of long-channel MOSFETs. The level of leakage current was not changed by the gate voltage and back gate voltage, and the activation energy of the leakage current was almost 0 eV. According to these results, it is concluded that the origin of the anomalous leakage current is the enhanced diffusion of source-drain impurities     

Principles of transient charge pumping on partially depleted SOIMOSFETs

A new method to determine the interface trap density in partially depleted silicon-on-insulator (SOI) floating body MOSFETs is proposed for the first time. It can be considered as a "transient" charge-pumping (CP) technique in contrast to the normally used "steady-state" method. In our technique, majority carriers are removed from the floating body by applying a burst of pulses to the transistor gate. The change in the linear drain current after each pulse is used to determine the device interface trap density. The unique advantage of this method is the possibility to use it to characterize SOI MOSFETs without a body contact. The technique proposed is simple, reliable, and can be used for the characterization of deep submicron devices     

Kink-like effect in long n-channel twin-gate fully-depleted SOIMOSFETs

Twin-gate structures consisting of the series combination of two short-channel SOI MOSFETs of different lengths with a common gate have previously demonstrated kink-free and very flat output characteristics. The authors observe and explain that when using long-channel fully-depleted twin-gates a kink-like effect reappears and seriously damages the output conductance     

Noise contribution of the body resistance in partially-depleted SOIMOSFETs

An additional noise component is observed in the noise spectrum of transistors in a partially-depleted (PD) medium-thickness SOI-CMOS technology. We identify the origin of this additional noise in the noisy resistance of the body film. This resistance, coupled to the gate capacitance, forms an RC filter and generates the hump-shape of the additional noise component. Several experimental observations that support this model are presented