凹槽栅MOSFET凹槽拐角的作用与影响研究

短沟道效应是小尺寸ＭＯＳＦＥＴ中很重要的物理效应之一，凹槽栅ＭＯＳＦＥＴ对短沟道效应有很强的抑制能力，通过对凹槽栅ＭＯＳＦＥＴ结构，特性的研究，发现凹槽拐角对凹槽栅ＭＯＳＦＥＴ的阈值电压及特性有着显著的影响，凹槽拐角处的阈值电压决定着整个凹槽栅ＭＯＳＦＥＴ的阈值电压，凹槽拐角的曲率半径凹槽ＭＯＳＦＥＴ一个重要的结构参数，通过对凹槽拐角的曲率半径，源漏结深及沟道掺杂浓度进行优化设计，可使凹槽栅ＭＯＳ     

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET’s

Grooved gate structure Metal-Oxide-Semiconductor(MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region,for it can suppress hot carrier effect and short channel effect deeply.Based on the hydrodynamic energy transoprt model,using two-dimensional device simulator Medici,the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel Mosfet‘s is studied and compared with that of counterpart conventional planar device in this paper.The examined structure parameters include negative junction depth,conventinal planar device in this paper.The examined structure parameters include negative junction depth,concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device.With the increase of concave corner,the hot carrier effect in groovd gate MOSFET decreases sharply,and with the reducing of effective channel length,the hot carrier effect becomes large.     

凹槽拐角对深亚微米槽栅PMOSFET特性的影响

为优化槽栅器件结构 ,提高槽栅 MOSFET的性能和可靠性 ,文中用器件仿真软件对凹槽拐角对深亚微米槽栅 PMOSFET的特性影响进行了研究。研究结果表明凹槽拐角强烈影响器件的特性 :随着凹槽拐角的增大 ,阈值电压上升 ,电流驱动能力提高 ,而热载流子效应大大减弱 ,抗热载流子性能增强 ,热载流子可靠性获得提高 ;但凹槽拐角过大时 (例如 90°) ,器件特性变化有所不同     

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET''''s

Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region, for it can suppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energy transport model, using two-dimensional device simulator Medici, the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET's is studied and compared with that of counterpart conventional planar device in this paper. The examined structure parameters include negative junction depth, concave corner and effective channel length. Simulation results show that grooved gate device can suppress hot carrier effect deeply even in deep sub-micron region. The studies also indicate that hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device. With the increase of concave corner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the redu     

Reliable tantalum-gate fully-depleted-SOI MOSFET technologyfeaturing low-temperature processing

A reliable tantalum (Ta)-gate device technology, which can drastically reduce the number of process steps, has been developed. Ta-gate fully-depleted-silicon-on-insulator (FDSOI) MOSFETs with 0.15-μm gate length by low-temperature processing below 500°C after the gate oxide formation have good on/off characteristics. Comprehensive design guidelines for Ta-gate MOSFETs in the deep-submicrometer regime is provided by investigating a wide range of performance and reliability constraints on the process temperature and the SOI thickness. In the guideline, the recrystallization of the source/drain region gives inferior limits of the SOI thickness and the process temperature. Thermal reaction between Ta and SiO₂ films sets a superior limit of the process temperature, and a short-channel effect sets a superior limit of the SOI thickness     

Current-crowding effect in diagonal MOSFET's

Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I_sub condition (V_g =0.5 V_d). However, in the high-gate-bias region (V_g=V_d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I_sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V_g>V_d), this current-crowding effect in the diagonal transistor can be a serious reliability concern     

槽栅NMOSFET结构与性能仿真

基于流体动力学能量输运模型 ,利用二维器件模拟器 MEDICI对深亚微米槽栅 NMOSFET器件的结构参数 ,如结深、凹槽拐角及沟道长度等对器件性能的影响进行了仿真研究 ,并与相应的常规平面器件特性进行了对比 .研究表明在深亚微米范围内 ,槽栅器件能够很好地抑制短沟道效应和热载流子效应 ,但电流驱动能力较平面器件小 ,且器件性能受凹槽拐角和沟道长度的影响较显著     

Investigation of geometry dependence on MOSFET linearity in the impact ionization region using Volterra series

In this paper, investigation of device geometry on intermodulation distortion (IMD) of metal–oxide–semiconductor field-effect transistors (MOSFETs) is presented in the impact ionization region based on the Volterra analysis. As the gate length or gate width decreases, observed linearity improvement of the MOSFET in the breakdown regime is attributed to the more obvious breakdown inductance nonlinearity which cancels the transconductance nonlinearity. Linearity of the MOSFETs can be improved by choosing suitable device geometry in the breakdown region. It is believed the presented analysis results can benefit the reliability investigation for MOSFET linearity in the breakdown region.     

High-frequency characterization of sub-0.25-μm fully depletedsilicon-on-insulator MOSFETs

A cutoff frequency, f_T, of 85 GHz was measured on a fully-depleted silicon-on-insulator (FDSOI) n-MOSFET with a gate length of 0.15 μm. The p-MOSFET with 0.22-μm gate length has an f_T of 42 GHz. The high-frequency equivalent circuits were derived from scattering parameters for MOSFETs with various gate lengths. The effects of gate length and other device parameters on the performance of FDSOI MOSFETs at RF are discussed     

GaAs MOSFETs fabrication with a selective liquid phase oxidizedgate

The N-channel depletion-mode GaAs MOSFETs with a liquid phase chemical enhanced selective gate oxide grown at low temperature are demonstrated. The proposed selective oxidation method makes the fabrication process of GaAs MOSFETs more reliable and self side-wall passivation possible. The fabricated GaAs MOSFETs exhibit current-voltage characteristics with complete pinch-off and saturation characteristics. The 2 μm gate-length MOSFETs with a gate oxide thickness of 35 nm show transconductance larger than 80 mS/mm and maximum drain current density of 380 mA/mm. In addition, microwave characteristics with f_T of 1.8 GHz and f_max of 5.2 GHz have been achieved from the 3 μm×60 μm GaAs MOSFETs     

Suppression of corner effects in triple-gate MOSFETs

The abnormal corner effects on channel current in nanoscale triple-gate MOSFETs are examined via two-dimensional (2-D) numerical simulations and quasi-2-D analysis. Heavy body doping [for threshold voltage (V/sub t/) control with a polysilicon gate] is found to underlie the effects, which can hence be suppressed, irrespective of the shape of the corners, by leaving the body undoped, and relying on a metal gate with proper work function for V/sub t/ control. Short-channel effects tend to ameliorate the corner effects, but the need for ad hoc suppression remains.     

Scaling theory for double-gate SOI MOSFET's

A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t_si; gate oxide thickness t_ox) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 μm while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator     

High-current snapback characteristics of MOSFETs

The high-current snapback characteristics of MOSFETs with different channel lengths and widths, gate oxide thicknesses, and substrate dopings were studied to determine their effectiveness in electrostatic discharge stress protection. Filamentary conduction was not observed for currents up to 7 mA/μm of channel width for a pulsewidth of 500 ns. MOSFETs with shorter channel lengths require lower voltages to sustain the same current, independent of gate oxide thickness. Increasing the substrate doping does not necessarily reduce the high current voltage. These trends can be explained using a simple lateral n-p-n bipolar transistor snapback model     

Study of the manufacturing feasibility of 1.5-nm direct-tunnelinggate oxide MOSFETs: uniformity, reliability, and dopant penetration ofthe gate oxide

Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 μm×0.75 μm, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n⁺ polysilicon gates subjected to RTA at 1050°C for 20 s and furnace annealing at 850°C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications     

Effect of extrinsic impedance and parasitic capacitance on figure of merit of RF MOSFET

This paper investigates the impact of source/drain impedance, gate-to-bulk capacitance, and gate resistance on device properties from 0 to 50 GHz for 0.13-/spl mu/m MOSFETs. Better device characteristics (g/sub m/ and C/sub gg/) can be found on MOSFETs with lower metal (or source/drain) resistance. But the best frequency characteristics (f/sub T/ and f/sub max/) occurred on MOSFETs with medium metal (or source/drain) resistance due to the increased interconnection capacitances. For radio frequency MOSFETs with finger-gate structure, better high-frequency behavior occurred on devices with medium finger-gate width W/sub f/ because of the tradeoff between gate (or source/drain) resistance and parasitic capacitance.     

槽栅NMOSFET结构与性能仿真

基于流体动力学能量输运模型,利用二维器件模拟器MEDICI对深亚微米槽栅NMOSFET器件的结构参数,如结深、凹槽拐角及沟道长度等对器件性能的影响进行了仿真研究,并与相应的常规平面器件特性进行了对比.研究表明在深亚微米范围内,槽栅器件能够很好地抑制短沟道效应和热载流子效应,但电流驱动能力较平面器件小,且器件性能受凹槽拐角和沟道长度的影响较显著.     

Ultrathin gate oxide CMOS on (111) surface-oriented Si substrate

The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a (111) surface-oriented Si substrate were investigated and compared with those on a (100) substrate for the first time. It was confirmed that low field mobility of n-MOSFETs on the (111) substrate is smaller than that on the (100) substrate and that of p-MOSFETs on (111) is larger than that on (100) until the direct-tunneling gate oxide regime. It has been found that most of the electrical properties of MOSFETs, with the notable exception of mobility, become almost identical for (100) and (111) substrates when the oxide thickness is reduced to less than 2.0 nm. Some of the properties are quite different between the two substrates for the thicker oxide case. It has been found that the reliability of hot carrier injection and time-dependent dielectric breakdown (TDDB) of the oxides and MOSFETs on the (111) substrate is slightly better than that on the (100) substrate. In addition, the characteristics and reliability of oxides and MOSFETs on a wafer tilted 4° from (100) axis were investigated. It was found that there are few differences in the mobility between (100) and (100) 4° off substrates for both n- and p-MOSFET cases. The reliability of oxides or MOSFETs on the wafer was identical to that on normal (100) substrate. These results suggest that ultrathin gate oxide MOSFETs on Si surfaces with various orientations are likely to have practical applications. This is good news for possible future new structures of MOSFETs such as vertical or three-dimensional (3-D) MOSFETs     

深亚微米槽栅PMOSFET几何结构参数对抗热载流子特性的影响

基于流体动力学能量输运模型,利用二维仿真软件Medici对深亚微米槽栅PMOS器件的几何结构参数,如:沟道长度、凹槽拐角、凹槽深度和漏源结深导致的负结深对器件抗热载流子特性的影响进行了研究。并从器件内部物理机理上对研究结果进行了解释。研究发现,在深亚微米和超深亚微米区域,槽栅器件能够很好地抑制热载流子效应,且随着凹槽拐角、负结深的增大,器件的抗热载流子能力增强。这主要是因为这些结构参数影响了电场在槽栅MOS器件的分布和拐角效应,从而影响了载流子的运动并使器件的热载流子效应发生变化。     

1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs with 1.5 nm gate oxides. This is the highest value ever obtained for p-channel Si MOSFETs at room temperature. Further, it was demonstrated that more than 100 GHz of cutoff frequency is realized both for n- and p-MOSFETs. Thus, using [110] substrates results in a better balance for n- and p-MOS performances. The SiO/sub 2/ film and SiO/sub 2//Si interface qualities on [110] substrates were also investigated. In this experiment, it was found that direct-tunneling gate leakage current and initial 1/f noise of MOSFETs on [110] substrates are larger than those on [100] substrates. The reliability regarding Negative Bias Temperature Instability (NBTI) for p-MOSFETs on [110] substrates was also inferior to that for [100] MOSFETs. However, with a high-k insulator or improvement of the SiO/sub 2/ film quality, high mobility of p-MOSFETs on [110] substrates will have a potential not only for digital applications but also for new RF analog circuits under low supply voltage.     

深亚微米槽栅NMOSFET结构参数对其抗热载流子特性的影响

基于流体动力学能量输运模型和幸运热载流子模型,用二维器件仿真软件Medici对深亚微米槽栅NMOSFET的结构参数,如沟道长度、槽栅凹槽拐角角度、漏源结深等,对器件抗热载流子特性的影响进行了模拟分析,并与常规平面器件的相应特性进行了比较.结果表明即使在深亚微米范围,槽栅器件也能很好地抑制热载流子效应,且其抗热载流子特性受凹槽拐角和沟道长度的影响较显著,同时对所得结果从内部物理机制上进行了分析解释.