Algorithm for efficient symbolic analysis of large analoguecircuits

An algorithm is presented that generates simplified symbolic expressions for the small-signal characteristics of large analogue circuits. The expressions are approximated while they are computed, so that only the most significant terms are generated which remain in the final expression. This principle leads to dramatic savings in CPU time and memory compared to existing techniques, significantly increasing the maximum size of circuits that can be analysed. By taking into account a range for the value of a circuit parameter rather than one single number the generated symbolic expressions are also generally valid     

ISAAC: a symbolic simulator for analog integrated circuits

The symbolic simulator ISAAC (interactive symbolic analysis of analog circuits) is presented. The program derives all AC characteristics for any analog integrated circuit (time-continuous and switched-capacitor, CMOS, JFET, and bipolar) as symbolic expressions in the circuit parameters. This yields analytic formulas for transfer functions, CMRR (common-mode rejection ratio), PSRR (power-supply rejection ratio), impedances, noise, etc. Two novel features are included in the program. First, the expressions can be simplified with a heuristic criterion based on the magnitudes of the elements. This yields interpretable formulas showing only the dominant terms. Second, the explicit representation of mismatch terms allows the accurate calculation of second-order effects, such as the PSRR. ISAAC provides analog designers with more insight into the circuit behavior than do numerical simulators and is a useful tool for instruction or designer assistance. Moreover, it generates complete analytic AC circuit models, which are used for automatic sizing in a nonfixed topology analog module generator. The program's capabilities are illustrated with several examples. The efficiency is established by a dedicated sparse-matrix algorithm     

Interactive AC modeling and characterization of analog circuits via symbolic analysis

An advanced symbolic analyzer, called ASAP, has been developed for the automatic ac modeling of analog integrated circuits. ASAP works on a data base of model primitives and provides error-free symbolic expressions for the different system functions of analog circuits composed by the primitives. Both complete and simplified expressions can be calculated. Two simplification criteria have been implemented. The basic one is based on pruning the least significant terms in the different system function coefficients. This may yield important errors in pole and zero locations. To avoid that, an improved criterion has been developed where pole and zero displacements are forced to remain bounded. Also implemented are routines for symbolic pole/zero extraction and parametric ac circuit characterization. ASAP uses the signal flow graph method for symbolic analysis and has been written in the C language for portability. Together with portability, efficiency and ability to manage complexity have been fundamental goals in the implementation of ASAP. These features are demonstrated in this paper via practical examples.     

Symbolic Steady-State Analysis for Strongly Nonlinear Circuits and Systems

A symbolic method for steady-state analysis of nonlinear circuits and systems is presented. This method is based on the principle of the Equivalent Small Parameter method (the ESP method), which is an improved perturbation technique combined with the harmonic balance method. Using this method, a set of high-order nonlinear differential equations can be solved and the symbolic expressions of the steady-state periodic solutions for the required variables can be obtained. Two examples are given and show that the method is general and can be used for both weakly and strongly nonlinear circuits, and time-variant nonlinear circuits such as switching mode circuits.     

Automated simplified analysis of analogue circuit behaviour based on fully symbolic relations between parameters

Symbolic circuit analysis provides the key for understanding the mechanisms underneath circuit operation, and it can be used to obtain predictive models of circuit behaviour. Symbolic analysis has many applications in the design of analogue circuits but is severely limited by the size of the resulting expressions. Thus an efficient approximation strategy is required for successful symbolic analysis of large analogue circuits. A fully symbolic procedure for the simplification of large expressions, which mimics the heuristic procedures followed by an experienced designer (based on the relations between the parameters of the circuit), is presented in this paper. This simplification strategy is particularly well suited to be combined with some circuit level partition algorithms, leading to a blend between simplification after generation (SAG) and simplification during generation (SDG). The algorithms have been implemented and integrated on a prototype software package for the automated analysis and design of analogue circuits.     

Symbolic Analysis of Nullor-Based Circuits with the Two-Graph Technique

Symbolic analysis is a powerful tool which accelerates the electronic design process by providing insight about the behavior of a circuit. Recently, the analysis and synthesis of electronic circuits with nullors have received considerable attention. This is due to the fact that nullors are very flexible and versatile active elements. Very efficient analysis methods, such as nodal analysis, Coates flow graphs, and two-graphs are proposed in the literature and are widely used. It has arguably been reported (because it does not generate vanishing terms in the symbolic network functions) that the last cited analysis method may be considered as the most promising. Actually, using the two-graph method, symbolic transfer functions can be calculated via either signal flow graphs and Mason’s formula, without any restriction on the type of the sources (dependent and independent), or the spanning tree enumeration method for RLC circuits with nullor equivalent circuits of independent voltage sources and all types of controlled sources. In this paper we propose a new method for symbolic analysis of circuits with nullors using the two-graph method in both versions, i.e. signal flow graphs and enumeration of spanning trees. This new method helps us to see distinctly the relationships between various circuit components (for the method using the signal flow graph) and enables us to calculate the symbolic network functions without the excess terms (for the method using the enumeration of spanning trees).     

Symbolic pole/zero calculation using SANTAFE

The aim of symbolic analysis is to gain insight into circuit behavior. To study the behavior of analog circuits, the locations of the poles and zeros have to be known. Unfortunately, no general method exists to calculate the poles and zeros symbolically for polynomials of degree greater than four from transfer functions in coefficient form. The CAD tool SANTAFE (Symbolic Analysis of Transfer Functions) applies the signal-flow graph method, which permits to keep the result in a factorized or partially factorized form. The graphic view provided by a signal-flow graph offers insight into the internal interactions between the circuit elements and, as will be demonstrated, enables the user to perform circuit knowledge-based approximations. A novel procedure based on symbolic Newton-iteration, accurately calculates high-order transfer functions in the desired pole/zero form. Another special routine, based on element weight ratios rather than numerical values, enables the simplification of large symbolic expressions without numerical values for each parameter. With the program SANTAFE, even large networks can be analyzed symbolically. This will be shown with an example of a wide band BiCMOS operational amplifier     

Approximate Symbolic Analysis of Hierarchically Decomposed Analog Circuits

This paper presents a methodology for the symbolic analysis of large analog integrated circuits using a hierarchical approach. The drawbacks of previous approaches are solved by the introduction of error-controlled approximation strategies. A proper modeling methodology through the different hierarchical levels allows to combine the optimum techniques for generation of the symbolic expressions and the most efficient numerical techniques for error control. These approximation strategies together with mechanisms for partitioning and union of blocks through the hierarchy yield optimum results in terms of speed, accuracy and complexity of the symbolic results.     

Pathological equivalents of CMs and VMs with multi-outputs

New models based on pathological elements are introduced to describe the behavior of current- and voltage-mirrors with multi-outputs. To do so, simple element stamps for a current-controlled current source and a voltage controlled voltage source have been deduced. The difference of the new stamps with those reported in the literature is that herein, input–output impedances of the controlled sources are taken into account. As a consequence, not only the behavior of controlled sources can be directly introduced on the admittance matrix without extra variables, but also the new stamps have few nonzero elements. Relying on these stamps, the modeling of current- and voltage-mirrors with multi-outputs based on pathological elements is generated. Gain and parasitic elements associated to each input–output terminal of current- and voltage-mirrors are considered in the proposed models. Due to the simplicity of our models, a reduced and sparse system of equations is obtained for analog circuits containing current- and/or voltage-mirrors. As a consequence, the computational complexity used in the solution of the system of equations is diminished when recursive determinant-expansion techniques are applied. The usefulness of the models to realize symbolic analysis of analog circuits is demonstrated and compared with nullor-based models of current- and voltage-mirrors previously reported. Furthermore, these models can be used either at the transistor or circuit level of abstraction in order to compute fully-symbolic small-signal characteristics of analog circuits.     

A Symbolic Pole/Zero Extraction Methodology Based on Analysis of Circuit Time-Constants

This paper introduces a methodology for symbolic pole/zero extraction based on the formulation of the time-constant matrix of the circuits. This methodology incorporates approximation techniques specifically devoted to achieve an optimum trade-off between accuracy and complexity of the symbolic root expressions. The capability to efficiently handle even large circuits will be demonstrated through several practical circuits.     

TAO: regular expression-based register-transfer level testabilityanalysis and optimization

In this paper, we present testability analysis and optimization (TAO), a novel methodology for register-transfer level (RTL) testability analysis and optimization of RTL controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits (ASICs), application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. We also augment TAO with a design-for-test (DFT) framework that can provide a low-cost testability solution by examining the tradeoffs in choosing from a diverse array of testability modifications like partial scan or test multiplexer insertion in different parts of the circuit. Test generation is symbolic and, hence, independent of bit width. Experimental results on benchmark circuits show that TAO is very efficient, in addition to being comprehensive. The fault coverage obtained is above 99% in all cases. The average area and delay overheads for incorporating testability into the benchmarks are only 3.2% and 1.0%, respectively. The test generation time is two-to-four orders of magnitude smaller than that associated with gate-level sequential test generators, while the test application times are comparable     

Analog circuit design optimization based on symbolic simulation andsimulated annealing

A methodology for the automatic design optimization of analog integrated circuits is presented. A non-fixed-topology approach is realized by combining the optimization program OPTIMAN with the symbolic simulator ISAAC. After selecting a circuit topology, the user invokes ISAAC to model the circuit. ISAAC generates both exact and simplified analytic expressions, describing the circuit's behavior. The model is then passed to the design optimization program OPTIMAN. This program is based on a generalized formulation of the analog design problem. For the selected topology, the independent design variables are automatically extracted and OPTIMAN sizes all elements to satisfy the performance constraints, thereby optimizing a user-defined design objective. The global optimization method used on the analytic circuit models is simulated annealing. Practical examples show that OPTIMAN quickly designs analog circuits, closely meeting the specifications, and that it is a flexible and reliable design and exploration tool     

A new multi-valued neural network for the extraction of lumped models of analog circuits

A novel identification technique for lumped models of general distributed circuits (i.e. microwave transmission lines, monolithic integrated circuits and filters) is presented. The approach is based on a hybrid multi-valued neuron neural network with a modified layer and learning process, whose convergence allows the validation of the approximated lumped model. The modified layer is generated by symbolic analysis of the model under exam. The inputs of the neural network are geometrical parameters, while the outputs represent the estimation of the lumped circuit parameters.     

Influence of transistor parameters on the noise margin of organic digital circuits

The concept of noise margin is crucial in the design and operation of digital logic circuits. Analytical expressions for the transfer curves of an inverter based on two depletion-mode p-type organic thin-film transistors (OTFTs) were calculated. Based on these expressions, the values for the noise margin of organic-based inverters were calculated. In this paper, the influence of the OTFT parameters on the noise margin is presented. Knowing that statistical variations of the transistor parameters are inherent to OTFT technology, these statistical variations are also taken into account. Finally, a circuit yield analysis is presented.     

Matrix Approximation Techniques for Symbolic Extraction of Poles and Zeros

Several recently published approaches to symbolic pole/zero analysis of analog circuits exploit the order reduction effect of Simplification Before Generation (SBG) techniques [1]. SBG methods allow the extraction of symbolic expressions for poles and zeros by computing local low-order approximations of transfer functions whose roots can be calculated analytically. In this article we present a new matrix-based SBG method for pole/zero analysis which simplifies a symbolic generalized eigenvalue problem with respect to a selected root. The method uses a fast linear error estimation formula based on eigenvalue sensitivities to obtain a term ranking. Accurate and efficient error control is achieved by tracking eigenvalue shifts numerically using an iterative generalized eigenvalue solver. The new algorithm is capable of computing real and complex dominant as well as unobservable poles and zeros.     

A Method of Transformation from Symbolic Transfer Function to Active-RC Circuit by Admittance Matrix Expansion

Active-RC circuits containing 2-terminal linear passive elements and ideal transistors or operational amplifiers are derived from symbolic voltage or current transfer functions by admittance matrix transformations without any prior assumption concerning circuit architecture or topology. Since the method is a reversal of symbolic circuit analysis by Gaussian elimination applied to a circuit nodal admittance matrix, it can generate all circuits using the specified elements that possess a given symbolic transfer function. The method is useful for synthesis of low-order circuits, such as those used for cascade implementation, for deriving alternative circuits with the same transfer function as an existing circuit or for realizing unusual transfer functions, as may arise, for example, where a transfer function is required that contains specific tuning parameters     

Symbolic Macromodeling for Statistical Simulation of Operational Amplifiers

Symbolic circuit simulator is traditionally applied to the small-signal analysis of analog circuits. This paper establishes a symbolic behavioral macro-modeling method applicable to both small-signal and large-signal analysis of general two-stage operational amplifiers (op-amps). The proposed method creates a two-pole parametric macromodel whose parameters are analytical functions of the circuit element parameters generated by a symbolic circuit simulator. A moment matching technique is used in deriving the analytical model parameter. The created parametric behavioral model can be used for op-amps performance simulation in both frequency and time domains. In particular, the parametric models are highly suited for fast statistical simulation of op-amps in the time-domain. Experiment results show that the statistical distributions of the op-amp slew and settling time characterized by the proposed model agree well with the transistor-level results in addition to achieving significant speedup.     

Symbolic analysis methods and applications for analog circuits: atutorial overview

This tutorial paper gives an overview of the history and present state of the art in symbolic analysis of electronic circuits at the so-called circuit level. Symbolic analysis is defined as a technique generating a closed-form analytic expression for a circuit characteristic with the circuit's elements represented by symbols. Such analytic information complements the results from numerical simulations. The paper then describes the different application areas of symbolic analysis for the design of analog circuits. Symbolic analysis is mainly used as a means to obtain insight into a circuit's behavior, to generate analytic models for automated circuit sizing, and in applications requiring the repetitive evaluation of circuit characteristics. Next, the present capabilities and limitations of symbolic analysis, both in functionality and efficiency, are discussed. The major symbolic analysis methods are presented, and algorithmic details are provided for symbolic approximation, hierarchical decomposition, and symbolic distortion analysis. Finally, existing symbolic simulators are compared, and directions for future research are pointed out     

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits

A symbolic fault simulator is integrated in a Genetic Algorithm (GA) environment to perform Automatic Test Pattern Generation (ATPG) for synchronous sequential circuits. In a two phase algorithm test length and fault coverage as well are optimized. Furthermore, not only the Single Observation Time Test Strategy is supported, but also test patterns with respect to the Multiple Observation Time Test Strategy are generated. However, there are circuits that are hard to test using random pattern sequences, even if these sequences are genetically optimized. Thus, deterministic aspects are included in the GA environment to improve fault coverage. Experiments demonstrate that both a priori time consuming strategies, the symbolic simulation approach and the GA, can be combined at reasonable costs: Tests with higher fault coverages and considerably shorter test sequences than previously presented approaches are obtained.