Oscillation-based test in oversampled ΣΔ modulators

This paper discusses a way of applying the oscillation-based test (OBT)/oscillation-based built-in-self test concept to oversampled ΣΔ modulators, exploiting previous experience coined through the implementation of OBT in SC integrated filters. Analytical and simulation results demonstrate that it is always feasible to find out an OBT configuration for a typical discrete-time second-order modulator structure without adding a substantial extra circuitry, but only resorting to local feedback loops. A feedback strategy can be chosen providing enough freedom to force oscillations, which can be worthwhile for testing purposes. The selected oscillation parameters allow us to establish criteria for a high fault coverage.     

Oscillation-based test in digital shapers

We address the problem of testing digital shapers used for nuclear spectroscopy. Particularly, we propose a solution based on the oscillation-based test (OBT) for testing the finite impulse response (FIR) filters of the shaper. The OBT strategy developed here exploits the natural partition of the system in high-pass and low-pass sections for implementing two different non-linear oscillators. The oscillation parameters are obtained in advance using two different approaches: one based on the filter signal flow-graph; the other based on the describing function technique. The fault simulation results show high fault coverage and acceptable test time. Additionally, we suggest the use of this test strategy in a BIST environment, because it does not need resources for pattern generation and presents both low system intrusion and low hardware overhead.     

Oscillation-based test in bandpass oversampled A/D converters

This paper extends a study performed by the authors in previous papers dealing with the OBT approach applied to low-pass modulators ‘Microelectron. J. 33/10 (2002) 799’, showing herein the specific features associated to the bandpass case. A practical feedback strategy will be proposed in order to built an effective oscillator, which can be valuable for testing purposes. Critical points of the proposed OBT solution will be considered in order to establish useful guidelines to apply this test approach to generic bandpass ΣΔ modulators.     

Self-Timed Boundary-Scan Cells for Multi-Chip Module Test

This paper presents a self-timed scan-path architecture, to be used in a conventional synchronous environment, and with basic application in digital testing and interconnections checking in a Smart-Substrate MCM (T.A. García, A.J. Acosta, J.M. Mora, J. Ramos, and J.L. Huertas, Self-Timed Boundary-Scan Cells for Multi-Chip Module Test, Proceedings of IEEE VLSI Test Symposium, April 1998, pp. 92–97). With this approach, the potential advantages of self-timed asynchronous systems are explored for their practical use in a classical MCM testing application. Three different self-timed asynchronous boundary scan cells are proposed (Sense, Drive and Drive & Sense cells) that can be connected to form a self-timed scan-path. The main advantage is that no global test clock is needed, avoiding clock skew and synchronization faults in test mode, and hence, a more reliable test process is achieved. These cells have been designed and integrated in active substrates, building several boundary-scan configurations and being fully compatible with the ANSI/IEEE 1149.1 Standard. The experimental results, as well as their comparison with their synchronous counterparts, show the feasibility of the proposed self-timed approach for testing interconnections in a MCM.     

模拟电路的振荡测试技术

集成电路设计和制造技术的发展给电路测试带来了巨大的挑战,其中模拟电路的测试是电路测试的难点.目前在这一领域有许多致力于降低测试难度,节约测试成本的研究.介绍了一种称为"振荡测试"的模拟电路测试技术,从振荡电路的构造、测试响应的测量和分析等方面综述了振荡测试技术的研究现状,同时总结了振荡测试技术的优点,分析了当前存在的局限性,并对将来的发展进行了展望.     

Investigation of the optimum oscillation frequency value towards increasing the efficiency of OBIST approach

This paper is mainly focused on the investigation of the optimum value of the oscillation frequency in the Oscillation-based Built-In Self Tests (OBIST). It has been assumed that the proper frequency value might increase the test efficiency in covering hard-detectable short faults in analog integrated circuits (ICs) designed in nanoscale technology. In our research, active analog filters designed in 0.35 μm and 90 nm CMOS technologies were used as circuits under test (CUT). The tested circuits were brought to oscillation at different oscillation frequencies by varying the values of passive devices. The achieved results prove that the efficiency of OBIST approach can be increased in this way.     

An On-Chip Spectrum Analyzer for Analog Built-In Testing

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 m technology are presented to demonstrate the feasibility of the proposed BIT technique.Marcia G. Mendez-Rivera was born in Irapuato, Mexico in 1972. She received the Communications and Electronics Engineering Degree from the Universidad de Guanajuato, Guanajuato, Mexico. in 1996, the M.Sc. degree from the Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico in 1998 and the M.Sc. from Texas A&M University, College Station in 2002. Her research interest is in the design and fabrication of analog and mixed-signal circuits.Alberto Valdes-Garcia born in 1978, grew up in San Mateo Atenco, Mexico. He received the B.S. in Electronic Systems Engineering degree from the Monterrey Institute of Technology (ITESM), Campus Toluca, Mexico in 1999 (with honors as the best score from all majors). Since the fall of 2000 he has been working towards the Ph.D. degree at Analog and Mixed-Signal Center (AMSC), Texas A&M University. During the spring and summer of 2000 he was a Design Engineer with Motorola Broadband Communications Sector. In the summer of 2002 he was with the Read Channel Design Group at Agere Systems where he investigated wide tuning range GHz LC VCOs for mass storage applications. During the summer of 2004 he was with the Mixed-Signal Communications IC Design Group at the IBM T. J. Watson Research Center, where worked on design and analysis of SiGe power amplifiers for millimeter wave radios. Since the fall of 2001 he has been a Semiconductor Research Corporation (SRC) research assistant at the AMSC working on the development of analog built-in testing techniques. Since the fall of 2000, Alberto has been the recipient of a scholarship from the Mexican National Council for Science and Technology (CONACYT). He represented Mexico in the 1994 Odyssey of the Mind World Creativity Contest and in the 1997 International Exposition for Young Scientists. His present research interests include built-in testing implementations for analog and RF circuits, system level design for wireless receivers and RF circuit design for UltraWideBand (UWB) communications.Jose Silva-Martinez was born in Tecamachalco, Puebla, México. He received the B.S. degree in electronics from the Universidad Autónoma de Puebla, México, in 1979, the M.Sc. degree from the Instituto Nacional de Astrofísica Optica y Electrónica (INAOE), Puebla, México, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven Belgium in 1992. From 1981 to 1983, he was with the Electrical Engineering Department, INAOE, where he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autonoma de Puebla, where he remained until 1993; He was a co-founder of the graduate program on Opto-Electronics in 1992. From 1985 to 1986, he was a Visiting Scholar in the Electrical Engineering Department, Texas A&M University. In 1993, he re-joined the Electronics Department, INAOE, and from May 1995 to December 1998, was the Head of the Electronics Department; He was a co-founder of the Ph.D. program on Electronics in 1993. He is currently with the Department of Electrical Engineering (Analog and Mixed Signal Center) Texas A&M University, at College Station, where He holds the position of Associate Professor. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical application. Dr. Silva-Martinez has served as IEEE CASS Vice President Region-9 (1997–1998), and as Associate Editor for IEEE Transactions on Circuits and Systems part-II from 1997–1998 and May 2002–December 2003. Since January 2004 is serving as Associate Editor of IEEE TCAS Part-I. He was the main organizer of the 1998 and 1999 International IEEE-CAS Tour in region 9, and Chairman of the International Workshop on Mixed-Mode IC Design and Applications (1997–1999). He is the inaugural holder of the TI Professorship-I in Analog Engineering, Texas A&M University. He was a co-recipient of the 1990 European Solid-State Circuits Conference Best Paper Award.Edgar Sánchez-Sinencio was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, CA, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 1966, 1970, and 1973, respectively. In 1974 he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983 he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983-1984. He is currently the TI J Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He was an Associate Editor for IEEE Trans. on Circuits and Systems, (1985–1987), and an Associate Editor for the IEEE Trans. on Neural Networks. He is the former Editor-in-Chief of the Transactions on Circuits and Systems II. He is co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold 1984), and co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems (IEEE Press 1999). In November 1995 he was awarded an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico. The first honorary degree awarded for Microelectronic Circuit Design contributions. He is co-recipient of the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the co-recipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He was the IEEE Circuits and Systems Society, Representative to the Solid-State Circuits Society (2000–2002). He is presently a member of the IEEE Solid-State Circuits Fellow Award Committee. His present interests are in the area of RF-Communication circuits and analog and mixed-mode circuit design. He is an IEEE Fellow Member since 1992.     

1300 V, 2 ms pulse inductive load switching test circuit with 20 ns selectable crowbar intervention

A non destructive inductive load switching (ILS) test apparatus with the capability of delivering high current pulses with a maximum 2 ms duration under a 1300 V supply is presented in this work. The system is also provided with a fast crowbar whose intervention is programmable with a 20 ns resolution and is intended to perform tests on power devices driving generic inductive loads. This kind of test is commonly used for quality control and prototype verification in power devices industry [Busatto G, Cascone B, Fratelli L, Balsamo M, Iannuzzo F, Velardi F. Non-destructive high temperature characterization of high-voltage IGBTs. Microelectron Reliab 2002;42(9–11):1635–40]. The high resolution crowbar intervention allows an immediate steering of the current away from the Device Under Test (DUT) after the failure event. In this way device damage is minimized so as to have a better understanding of the exact position of the failure, an essential parameter to infer the reasons that caused it [Trivedi M, Shenai K. Failure mechanisms of IGBTs under short-circuit and clamped inductive switching stress. IEEE Trans Power Electron 1999;14(1):108–16; Breglio G, Irace A, Riccio M, Spirito P, Hamada K, Nishijima T, et al. Detection of localized UIS failure on IGBTs with the aid of lock-in thermography. Microelectron Reliab 2008;48(8–9):1432–4].     

Overlapping block transform: window design, fast algorithm, and animage coding experiment

A window design and fast algorithm for the overlapping block transform (OBT) of size N×L are presented. The presented algorithm for the OBT reduces the calculation complexity to an N×N transform with a fast algorithm and a simple preprocessing including windowing. A signal-independent window optimization strategy is introduced for image coding application. Results for a first-order Markov model and an image coding experiment show, that the coding gains of the optimized OBTs increase and blocking effects decrease with increasing window length L. A comparison with DCT-coding shows that the OBT, which has a slightly increased realization complexity, provides higher coding gain and a significant blocking effect reduction     

Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems

Recent years have seen the emergence of droplet-based microfluidic systems for safety-critical biomedical applications. In order to ensure reliability, microsystems incorporating microfluidic components must be tested adequately. In this paper, we investigate test planning and test resource optimization for droplet-based microfluidic arrays. We first formulate the test planning problem and prove that it is NP-hard. We then describe an optimization method based on integer linear programming (ILP) that yields optimal solutions. Due to the NP-hard nature of the problem, we develop heuristic approaches for optimization. Experimental results indicate that for large array sizes, the heuristic methods yield solutions that are close to provable lower bounds. These heuristics ensure scalability and low computation cost. This research was supported in part by the National Science Foundation under grant number IIS-0312352. A preliminary version of this paper appeared in Proc. European Test Symposium. pp. 72–77, 2004 Fei Su received the B.E. and the M.S. degrees in automation from Tsinghua University, Beijing, China, in 1999 and 2001, respectively, and the M.S. degree in electrical and computer engineering from Duke University, Durham, NC, in 2003. He is now a Ph.D. candidate in electrical and computer engineering at Duke University. His research interests include design and testing of mixed-technology microsystems, electronic design automation, mixed-signal VLSI design, MEMS modeling and simulation. Sule Ozev received her B.S. degree in Electrical Engineering at Bogazici University in 1995, and her M.S. and Ph.D. degrees in Computer Science and Engineering at University of California, San Diego in 1998 and 2002 respectively. Since 2002, she has been a faculty member at Duke University, Electrical and Computer Engineering Department. Her research interests include RF circuit analysis and testing, process variability analysis, and mixed-signal testing. Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively, all in Computer Science and Engineering. He is now Associate Professor of Electrical and Computer Engineering at Duke University. Dr Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award and the Office of Naval Research Young Investigator award. His current research projects include: design and testing of system-on-chip integrated circuits; design automation of microfluidics-based biochips; microfluidics-based chip cooling; distributed sensor networks. Dr Chakrabarty has authored three books Microelectrofluidic Systems: Modeling and Simulation (CRC Press, 2002), Test Resource Partitioning for System-on-a-Chip (Kluwer, 2002), and Scalable Infrastructure for Distributed Sensor Networks (Springer, 2005) 3/4 and edited the book volume SOC (System-on-a-Chip) Testing for Plug and Play Test Automation (Kluwer 2002). He has published over 200 papers in journals and refereed conference proceedings, and he holds a US patent in built-in self-test. He is a recipient of best paper awards at the 2005 IEEE International Conference on Computer Design and 2001 IEEE Design, Automation and Test in Europe (DATE) Conference. He is also a recipient of the Humboldt Research Fellowship, awarded by the Alexander von Humboldt Foundation, Germany. Dr Chakrabarty is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and System I, ACM Journal on Emerging Technologies in Computing Systems, and an Editor of Journal of Electronic Testing: Theory and Applications (JETTA). He a member of the editorial board for Sensor Letters and Journal of Embedded Computing and he serves as a subject area editor for the International Journal of Distributed Sensor Networks. He has also served as an Associate Editor of IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. He is a senior member of IEEE, a member of ACM and ACM SIGDA, and a member of Sigma Xi. He serves as Vice Chair of Technical Activities in IEEE’s Test Technology Technical Council, and is a member of the program committees of several IEEE/ACM conferences and workshops. He served as the Program Co-Chair for the 2005 IEEE Asian Test Symposium.     

Testing Biquad Filters under Parametric Shifts Using X-Y Zoning

Testing mixed-signal circuits is a difficult task due to defect modeling challenges, observability and controllability restrictions and ATE bandwidth limitations. In this paper, the X-Y Zoning test of a Biquad filter is addressed to select the optimal excitation frequency and the best partition of the X-Y plane. Thus we obtain the best sensitivity of the BIST scheme to parametric shifts of the parameters defining the filter. The study has been particularized to shifts in the natural frequency f₀ of the Biquad filter. Analytical results on the best input as well as the best partition of the observed X-Y Lissajous plots are obtained. Extensive MATLAB simulations validate the proposal, which has also been validated experimentally. For these experiments, multiple implementations of the Biquad with nominal and shifted parameters have been performed using a commercial Field Programmable Analog Array (FPAA). The experimental measures show good correlation with the analytical expressions and the simulations performed, and validate the proposed testing methodology.Ricard Sanahuja is Associate Professor in the Electronic Engineering Department of the Universitat Politècnica de Catalunya in Manresa (Barcelona), with teaching responsibilities in microelectronics. His current research interest is centred in Mixed-Signal Testing which offers the bases of his Ph.D. Sanahuja received his Electronic Engineering degree in 1997 from the Universitat Autònoma de Barcelona and Universitat Politècnica de Catalunya.Victor Barcons is Associate Professor in the Electronic Engineering Department of the Universitat Politècnica de Catalunya in Manresa (Barcelona), with teaching responsibilities in analog electronics. His current research interest are in Mixed-Signal Testing and Vibration Test Control Systems. Barcons received his Industrial Engineering degree in 1994 from the Universitat Politècnica de Catalunya.Luz Balado received the degree in Industrial Engineering in 1980 from the Universitat Politècnica de Catalunya (UPC) and the Doctor degree in Electronic Engineering in 1986. She is presently Associate Professor at the Electronic Engineering Department of the UPC where teaches Electronics and Electronic Instrumentation and is involved in its Microelectronics and Test research Group. Her main research interests are Design and Test of digital and mixed-signal circuits and defect modeling.Joan Figueras received his Ph.D. degrees from the Universitat Politecnica de Catalunya (UPC), and the University of Michigan in Ann Arbor, Mich. where he was a Fulbright Scholar and worked in the Systems Engineering Laboratory. Currently he is Professor at the the Electronics Engineering Dpt. of the UPC in Barcelona, Spain, with teaching and research responsibilities in the area of electronics and VLSI design. His present research interests include emerging design and test techniques for high performance and low power electronic circuits. He is at present, member of the Editorial Board of the Journal of Electronic Testing (JETTA), Editor of a special issue of the IEEE Transactions on Computer Aided Design, and Chair of the European IEEE Test Technology Technical Council.     

Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model

This paper presents new test methods for nonlinear Analog and Mixed-Signal (AMS) circuits which use a pseudorandom signal to test multiple Devices Under Test (DUTs) accurately. The goal of the studies presented in this paper is to understand the behaviors of nonlinear AMS circuits in a low-cost test environment and to develop the algorithm to extract the performance information of the DUTs using simple test measurements. The extracted information is then used to estimate the various specifications of DUTs. In order to achieve this goal, we analyze the behaviors of AMS circuits using a Volterra series model, and investigate the stochastic properties of the pseudorandom signals to develop the efficient performance characterization algorithms. The mathematical theory and experimental results are presented to validate the presented test methods.     

Applying the Oscillation Test Strategy to FPAA’s Configurable Analog Blocks

This paper presents the application of the oscillation test methodology as an alternative to test configurable analog blocks of Field Programmable Analog Arrays. The blocks of the device under test are first configured to behave as oscillators. Then, the output frequency and amplitude are observed to obtain the signature of the fault-free circuit. During test, this signature is compared to the actual output signal. Experimental results show the effectiveness of the method in detecting parametric and large deviation faults of the tested components.A paper based on this work was presented at the Fourth IEEE Latin American Test Workshop, Natal, Brazil, February 2003.Tiago Roberto Balen was born in Erechim, Brazil, in 1979. He received the Electrical Engineering degree from the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil in 2004. At present, he is M.Sc. student in the Electrical Engineering Department and works in the Prototyping and Test Laboratory at UFRGS. His research interests include analog and mixed-signal design and test, built-in self-test and design-for-testability. He has published papers on FPAA testing in important conferences, such as the VLSI Test Symposium (VTS) and the International Test Conference (ITC).Antonio Andrade, Jr., received the Electrical Engineering degree from the Universidade Federal da Bahia (UFBA), Salvador, Brazil, in 2003, and is currently pursuing the M.Sc. degree at Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil. His experience as a researcher includes the design of a temperature controller using thermo-resistive sensors and FPGA prototyping, at the Instrumentation Laboratory in UFBA, in 2001, a 2-month scholarship from Laboratorio Nacional de Luz Sincrotron (LNLS), Campinas, Brazil, in 2002, and 2 years as a graduate student at the Prototyping and Test Laboratory, at UFRGS. His primary research topics include Mixed-Signal Circuit and Systems Testing as well as fast system prototyping in platforms as FPGAs and FPAAs, having published papers in important conferences, such as the VLSI Test Symposium (VTS) and International Test Conference (ITC), in the field of FPAA testing.Florence Azaïs received the Ph.D. degree in electrical engineering from the University of Montpellier, France in 1996. She is currently working in the Microelectronics department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as a researcher of the National Council of Scientific Research (CNRS). Since 1993, she has been interested in the general domain of test and reliability of integrated circuits and systems. Her main research interests include fault modeling, analog and mixed-signal circuit testing, MEMS testing, reliability and failure analysis of integrated systems. She has authored or co-authored over 80 international papers on these topics. She also served as a member of the Program Committee of several international conferences (DATE, ICCD, ETS, IMSTW, LATW).Marcelo Lubaszewski received the Electrical Engineering and M.Sc. degrees from the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1986 and 1990, respectively. In 1994, he received the Ph.D. degree from the Institut National Polytechnique de Grenoble (INPG), France. In 2001, he joined the Laboratoire dInformatique, Robotique et Microélectronique de Montpellier in France as an Invited Researcher for 3 months and, in 2004, the Instituto de Microelectrónica de Sevilla (IMSE) in Spain for 1 year. He is currently with UFRGS, where he has been an Associate Professor since 1990. His primary research interests include design and test of mixed-signal, micro-electro-mechanical and core-based systems, self-checking and fault-tolerant architectures, and computer-aided testing. He has published over 150 papers in international journals and conferences on these topics. Dr. Lubaszewski has served as the general chair or program chair of the Symposium on Integrated Circuits and Systems Design (SBCCI) and of the Latin American Test Workshop (LATW), and as a member of the Organizing or the Program Committee of the VLSI Conference, the International Mixed-Signals Testing Workshop, the Asian Test Symposium, the European Design and Test Conference, the Design of Complex Integrated Systems Conference, the European Test Symposium and the GHz/Gbps Test Workshop. He has also served as a Guest Editor of the Journal of Electronic Testing: Theory and Applications and as an Associate Editor of the Design and Test of Computers Magazine.Michel Renovell is head of the Microelectronics Department at LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier). His research interests include: Fault modeling, Analog testing and FPGA testing. He is Vice-Chair of the IEEE TTTC (Test Technology Technical Committee). He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. Michel has been General Chair of the International Mixed Signal Testing Workshop IMSTW2000, the Field Programmable Logic Conference FPL2002 and the European Test Symposium ETS2004.     

Application of Representation Theory to Dual-Mode Microwave Bandpass Filters

This paper discusses the physics behind the operation of dual-mode bandpass filters from a field theoretical point of view. It is argued that the two degenerate modes of the empty dual-mode cavity, commonly taken as the vertical and horizontal polarizations, become nonphysical when coupling and tuning elements are inserted. Instead, the original degenerate modes are rotated, or modified in a complex way, to generate two new modes whose characteristics depend on the coupling and tuning elements. It is shown that the tuning elements, as placed in existing dual-mode filter designs, act as both tuning and coupling elements. A working dual-mode filter can be designed with only “tuning” elements present. A physical representation of dual-mode filters in terms of the eigenresonances of the dual-mode cavities, with the tuning and coupling elements present, is introduced. Two fourth-order dual-mode rectangular cavity filters with the same response in the passband and its vicinity are also presented to demonstrate the similar role played by “tuning” and coupling elements in dual-mode cavities. The first filter uses only “tuning” elements, while the second is based only on “coupling” elements.      

On-Chip Evaluation of Oscillation-Based-Test Output Signals for Switched-Capacitor Circuits

This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approach.     

J750到BC3192测试程序转换方法

由于不同测试系统上测试资源的差异,即便是对同一个被测器件的测试程序也不相同。将测试程序从一种测试系统移植到另一个系统上,可以避免测试重复开发,缩短产品开发周期,提高测试效率和灵活性。J750是目前国内装机量较大的进口测试系统,BC3192是国产的新型测试系统,本文介绍了一种测试程序从J750到BC3192转换的方法,用IC卡测试程序做实验,证明该方法是可行的。     

The self-formatting barrier characteristics of Cu–Mg/SiO2 and Cu–Ru/SiO2 films for Cu interconnects

To substitute or to supplement diffusion barrier as reducing lateral dimension of interconnects, the alloying Mg and Ru to Cu was investigated as a self-formatting barrier in terms of their resistivity, adhesion, and barrier characteristics After annealing at 400 °C for 30 min, the resistivities of the Cu–0.7 at%Mg alloy and Cu–2.2 at%Ru alloy were 2.0 μΩ cm and 2.5 μΩ cm, respectively, which are comparable to that of Cu films. The adhesion was investigated by means of a sandwiched structure using the four point bending test. The interfacial debonding energy, which represents the adhesion, of Cu–Mg/SiO₂ was over 5.0 J/m², while those of the Cu–Ru/SiO₂ and Cu/SiO₂ interfaces were 2.2 J/m² and 2.4 J/m², respectively. The barrier characteristics of the alloy films were also investigated by the time-dependent dielectric breakdown test, using a metal–oxide–semiconductor structure, under bias-temperature stress. It was shown that the alloying of Mg made the lifetime seven times longer, as opposed to the alloying of Ru which made it shorter.     

Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current

Wavelet transform has the property of resolving signal in both time and frequency unlike Fourier transform. In this work, we show that time-domain information obtained from wavelet analysis of supply current can be used to test the frequency specification of analog filters efficiently. The pole/zero locations in the frequency response of analog filters shift due to change in component values with process variations. It is essential to test the filters for the shift in frequency response and fix it during production test. Wavelet analysis of supply current can be a promising alternative to test frequency specification of analog filters, since it needs only one AC stimulus and is virtually unaffected by transistor threshold variation. Simulation results on two test circuits demonstrate that we can estimate pole/zero shift with less than 3% error using only one measurement, which requires about 18 measurements in the conventional technique.Swarup Bhunia received the undergraduate degree from Jadavpur University, Calcutta, India, and the Masters degree from the Indian Institute of Technology (IIT), Kharagpur. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Purdue University, West Lafayette, IN, USA. He has worked in the EDA industry on RTL synthesis and verification for about three years. His research interest includes design methodologies for high-performance low-power testable VLSI system, defect-based testing, noise analysis, and noise-aware design.Arijit Raychowdhury received the B.E. degree in 2001 in electronics and telecommunication engineering from Jadavpur University, India. He is currently pursuing the Ph.D. degree in electrical and computer engineering in Purdue University, West Lafayette, IN, USA. He has worked as an analog circuit designer in Texas Instruments India. His research interests include device/circuit design for scaled silicon and nonsilicon devices. He has received academic excellence awards in 1997, 2000, and 2001 and Messner Fellowship from Purdue University in 2002. Mr. Raychowdhury has been awarded the Best Student Paper Award in the IEEE Nanotechnology Conference, 2003.Kaushik Roy received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty, Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 250 papers in refereed journals and conferences, holds six patents, and is Co-Author of a book on Low Power CMOS VLSI Design (New York: Wiley). He was Guest Editor for a Special Issue on Low-Power VLSI in IEE Proceedings Computers and Digital Techniques (July 2002). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, AT&T/Lucent Foundation Award, Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, and 2003 IEEE Nano. He is on the Editorial Board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was Guest Editor for a Special Issue on Low-Power VLSI in IEEE DESIGN AND TEST (1994), and for the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).     

Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications

The long and complex procedure to test ADCs constitutes an important issue in the context of mixed-signal testing. To lower the testing costs, we propose shorter but less selective test flows solely based on spectral analysis. This paper investigates the efficiency that can be achieved using this approach and studies the influence of the ADC specifications on the efficiency of the proposed dynamic-only test flows.Florence Azaïs received the Ph.D. degree in electrical engineering from the University of Montpellier, France in 1996. She is currently working in the Microelectronics department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as a researcher of the National Council of Scientific Research (CNRS). Since 1993, she has been interested in the general domain of test and reliability of integrated circuits and systems. Her main research interests include fault modeling, analog and mixed-signal circuit testing, MEMS testing, reliability and failure analysis of integrated systems. She has authored or co-authored over 80 international papers on these topics. She also served as a member of the Program Committee of several international conferences (DATE, ICCD, ETS, IMSTW, LATW).Serge Bernard received the M.S. degree in Electrical Engineering from the University of Paris XI, France in 1998 and the Ph.D. degree in Electrical Engineering from the University of Montpellier, France in 2001. He is a researcher of the National Council of Scientific Research (CNRS) in the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM). His main research interests include Test, Design-For-Testability and Built-In-Self-Test for mixed-signal circuits and Design-For-Reliability for medical application ICs.Yves Bertrand is a Professor at the University of Montpellier (France). He works at the Microelectronics Department of the Laboratoire dAutomatique, Robotique et Microélectronique de Montpellier (LIRMM). Previously, Yves Bertrand worked in the field of solid-state physics and published several papers, especially on the photoemission of the semiconductors under synchrotron radiation. He joins the LIRMM in 1988. His research interests are principally, Fault Modeling, Design-For-Test and Built-In Self-Test for digital and mixed-signal analog/digital Integrated Circuits. He is author or co-author of about 200 papers in the field of solid-state physics and microelectronics. He is presently responsible for the CRTC (Centre de Ressources de Test du CNFM), which is the Common Test Resources Center for the French and European Universities.Mariane Comte took her Master of Engineering and Master of Sciences degrees in microelectronics engineering at INPG, (Institut National Polytechnique de Grenoble, National Engineering University Institution of Grenoble), France, in 2000. She carried out her Ph.D. studies at LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier, Computer Sciences, Robotics and Microelectronics Laboratory of Montpellier), France, working on Analog-to-Digital Converter testing, and received Ph.D. degree in microelectronics from the University of Montpellier, France, in 2003. After a post-doctoral fellow position at the Computer Design and Test Laboratory of NAIST (Nara Institute of Science and Technology), Japan, where she investigated on the detection of Gate-Oxide Shorts in Domino Logic cells, she is currently working as an assistant professor at the University of Montpellier. Her fields of interest spread from analog and mixed-signal testing to defect modeling.Michel Renovell is head of the Microelectronics Department at LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier). His research interests include: Fault modeling, Analog testing and FPGA testing. He is Vice-Chair of the IEEE TTTC (Test Technology Technical Committee). He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. Michel has been General Chair of the International Mixed Signal Testing Workshop IMSTW2000, the Field Programmable Logic Conference FPL2002 and the European Test Symposium ETS2004.     

Book Reviews

Book reviewed in this article:
Books: A Review of Selected Basic Speech Books Dealing with Speech-Communication: 1965–1969. J ames V. F ee
I nterpersonal C oumumcation in the m odern O rganization . By Ernest G. Bormann, William S. Howell, Ralph G. Nichols, and George L. Shapiro
T he G olden W eb . By Erik Barnouw
R eport W riting for B usiness . By Raymond V. Lesikar
S peech : S cience -A rt . By Elwood Murray, Gerald M. Phillips, and J. David Truby
D iffusion of A bstracting and I ndexing S ervices for G overnment -S ponsored R esearch . By Irving M. Klempner
V erbal L earning . By John Jung
T elevision and the N ews : A C ritical A ppraisal . By Harry J. Skornia
H ow C hildren L earn to S peak . By Maurice Sklar
A n A nnotated B ibliography of S tatistical S tylistics . Compiled and edited by Richard W. Bailey and Lubomir Dolezel.
A D ictionary of T erms and C oncepts in R eading , 2nd edition. Delwyn G. Schubert
G uide to G athering I nformation in F ace to F ace I nterviews . By Morris Balsky.