A single-chip GaAs RF transceiver for 1.9-GHz digital mobilecommunication systems

A 1.9-GHz single-chip GaAs RF transceiver has been successfully developed using a planar self-aligned gate FET suitable for low-cost and high-volume production. This IC includes a negative voltage generator for 3-V single voltage operation and a control logic circuit to control transmit and receive functions, together with RF front-end analog circuits-a power amplifier, an SPDT switch, two attenuators for transmit and receive modes, and a low-noise amplifier. The IC can deliver 22-dBm output power at 30% efficiency with 3-V single power supply, The new negative voltage generator operates with charge time of less than 200 ns, producing a low level of spurious outputs below -70 dBc through the power amplifier. The generator also suppresses gate-bias voltage deviations to within 0.05 V even when gate current of -144 μA flows. The IC incorporates a new interface circuit between the logic circuit and the switch which enables it to handle power outputs over 24 dBm with only an operating voltage of 3 V. This transceiver will be expected to enable size reductions in telephones for 1.9-GHz digital mobile communication systems     

A 5-GHz-band multifunctional BiCMOS transceiver chip for GMSKmodulation wireless systems

This paper reports the first multifunctional 0.4-μm BiCMOS-based transceiver chip developed for 5-GHz-band Gaussian minimum-shift keying modulation wireless systems. The chip integrates a low-noise radio-frequency amplifier, a down-mixer, and an intermediate-frequency (IF) amplifier in the down-converter path; an IF amplifier, a limiter, an up-mixer, and a buffer amplifier in the up-converter path; and a frequency doubler and a local oscillator amplifier in the local oscillator path. The chip featuring gain attenuation as well as standby mode operation uses a single 2.6-5.2-V bias voltage and dissipates 56 mW in receive mode and 66 mW in transmit mode. The transceiver chip size is 3.0×2.4 mm²     

A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications

This paper describes a single-chip RF transceiver LSI for 2.4-GHz-band Gaussian frequency shift-keying applications, such as Bluetooth. This chip uses a 0.18-/spl mu/m bulk CMOS process for lower current consumption. The LSI consists of almost all the required RF and IF building blocks: a transmit/receive antenna switch, a power amplifier, a low noise amplifier, an image rejection mixer, channel-selection filters, a limiter, a received signal strength indicator, a frequency discriminator, a voltage controlled oscillator, and a phase-locked loop synthesizer. The bandpass filter for channel selection was difficult to achieve since it operates at a low supply voltage. However, because large interference is roughly rejected at the output of the image rejection mixer and a wide-input-range bandpass filter with an optimized input bias is realized, the transceiver can operate at a supply voltage of 1.8 V. In the IF section, we adopted a circuit design using the minimum number of passive elements, resistors and capacitors, for a lower chip area of 10.2 mm/sup 2/.     

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMICfront-end with a low insertion loss switch

This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-μm standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.1 GHz and 1.8 V: a 5-dBm transmit power at a -1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA     

A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively     

Macromodels in the frequency domain analysis of microwave resonators

This paper describes a 1-V operation Bluetooth RF transceiver in 0.2-/spl mu/m CMOS SOI. The transceiver integrates a radio-frequency transmit/receive switch, an image-reject mixer, a quadrature demodulator, g/sub m/-C filters, an LC-tank voltage-controlled oscillator, a phase-locked loop synthesizer, and a power amplifier. The phase shifter in the quadrature demodulator is tuned dynamically to track the carrier-frequency drift allowed in the Bluetooth specification. The g/sub m/ cell in the filters uses depletion-mode pMOS transistors. In order to achieve 1-V operation, LC-tuned-folded and transistor-current-source-folded circuits are used in the RF and IF building blocks, respectively. In order to minimize power consumption, the current flowing through the circuit is optimally shared between the folded stages. A tuning circuit for the g/sub m/-C filters and a bias generation circuit ensure stable transceiver performance. The transceiver shows -77-dBm sensitivity at 0.1% bit error rate and consumes 33 and 53 mW from 1 V in the transmit and receive modes, respectively.     

A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wirelesscommunications networks

This paper concerns the design consideration, fabrication process, and performance results for an ultra-broadband, low-voltage, low-power, BiCMOS-based transceiver chip for cellular-satellite-LAN wireless communication networks. The transceiver chip incorporates an RF amplifier, a Gilbert down-mixer, and an IF amplifier in the receive path, and an IF amplifier, a Gilbert up-mixer, and an RF amplifier in the transmit path. For an RF frequency in the 1-10 GHz band and an IF frequency in the 100-1000 MHz band, the developed transceiver chip consumes less than 60 mW at 2 V, to yield a downconversion gain of 40 dB at 1 GHz and 10 dB at 10 GHz and an upconversion gain of 42 dB at 1 GHz and 11 dB at 10 GHz. To avoid possible start-up problems caused during “stand-by” to “enable” mode transition, a simple switching technique is employed for enabling either the receive or the transmit path, by changing the value of a reference voltage applied to both the down- and the up-mixers. While the developed transceiver chip exhibits the best performance for a dc supply voltage of 2 V, it shows a graceful degradation for a ±0.15 V voltage deviation. The transceiver's chip size is 1.04 mm×1.04 mm     

GaAsFET Mount Structure Design for 30-GHz-Band Low-Noise Amplifiers

This paper describes a GaAsFET mount design method for 30-GHz-band low-noise reflection-type amplifiers with the metal wall as a feedback circuit. Two examples of 30-GHz-band low-noise amplifiers are described; one with wide-band response and the other with high-gain response. The wide-band amplifier has 13-dB gain and 8.5-dB noise figure in the frequency range from 27.5 GHz to 29.1 GHz. The high gain amplifier has 15-dB gain and 9-dB noise figure in the frequency range from 27.7 GHz to 28.7 GHz. These results demonstrate the utility of this design approach.     

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.     

A 2.5-GHz BiCMOS transceiver for wireless LAN's

A BiCMOS transceiver intended for spread spectrum applications in the 2.4-2.5 GHz band is described. The IC contains a low-noise amplifier (LNA) with 14 dB gain and 2.2 dB NF in its high-gain mode, a downconversion mixer with 8 dB gain and 11 dB NF, and an upconversion mixer with 17 dB gain and P_{-1 dB} of +3 dBm out. An on-chip local oscillator (LO) buffer accepts LO drive of -10 dBm with a half-frequency option allowed by an on-chip frequency doubler. Power consumption from a single 3-V supply is 34 mA in transmit mode, 21 mA in receive mode, and 1 μA in sleep mode     

A Transceiver Front-End for Ultra-Wide-Band Applications

An integrated pulse based ultra-wide-band (UWB) transceiver front-end is presented in this paper. The pulse generator produces Gaussian modulated pulses satisfying Federal Communication Commission spectral mask with possibility for binary-phase shift keying modulation. The generated pulses have a bandwidth of 2 GHz from 3.1 to 5.1 GHz. The receiver front-end consists of an UWB low-noise amplifier (LNA). The transmit and receive paths are chosen by a transmit/receive (T/R) switch. The pulse generator, T/R switch and the LNA are integrated on a single chip and fabricated using 0.25-mum SiGe:C BiCMOS technology. The integrated circuit components are designed fully differential. The off-chip antenna and bandpass filter are single ended and connected to the T/R switch through a hybrid coupler     

5-GHz CMOS radio transceiver front-end chipset

Incorporating the direct-conversion architecture, a 5-GHz band radio transceiver front end chipset for wireless LAN applications is implemented in a 0.25-μm CMOS technology. The 4-mm² 5.25-GHz receiver IC contains a low noise amplifier with 2.5-dB noise figure (NF) and 16-dB power gain, a receive mixer with 12.0 dB single sideband NF, 13.7-dB voltage gain, and -5 dBm input 1-dB compression point. The 2.7-mm² transmitter IC achieves an output 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4-dB (image) sideband rejection by using an integrated quadrature voltage-controlled oscillator. Operating from a 3-V supply, the power consumptions for the receiver and transmitter are 114 and 120 mW, respectively     

A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-$mu$m CMOS Technology

A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18-mu m 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s operation, several techniques include active load inductive peaking and active feedback with current buffer in Cherry-Hooper topology. With these techniques, it reduces 30%-65% of the chip area comparing with on-chip inductor peaking method. This design also passes the interoperability test with switch fabric successfully. It provides 600- mV_pp differential voltage swing in driving 50-Omega output loads, 40-dB input dynamic range, 40-dB voltage gain, and 8-mV input sensitivity. The total power consumption is only 85 mW in 1.8-V supply and the chip feature die size is 700 mum times 400 mum.     

220GHz低噪声放大器研究

基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极（Common Base, CB）电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。     

A dual-mode 802.11b/bluetooth radio in 0.35-/spl mu/m CMOS

A fully integrated dual-mode CMOS transceiver tuned to 2.4 GHz consumes 65 mA in receive mode and 78 mA in transmit mode from a 3-V supply. The radio includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), and power amplifier, and is intended for use in 802.11b and Bluetooth applications. The Bluetooth receiver uses a low-IF architecture for higher level of integration and lower power consumption, while the 802.11b receiver is direct conversion. The receiver achieves a typical sensitivity of -88 dBm at 11 Mb/s for 802.11b, and -83 dBm for Bluetooth mode. The receiver minimum IIP3 is -8 dBm. Both transmitters use a direct-conversion architecture, and deliver a nominal output power of 0 dBm, with a power range of 20 dB in 2-dB steps.     

Class-AB high-swing CMOS power amplifier

A power amplifier for a loudspeaker and the earpiece of a telephone subset, integrated in the codec chip ARCOFI-SP (audio ringing codec filter featuring speakerphone function), are presented. The ARCOFI-SP is part of a subscriber telephone chip set. The analog section of the receive path comprises a low-noise programmable gain microphone amplifier with a maximum gain of 30-dB followed by a 16-b second-order sigma-delta analog-to-digital (A/D) converter. The analog section of the transmit path consists of two 16-b second-order sigma-delta D/A converters, one driving a pair of handset amplifiers for 200- Omega differential load and the other one a pair of loudspeaker amplifiers for 50- Omega differential load. The loudspeaker amplifier is described. A digital signal processor calculates the filter functions and handles frequency and tone generation. The amplifier has 1.2-mA quiescent current, 64-mA peak current, and >60 dB S/THD with 3.2-V output swing into a 25- Omega load.<>     

12-GHz-Band Low-Noise GaAs Monolithic Amplifiers

One- and two-stage 12-GHz-band low-noise GaAs monolithic amplifiers have been developed for use in direct broadcasting satellite (DBS) receivers. The one-stage amplifier provides a less than 2.5-dB noise figure with more than 9.5-dB associated gain in the 11.7-12.7-GHz band. In the same frequency band, the two-stage amplifier has a less tlhan 2.8-dB noise figure with more than 16-dB associated gain. A 0.5-µm gate closely spaced electrode FET with an ion-implanted active layer is employed in the amplifier in order to achieve a low-noise figure without reducing reproducibility. The chip size is 1 mm x 0.9 mm for the one-stage amplifier, and 1.5 mm x 0.9 mm for the two-stage amplifier.     

A fully integrated SOC for 802.11b in 0.18-/spl mu/m CMOS

A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.     

A 2.4-GHz CMOS transceiver for Bluetooth

A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for higher level of integration and lower power consumption. It achieves a sensitivity of -82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of -7 dBm. The direct-conversion transmitter delivers a GFSK modulated spectrum at a nominal output power of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz offset