A Reconfigurable Gaussian/Triangular Basis Functions Computation Circuit

A CMOS Gaussian/Triangular Basis functions computation circuit suitable for analog neural networks is proposed. The circuit can be configured to realize any of the two functions. The circuit can approximate these functions with relative root-mean-square error less than 1%. It is shown that the center, width, and peak amplitude of the dc transfer characteristic can be independently controlled. SPICE simulation results using 0.18 μ m CMOS process model parameters of TSMC18 technology are included. Muhammad Taher Abuelma'Atti was born in Cairo, Egypt, in 1942. He received the B.Sc. degree in Electrical Engineering in 1963 from the University of Cairo, Cairo, Egypt, the Ph.D. degree in 1979 and the Doctor of Science degree in 1999 both from the University of Bradford, Bradford, England. From 1963 to 1967, he worked at the Military Technical College in Cairo as a Teaching Assistant. He was with the Iron and Steel Company in Helwan, Cairo, from 1967 to 1973 as a Senior Electrical Engineer. From 1973 to 1976 he was with the College of Engineering, University of Riyadh, Saudi Arabia, as a Teaching Assistant. From 1980 to 1981, he worked with the Faculty of Engineering, University of Khartoum, Sudan, as an Assistant Professor, and from 1981 to 1982 he was with the College of Engineering, King Saud University, Riyadh, Saudi Arabia, as an Assistant Professor. In 1982 he joined the College of Engineering, University of Bahrain and in 1987 he became an Associate Professor. In 1991 he joined the College of Engineering Sciences, King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia, where he became a Full Professor in January 1995. Dr. Abuelma'Atti is the recipient of the 1994/1995 Excellence in Teaching Award and the 1995/1996 and 2000/2001 Excellence in Research Award. Both at King Fahd University of Petroleum and Minerals. Dr. Abuelma'Atti is a contributor to Encyclopedia of RF and Microwave Engineering, Kai Chang, Editor, (New York: John Wiley, 2005), Survey of Instrumentation and Measurement, S.A. Dyer, Editor, (New York: John Wiley, 2001), The Encyclopedia of Electrical and Electronic Engineering, J.G. Webster, Editor, (New York:John Wiley, 1999), and Selected Papers on Analog Fiber-Optic Links, E.I. Ackerman, C.H. Cox III and N.A. Riza, Editors, SPIE Milestone Series, (Washington: SPIE Optical Engineering Press, 1998). His research interests include problems related to analysis and design of nonlinear electronic circuits and systems, analog integrated circuits and active networks design. He is the author or co-author of over 500 journal articles and technical presentations. Abdullah Bakri Shwehneh was born in Aleppo Syria, in 1973. He received the B. Sc. degree in electrical engineering in 1998 from Sumy State University, Sumy, Ukraine. In 2001, he received the Postgraduate Diploma in Automatic Control from Aleppo State University, Aleppo, Syria. In 2001, he joined the “Electronic Brain Company for Computer and Electronics” as an Electronic & Computer Engineer and since 2002, he is with King Fahd University of Petroleum and Minerals (KFUPM), Dhahran, Saudi Arabia, as a Research Assistant. In June 2005 he obtained his Master of Science Degree in Analog Electronics from KFUPM. At present he is a Ph.D. student at KFUPM. His main interests are in Nonlinear circuits, VLSI Analog Design and Neural Networks hardware implementation.     

Adaptive Chip-Level Channel Estimation for IMT-DS System: DL and UL

In this paper, chip-level adaptive channel estimation has been explored by using LMS algorithm for wideband CDMA channel estimation. The expression for the optimum step-size is modified for fading channel estimation problem. In addition, a new method is proposed to obtain channel estimates with known pilot symbols which is found to give better results than other methods. For slow fading channels, like pedestrian channel, LMS estimator with no update mode is found to give satisfactory results. For fast fading channels, like vehicular channel, a common decision directed technique of channel estimation is modified to be used at chip-level in the downlink (DL). A novel despreader-respreader based channel estimator has been proposed to obtain uplink channel estimates at chip level which resolves the deficiencies of conventional methods. The performance of Rake receiver with proposed channel estimation schemes for IMT-DS system – a 3G mobile communication standard – is evaluated in terms of BER. S. Faisal A. Shah received the B.S. degree from NED University of Engineering and Technology, Karachi, Pakistan, in 1998 and the M.S. degree from King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia, in 2001, both in Electrical Engineering. From 2001 to 2004, he was a Lecturer in Electrical & Electronics Engineering Department, University of Sharjah, UAE. In September 2004, he joined the Electrical and Computer Engineering Department of University of Minnesota, USA, as a research assistant where he is currently pursuing the Ph.D. degree in Electrical Engineering. His research interests include ultra-wideband communication systems, adaptive signal processing and its application to wireless communication systems. Asrar U.H. Sheikh graduated from the University of Engineering and Technology, Lahore, Pakistan with first class honours and received his M.Sc. and Ph.D. degrees from the University of Birmingham, England, in 1966 and 1969 respectively. After completing teaching assignments in several countries, he returned to Birmingham as a Research Fellow in 1975. He worked at Carleton University from 1981 to 1997, first as Associate Professor and later as a Professor and Associate Chairman for Graduate Studies. He was the Founder Director of PCS Research Laboratory at Carleton University. Before taking position of Bugshan/Bell Lab Chair in Telecommunications at King Fahd University of Petroleum and Minerals in April 2000, he was a Professor and Associate Head of the Department of Electronic and Information Engineering at Hong Kong Polytechnic University, where he was founding director of Wireless Information Systems Research (WISR) Centre. At KFUPM he established Telecommunications Research Laboratory. Professor Sheikh is the author of a recently published book, Wireless Communications - Theory & Techniques published by Kluwer Academic Publishers, Orwell, Mass., USA. He has published over 230 papers in international journals and conference proceedings. He also authored or co-authored 30 technical reports. Dr. Sheikh is a co-recipient of Paul Adorian Premium from IERE (London) for his work on impulsive noise characterization. He was awarded teaching achievement awards in 1984 and 1986, and Research Achievement Award in 1994, all by Carleton University. Dr. Sheikh is actively involved in several international conferences mainly as a member of Technical Program Committees. He has organized and chaired many technical sessions at several international conferences. He Chaired the Technical Program of VTC'98. He is an editor of IEEE Transaction on Wireless Communications, a Technical Associate Editor of IEEE Communication Magazine. He is on the Editorial Board of Wireless Personal Communications, and Wireless Communications and Mobile Computing. He was a co-guest editor of the Special Issue of WPC on Interference. Dr. Sheikh is also on the reviewer panels of many IEEE and IEE Transactions and Journals. Dr. Sheikh has been consultant to many private companies and government agencies. His current interests are in signal processing in communications, mitigation of interference, spread spectrum and 3G and beyond systems. His other interests include helping developing countries in education and research. He had assignments under UNDP's sustained Development Program. He is a Fellow of the IEEE and a Fellow of the IEE. Dr. Sheikh is listed in Marquis Who's Whos in the world and Who's Who in Science and Engineering.     

A Prototype Bandpass Sigma-Delta Modulator Employing Crystal Resonator

This paper describes an initial work on a second-order bandpass Sigma-delta modulator employing crystal resonator. The aim of this work is to explore the possibilities of realizing bandpass sigma-delta modulator using non-electronic resonators, such as micro-mechanical resonators. The initial study is based on crystal resonators as they have similar characteristics as the other types of resonator and are readily available. In order to obtain the desired loop transfer function, a compensation circuit is proposed to cancel the anti-resonance in the crystal resonator. The modulator chip is fabricated in a 0.6-μ m CMOS process. The bandpass noise shaping is demonstrated in the experiment with a 1- and 8-MHz crystal resonator, respectively. Yong Ping Xu graduated from Nanjing University, P.R. China in 1977. He received his Ph.D. from University of New South Wales (UNSW) Australia, in 1994. From 1978 to 1987, he was with Qingdao Semiconductor Research Institute, P.R.China, initially as an IC design engineer, and later the deputy R&D manager and the Director. From 1993 to 1995, he worked on an industry collaboration project with GEC Marconi, Sydney, Australia, at the same university, involved in design of sigma-delta ADCs. He was a lecturer at University of South Australia, Adelaide, Australia from 1996 to 1998. He has been with the Department of Electrical and Computer Engineering, National University of Singapore since June 1998 and is now an Associate Professor. His general research interests are in the areas of mixed-signal and RF integrated circuits, and integrated MEMS and sensing systems. He is a Senior Member of IEEE. Xiaofeng Wang was born in Shangqiu, China, in 1980. He received B.Eng. degree from Northwestern Polytechnical University, Xi'an, China, in 2000 and M. Eng. degree from National University of Singapore, Singapore, in 2003, both in electrical engineering. He is currently working toward the Ph.D. degree at Tufts University, Medford, USA. His research is on high speed ADC design. Wai Hoong Sun was born in Taiping, Malaysia in 1976. He received the B. App. Sc. (Honours) degree in electrical engineering from the University of Toronto, Canada in 1999. After graduating, he joined Sharp Electronics Singapore as an R&D Engineer where he was involved in FPGA and digital IC design of display related circuits. In 2001 and 2002, he did full time research in the National University of Singapore on bandpass sigma-delta modulators. During that period, he was also a Graduate Tutor in electronics for second year electrical and computer engineering students. He then joined Philips Electronics Singapore in 2002 as a Lead Engineer. He did board-level designs for LCD and plasma televisions. He was also development project leader for a project that was successful in bringing to the market a range of LCD and plasma televisions. Currently, he is a Hardware Architect where he is responsible for the system-level electrical design of the television board.     

Voltage-Mode Universal Biquadratic Filters with One Input and Five Outputs

Four new voltage-mode universal biquadratic filters each with one input terminal and five output terminals are presented. Each of the first two proposed circuits uses four plus-type second-generation current conveyors, two grounded capacitors and five resistors. The third proposed circuit employs two plus-type second-generation current conveyors, one differential voltage current conveyor, two grounded capacitors and five resistors. The fourth proposed circuit employs two multi-output second-generation current conveyors, two grounded capacitors and five resistors. Each of the proposed circuits can realize all the standard filter functions; highpass, bandpass, lowpass, notch and allpass, simultaneously, without changing the passive elements. The proposed circuits enjoy the features of orthogonal controllable of resonance angular frequencies and quality factors, using only grounded capacitors as well as low active and passive sensitivities. Jiun-Wei Horng was born in Tainan, Taiwan, Republic of China, in 1971. He received the B.S. degree in Electronic Engineering from Chung Yuan Christian University, Chung-Li, in 1993, and the Ph.D. degree from National Taiwan University, Taipei, in 1997. From 1997 to 1999, he served as a Second-Lieutenant in China Army Force. From 1999 to 2000, he joined CHROMA ATE INC. where he worked in the area of video pattern generator technologies. From 2000 to 2005, he joined the Department of Electronic Engineering, Chung Yuan Christian University, Chung-Li, Taiwan as an Assistant Professor. Since 2005, he is an Associate Professor. His teaching and research interests are in the areas of Circuits and Systems, Analog and Digital Electronics, Active Filter Design and Current-Mode Signal Processing. Chun-Li Hou was born in Taipei, Taiwan, Republic of China, in 1951. He received the B.S. degree, M.S. degree, and Ph.D. degree in Electrical Engineering from National Taiwan University, Taipei, in 1974, 1976, and 1991, respectively. From 1977 to 1979, he taught as a lecture in Tamkang College. From 1981 to 1991, he taught as a lecture in the department of Electronic Engineering, Chung-Yuan Christian University, Chung, Taiwan. From 1992 until now, he taught there as an Associate Professor. His teaching and research interests are in the areas of Current-Mode Analog Circuit Analysis and Design, Active Network Synthesis Circuit theory and Applications. Chun-Ming Chang obtained his bachelor and master degrees, both in the field of electrical engineering, from National Cheng Kung University, Tainan, Taiwan, R.O. China, and his Ph.D. degree in the field of electronics and computer science from the University of Southampton, U.K. He had been an associate professor in Chung Yuan Christian University in Taiwan from 1985 to 1991, and has been a full professor in the same University since 1991. His research interest is divided by two relative fields, network synthesis before 1991 and analog circuit design after 1991. He had been a chairman of the electrical engineering department in Chung Yuan Christian University from 1995 to 1999. Recently, he was recommended for inclusion in The Contemporary Who's Who of Professionals 2004 Edition, and nominated by the Governing Board of Editors of the American Biographical Institute for the prestigious title MAN OF THE YEAR-2005, and became an Advisor of the ABI's distinguished RESEARCH BOARD OF ADVISORS due to the invention of Analytical Synthesis Method and OTA-Only-Without-C Circuits in the field of analog circuit design. Wen-Yaw Chung was born in Hsin-Chu, Taiwan, R.O.C., 1957. He received the B.S.E.E. and M.S. degrees from Chung Yuan Christian University, Chung Li, Taiwan, in 1979 and 1981 respectively, and the Ph.D. degree in Electrical and Computer Engineering from Mississippi State University, USA, in 1989. Subsequently, he joined the Advanced Microelectronics Division, Institute for Technology Development in Mississippi, where he was involved in the design of a bipolar optical data receiver. In 1990 he worked as a design manager for the Communication Product Division, United Microelectronics Corporation, Hsin-Chu, where he was involved in the design of analog CMOS data communication integrated circuits. Since 1991 he has been an Associate Professor in the Department of Electronic Engineering at Chung Yuan Christian University. His research interests include mixed-signal VLSI design, biomedical IC applications, sensor and actuator interfacing for deep submicron VLSI electronics.     

Biorthogonal Recombination Nonuniform Cosine-Modulated Filter Banks and their Multiplier-Less Realizations

This paper studies the theory, design and multiplier-less (ML) realization of a class of perfect reconstruction (PR) low-delay biorthogonal nonuniform cosine-modulated filter banks (CMFBs). It is based on a recombination (or merging) structure previously proposed by the authors. By relaxing the original CMFB and the recombination transmultiplexer (TMUX) in the recombination structure to be biorthogonal, nonuniform CMFBs with lower system delay can be obtained. This also increases the possible choices of the prototype filters to meet different design objectives. A matching condition is introduced to suppress the spurious response resulting from the mismatch in the transition bands of the two biorthogonal CMFBs. A complete factorization of biorthgonal CMFB using the lifting scheme is employed to obtain structurally PR biorthogonal nonuniform filter banks (FBs), which are robust to coefficient quantization. In addition, by approximating the lifting coefficients and the modulation matrices by the sum of powers-of-two (SOPOT) coefficients, ML realization with very low implementation complexity is obtained. Design examples and comparison are given to illustrate the effectiveness of the proposed method. S. C. Chan received his B.Sc. (Eng) and Ph.D. degrees in electrical engineering from the University of Hong Kong, Hong Kong, in 1986 and 1992, respectively. He joined City Polytechnic of Hong Kong in 1990 as an assistant Lecturer and later as a University Lecturer. Since 1994, he has been with the department of electrical and electronic engineering, the University of Hong Kong, Hong Kong, and is now an associate Professor. He was a visiting researcher in Microsoft Corporation, Redmond, USA and Microsoft China at 1998 and 1999, respectively. Dr. Chan is currently a member of the Digital Signal Processing Technical Committee of the IEEE Circuits and Systems Society. He was Chairman of the IEEE Hong Kong Chapter of Signal Processing from 2000 to 2002. His research interests include fast transform algorithms, filter design and realization, multirate signal processing, communications signal processing, and image-based rendering. X. M. Xie received the M.S. degree in electronic engineering from Xidian University in 1996, and the Ph.D degree in electrical & electronic engineering from the University of Hong Kong in 2004. She is now with the school of electronic engineering, Xidian University. Her research interests are in digital signal processing, multirate filter bank and wavelet transform.     

Cooperative-diversity slotted ALOHA

We propose a cooperative-diversity technique for ad hoc networks based on the decode-and-forward relaying strategy. We develop a MAC protocol based on slotted ALOHA that allows neighbors of a transmitter to act as relays and forward a packet toward its final destination when the transmission to the intended recipient fails. The proposed technique provides additional robustness against fading, packet collisions and radio mobility. Network simulations confirm that under heavy traffic conditions, in which every radio always has packets to send, the proposed cooperative-diversity slotted-ALOHA protocol can provide a higher one-hop and end-to-end throughput than the standard slotted-ALOHA protocol can. A similar advantage in end-to-end delay can be obtained when the traffic is light. As a result, the proposed cooperative-diversity ALOHA protocol can be used to improve these measures of Quality of Service (QoS) in ad hoc wireless networks. John M. Shea (S’92–M’99) received the B.S. (with highest honors) in Computer Engineering from Clemson University in 1993 and the M.S. and Ph.D. degrees in electrical engineering from Clemson University in 1995 and 1998, respectively. Dr. Shea is currently an Associate Professor of electrical and computer engineering at the University of Florida. Prior to that, he was an Assistant Professor at the University of Florida from July 1999 to August 2005 and a post-doctoral research fellow at Clemson University from January 1999 to August 1999. He was a research assistant in the Wireless Communications Program at Clemson University from 1993 to 1998. He is currently engaged in research on wireless communications with emphasis on error-control coding, cross-layer protocol design, cooperative diversity techniques, and hybrid ARQ. Dr. Shea was selected as a Finalist for the 2004 Eta Kappa Nu Outstanding Young Electrical Engineer Award. He received the Ellersick Award from the IEEE Communications Society in 1996. Dr. Shea was a National Science Foundation Fellow from 1994 to 1998. He is an Associate Editor for the IEEE Transactions on Vehicular Technology. Tan F. Wong received the B.Sc. degree (1st class honors) in electronic engineering from the Chinese University of Hong Kong in 1991, and the M.S.E.E. and Ph.D. degrees in electrical engineering from Purdue University in 1992 and 1997, respectively. He was a research engineer working on the high speed wireless networks project in the Department of Electronics at Macquarie University, Sydney, Australia. He also served as a post-doctoral research associate in the School of Electrical and Computer Engineering at Purdue University. Since August 1998 he has been with the University of Florida, where he is currently an associate professor of electrical and computer engineering. He serves as Editor for Wideband and Multiple Access Wireless Systems for the IEEE Transactions on Communications and as the Editor for the IEEE Transactions on Vehicular Technology.     

Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator

A domino free 4-path time-interleaved second order sigma-delta modulator is proposed. This time-interleaved scheme uses only one integrator channel along with incomplete integrator output terms to completely eliminate the quantizer domino which is a key limit for the practical circuit implementation of conventional multi-path time-interleaved sigma-delta modulators. In addition, the single integrator channel leads to considerable hardware reduction as well as path mismatch insensitivity, since only one global feedback path is required. As a result, the switched capacitor implementation of the 4-path time-interleaved second order sigma-delta modulator is enabled with the conventional 2-phase clocking scheme by using only 5 op-amps.Kye-Shin Lee received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 1992 and the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the University of Texas at Dallas.He was with LG Semicon Co. (now Hynix Semicon Inc.), Seoul, Korea from 1994 to 1999, where he was involved in mixed signal circuit design and testing of BW/Color CCD chipsets including timing/sync. signal generator, camera signal processor, USB camera interface, and sigma-delta CODECs for audio and voice band applications. His research has been focused on switched-capacitor circuits, sigma-delta modulators, and pipeline ADCs.Yunyoung Choi received the B.S. degree from Kwangwoon University, Seoul, Korea, in 1999 and the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the University of Texas at Dallas. He worked for Texas Instruments, Dallas, from May to December 2003 at the Wireless Business Unit. His research interest includes sigma-delta A/D and D/A converters for audio systems and RF applications.Franco Maloberti received the Laurea Degree in physics (summa cum laude) from the University of Parma, Parma, Italy, in 1968 and the Dr. Honoris Causa degree in electronics from the Instituto Nacional de Astrofisica, Optica y Electronica (Inaoe), Puebla, Mexico, in 1996.In 1993, he was a Visiting Professor at ETH-PEL, Zurich, Switzerland. He was Professor of Microelectronics and Head of the Micro Integrated Systems Group, University of Pavia, Pavia, Italy, and the TI/J.Kilby Analog Engineering Chair Professor at Texas A&M University, College Station. He is currently with the University of Pavia and an adjunct Professor at the University of Texas at Dallas. His professional expertise is in the design, analysis, and characterization of integrated circuits and analog digital applications, mainly in the area of switched-capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analog and mixed A/D design. He has written more than 250 published papers, three books, and holds 15 patents.Dr. Maloberti was a 1992 recipient of the XII Pedriali Prize for his technical and scientific contributions to national industrial production. He was co-recipient of the 1996 Institution of Electrical Engineers (U.K.) Fleming Premium for the paper “CMOS triode transistor transconductance for high-frequency continuous time filters.” He has been responsible at both technical and management levels for many research programs including ten ESPRIT projects and has served the European Commission as ESPRIT Projects’ Evaluator and Reviewer and as a European Union expert in many Initiatives. He served the Academy of Finland on the assessment of electronic research in Academic institutions and on the research programs’ evaluator. He was Vice-President, Region 8, of the Editor of IEEE Circuits and Systems (CAS) Society from 1995 to 1997 and an Associate Editor of the IEEE Transcations on Circuits and Systems II. He received the 1999 IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the IEEE Millennium Medal. He is the President of IEEE Sensors Council and a member of the Board of Governors of the IEEE CAS Society. He is also the member of the Italian Electrotechnical and Electronic Society (AEI) and the Editorial Board of Analog Integrated Circuits and Signal Processing.     

Opamp gain insensitive MASH sigma delta modulator for wide bandwidth applications

This work presents a means to enhance the immunity of non-ideal opamp gain effect of the fourth order multi-stage noise shaped (MASH) sigma-delta modulator (SDM) for wide bandwidth applications. The first stage of the SDM is a low-distortion single-loop second order SDM, while the second stage is a low-distortion interpolative second order SDM with Chebyshev type II filter technique. Theoretically, the conventional MASH SDM is impacted by the nonlinear finite gain of the operational amplifier. This impact may have two main phenomena. First, it leaks the incompletely corrected quantization error to the output. Secondly, the nonlinearity causes the harmonic distortion of the input signal. The proposed architecture can reduce the distortion and the sensitivity of the nonlinear finite opamp gain to improve the performance by using low-distortion technique in the MASH SDM. Furthermore, the lower power budget and simplified digital cancellation logic can be achieved. The experimental results indicate that the dynamic range (DR) can reach 87dB with power dissipation of 65 mW. A test SDM chip for Asymmetric Digital Subscriber Line (ADSL) application is designed and implemented by TSMC 0.25 um 1P5M process. Jen-Shiun Chiang was born in Taichung Taiwan, ROC in 1960. He received the B.S. degree in electronics engineering from Tamkang University, Taipei, Taiwan in 1983. In 1988, he received the M.S. degree in electrical engineering from University of Idaho, Moscow Idaho, USA. In 1992, he received the Ph.D. degree in the electrical engineering from Texas A & M University, College Station Texas, USA. He joined the faculty member of the Department of Electrical Engineering at Tamkang University in 1992. Currently, he is a Professor and Department Chair of the Department of Electrical Engineering at Tamkang University. Dr. Chaings research interest includes computer arithmetic, computer architecture, digital signal processing for VLSI architecture, architecture for image data compressing, analog to digital data conversion, and low power circuit design. Hsin-Liang Chen was born in Taipei, Taiwan, in 1974. He received the B.S. degree and M.S. degree in the electrical engineering from Tamkang University, Taipei, Taiwan, in 1997 and 2003, respectively. He is currently working toward the Ph.D. degree at Tamkang University. His research interest focuses on mixed-signal CMOS circuit, sigma delta ADC, and low power circuit.     

HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing

The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell CMOS technology, occupies about 81 mm², and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.From 1995 to 1996, he was with the NEC Information Technology Research Laboratories, Kawasaki, Japan, working on efficient implementations of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization for signal processing and multimedia applications.Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.Sören Moch received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1997.Since then he has been Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of processor architectures for image, video and multimedia signal processing applications.Lars Friebe studied electrical engineering at the Universities Ulm and Hannover, Germany. In 1999, he worked at the NEC System ULSI Research Laboratory in Kanagawa, Japan. He received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1999.Since then he has been a Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of parallel programmable VLSI architectures for real-time image processing.Mark B. Kulaczewski started his studies in electrical engineering at the University of Hannover, Germany. In 1994, he transferred to Purdue University, West Lafayette, USA, and received the M.S. degree in electrical engineering in 1996.Since 1997 he has been a Research Assistant at the Laboratory for Information Technology and the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable real-time architectures for video coding and image segmentation, and instruction-set extensions for cryptographic applications.Sebastian Flügel was born in Crivitz, Germany, in 1975. He received his Dipl.-Ing. degree from the Department of Electrical Engineering of the University of Rostock in 2001.Since then he has been a Ph.D. candidate at the Institute of Microelectronic Systems at the University of Hannover. He works in the field of architectures and systems for video processing systems. His focus is on algorithms for video encoding and the development of optimized hardware architectures.Heiko Klußmann received the Dipl.-Ing. degree in computer engineering from the University of Hannover, Germany, in 2002.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests are in the area of programmable architectures for real-time video signal processing.Andreas Dehnhardt was born in Frankfurt am Main, Germany, in 1976. He received his Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 2002.Since then, he has been a Research Assistant with the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable architectures for multimedia applications and implementation of real-time MPEG-4 encoding schemes.Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1980 and in Summer 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL research center, Stuttgart. Since 1987 he is Professor in the Department of Electrical Engineering, since 2002 in the Department of Computer Science at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002. His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.     

A Fast Settling HBT Reference Amplifier for High Speed Digital-to-Analog Converters

This paper proposes a fast settling reference amplifier for use with a current-steering Digital-to-Analog Converter (DAC). The reference amplifier utilizes an open loop architecture, resulting in a bandwidth of 2.5 GHz, small chip area and low power. The wide bandwidth of the reference amplifier is shown to be important for fast settling of DAC current output. The reference amplifier is also able to generate a reference current that tracks fast changes of reference voltage, thus is useful in applications such as multiplying DACs and transversal filters. The proposed design was fabricated using a 1 μm GaAs HBT process. The prototype reference amplifier achieves a temperature coefficient of 92 ppm/°C over a temperature range of 0–100°C and the reference current changes only ±2.14% when the power supply varies ±0.2 V.Yihong Dai received his B.S. and M.Eng. degrees in Electrical Engineering from Shanghai JiaoTong University, Shanghai, China in 1993 and 1996, respectively. From 1996 to 1998, he enjoyed his industrial experiences in Shanghai with semiconductor companies like Shanghai Nortel Semiconductor and Motorola Electronics (China) Shanghai Branch. Since 1998, he has been a research assistant at the Analog and Mixed-signal Laboratory of the Electrical Engineering Department of Brigham Young University working toward his Ph.D. During the summer of 1999, he was with AMI semiconductor Utah Research and Design Center where he developed a threshold voltage based CMOS voltage reference architecture. In the summer of 2001, he was with Ultra Design LLC where he designed a reference amplifier for high speed digital-to-analog converters. His research interest includes voltage reference, reference amplifier and high speed data converters in both CMOS and GaAs processes.Donald T. Comer received the B.S., M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and the University of Santa Clara, respectively, all in electrical engineering. He began teaching at San Jose State University in 1961 and mixed his teaching and industrial work until he left San Jose State University in 1979. He has worked for California Technical Industries, IBM Corp., Mobility Systems, Precision Monolithics, Storage Technology Corp., and Analog Devices during his career. He founded the AMI Utah Research and Design Center in 1998 that specializes in MOS design. In 2002, Dr. Comer founded Ultra Design, a design center that specializes in high-frequency heterojunction circuit designs. He holds fifteen patents and has published over 50 articles dealing with solid-state and integrated circuits. He has published five textbooks in the field of large-signal and integrated circuits. He formerly held the Quentin Berg Chair at Penn State Harrisburg from 1990 to 1995. He is now a professor of electrical and computer engineering at Brigham Young University where he held the Endowed Chair of Engineering from 1995 to 1998.David J. Comer received the B.S., M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and Washington State University, respectively, all in electrical engineering. He has worked for IBM Corp., Pacific Electromagnetics, Lawrence Livermore Laboratories, and Intel Corporation. He began his teaching career at the University of Idaho and has taught at the University of Calgary and California State University, Chico. He is presently a professor of electrical and computer engineering at Brigham Young University. He served as Chairman of the Division (Dean) of Engineering at CSU, Chico and as Department Chair at BYU.While at CSU, Chico, Dr. Comer served on the statewide Engineering Liaison Committee and served as Chair of the Council of California State University Deans of Engineering.Dr. Comer has published twelve textbooks and over 60 articles in the field of circuit design. He has contributed sections to the Encyclopedia of Physical Science and Technology and holds seven patents. He was given the Professional Achievement Award at CSU, Chico and was named the Outstanding Teacher of Engineering at BYU. He has also held the College of Engineering Research Chair at Brigham Young University.     

Design of Current-Mode Square-Root Domain Band-Pass Filter with Reduced Voltage

A design technique for current-mode square-root domain band-pass filter fabricated in a 0.25 μ m CMOS process is presented. The basic building block consists of current-mode current mirrors, square-root circuits and capacitors, and in which the overall supply voltage is reduced by adopting low-voltage level-shift current mirror. Both of the simulation and measured results, which are in good agreement, indicate that the prototype of the band-pass provides tunable center frequency of 4–10 MHz with bias-current-tunable, −26.7 dB total harmonic distortion (THD), and approximately 1.598 mW power dissipation with a 1.5 V supply voltage. Advantages of the proposed filter include high frequency operation, tuneability, low supply voltage operation, low power consumption, and low third order intermodulation distortion. Gwo-Jeng Yu was born in Kaohsiung, Taiwan, R.O.C., in 1954. He received the B.S. and M.S. degrees in the Department Electronic Engineering in 1972 and 1976, respectively, from National Chiao Tung University, HsinChu, Taiwan, R.O.C., and he is currently working toward the Ph.D. degree in the Department of Electrical Engineering of National Cheng Kung University, Tainan, Taiwan, R.O.C. Since 1978, he has been on the Faculty of Institute of Cheng Shiu Technology, Kaohsiung, Taiwan, R.O.C., where he is currently a Associate Professor in the Department of Electronic Engineering. During 1979–1990, he was the Chairman of the Electronic Engineering Department and the Chairman of the Microelectronics and Information Technology Center during 1996–2000. His current researches include current-mode circuits design, analog IC design and VLSI circuit design. Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from the National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of the Department of Electronic Engineering. His current researches include current-mode circuits design, VLSI design, analog IC design, and analog IP design. Jenn-Jiun Chen received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. His research interests are design and modeling of current mode circuit, low power analog circuit design, current mode filters, and instrumental amplifier in micro sensor applications. He received Chip Design Award from the Chip Implementation Center, National Applied Research Laboratories, in 2002. Bin-Da Liu received the B.S., M.S., and Ph.D. degrees all in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1973, 1975, and 1983, respectively. Since 1977 he has been on the faculty of the National Cheng Kung University, where he is currently Distinguished Professor in the Department of Electrical Engineering and Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995 he has been a consultant of the Chip Implementation Center, National Applied Research Laboratories. He has published more than 190 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang Ed. Singapore: World Scientific Publisher, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordn, F. Herrera, and L. Magdalena Eds. Heidelberg, Germany: Springer-Verlag, 2003). He is currently a CAS Associate Editor of the IEEE Circuits & Devices Magazine and an Associate Editor of the IEEE Transactions on Circuits and Systems-I. His current research interests include low power circuit design, SoC system integration and verification, and VLSI implementation for fuzzy-neural networks and audio/video signal processors.     

A New Differential CMOS Current-Mode Preamplifier for GBps Data Communications

This paper presents a new low-voltage fully differential CMOS current-mode preamplifier for GBps data communications. The number of transistors between the power and ground rails is only two so that the minimum supply voltage is one threshold voltage plus one pinch-off voltage. The preamplifier is a balanced two-stage configuration such that the effect of bias-dependent mismatches is minimized. A new inductive series-peaking technique is introduced to increase the bandwidth by utilizing the resonance characteristics of LC networks. In addition, a new negative differential current feedback technique is proposed to boost the bandwidth and to reduce the value of peaking inductors. The preamplifier has been implemented in TSMC 0.18 μm, 1.8 V, 6-metal mixed-mode CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. For an optical front-end with a 0.3 pF photodiode capacitance, simulation results demonstrate that the preamplifier has bandwidth of 3.5 GHz and provides a transimpedance gain of 66 dBΩ. The total chip area is approximately 1 mm² and the DC power consumption is about 85 mW. Bendong Sun received the B.Eng. degree in electrical engineering from Shanghai Jiaotong University, Shanghai, China, in1992, and the MASc degree in electrical and computer engineering from Ryerson University, Toronto, Ontario, Canada, in 2003. He is currently working towards the Ph.D. degree in electrical and computer engineering at University of Waterloo, Waterloo, Ontario, Canada. During 1992 through 1998 he was a Design Engineer at China Electronics Engineering Design Institute, Beijing, China. From 1998 to 2000 he worked for Bently Nevada Corporation, a GE Power Systems business, as a System Engineer. Since 2001, he has been a Research Assistant with the System-on-Chip Laboratory at Ryerson University. His research interests include design of analog and mixed-signal integrated circuits for high-speed data communications. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc degree in chemical engineering and PhD degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching" award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada. Ajoy Opal (S'86-M'88) received the B. Tech degree from Indian Institute of Technology, New Delhi, India in 1981, and the MASc and PhD degrees from University of Waterloo, Waterloo, Ontario, Canada in 1984 and 1987, respectively. During 1989–92 he worked for Bell-Northern Research in the area of analog circuit simulation. He joined the Department of Electrical and Computer Engineering, University of Waterloo in 1992 and currently a Full Professor. Dr. Opal works in the area of simulation of analog and mixed digital-analog circuits, such as, switched capacitor, switched current, oversampled sigma-delta modulators. Other interests include circuit theory and filter design.     

A New Low Latency Parallel FIR Filter Scheme

A new array type parallel scheme for an FIR digital filter is presented in this paper. The proposed scheme is based on the structure of the carry-save array multiplier where each cell implements the computation of an FIR filter at the bit-level. This structure leads to latency independent of the number of the filter taps. The proposed scheme is pipelined at the bit-level, is systolic at the cell-level and requires less hardware than other schemes based on discrete multipliers.Paraskevas Kalivas received his Diploma and Ph.D. degree in electrical and computer engineering from the National Technical University of Athens, Greece, in 1990 and 2000 respectively.His research interests include computer arithmetic and efficient realization of arithmetic circuits and digital filters.Vassilis Vassilakis received his Diploma in electrical and computer engineering from NationalTechnical University of Athens, Greece, in 1997. He isworking toward the Ph.D. degree in electrical engineering at National Technical University of Athens.His research interests include efficient circuit implemenation of DSP algorithms and java processor architectures.Chris Meletis received his Diploma in electrical and computer engineering from National Technical University of Athens in 1997. Currently, he is working toward the Ph.D. degree in electrical engineering at National Technical University of Athens.His research interests include multirate filter banks, digital filter design and their efficient realization.Kiamal Z. Pekmestzi received his Diploma in electrical engineering from the National Technical University of Athens, Greece, in 1975. From 1975 to 1981, he was a research fellow in the Electronics Department of the Nuclear Research Center Demokritos. He received his Ph.D. in electrical engineering from the University of Patras, Greece, in 1981.From 1983 to 1985, he was a professor at the Higher School of Electronics in Athens. Since 1985, he has been with the National Technical University of Athens, where he is currently a professor. His research interests include computer arithmetic, VLSI digital filters and VLSI design automation.     

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

Technology is making the integration of a large number of processors on the same silicon die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a high degree of flexibility and represent the most efficient architectural solution for supporting multimedia applications, characterized by the request for highly parallel computation. As a consequence, tools for the simulation of these systems are needed for the design stage, with the distinctive requirement of simulation speed, accuracy and capability to support design space exploration. We developed a complete simulation platform for a MP-SoC called MP-ARM, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication architecture, memory models and support for parallel programming. A fully operating linux version for embedded systems has been ported on this platform, and a cross-toolchain has been developed as well. Our MP simulation environment turns out to be a powerful tool for the MP-SOC design stage. As an example thereof, we use our tool to evaluate the impact on system performance of architectural parameters and of bus arbitration policies, showing that the effectiveness of a particular system configuration strongly depends on the application domain and the generated traffic profile.Luca Benini received the B.S. degree (summa cum laude) in electrical engineering from the University of Bologna, Italy, in 1991, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1994 and 1997, respectively. He is an associate professor in the department of electronics and computer science in the University of Bologna. He also holds visiting researcher positions at Stanford University and the Hewlett-Packard Laboratories, Palo Alto, CA.Dr. Benini’s research interests are in all aspects of computer-aided design of digital circuits, with special emphasis on low-power applications, and in the design of portable systems. He is co-author of the book: Dynamic Power management, Design Techniques and CAD tools, Kluwer 1998.Dr. Benini is a member of the technical program committee for several technical conferences, including the Design Automation Conference, the International Symposium on Low Power Design and the International symposium on Hardware-Software Codesign.Davide Bertozzi received the B.S. degree in electrical engineering from the University of Bologna, Bologna, Italy, in 1999.He is currently pursuing the Ph.D. degree at the same University and is expected to graduate in 2003. His research interests concern the development of SoC co-simulation platforms, exploration of SoC communication architectures and low power system design.Alessandro Bogliolo received the Laurea degree in electrical engineering and the Ph.D. degree in electrical engineering and computer science from the University of Bologna, Bologna, Italy, in 1992 and 1998.In 1995 and 1996 he was a Visiting Scholar at the Computer Systems Laboratory (CSL), Stanford University, Stanford, CA.From 1999 to 2002 he was an Assistant Professor at the Department of Engineering (DI) of the University of Ferrara, Ferrara, Italy. Since 2002 he’s been with the Information Science and Technology Institute (STI) of the University of Urbino, Urbino, Italy, as Associate Professor. His research interests are mainly in the area of digital integrated circuits and systems, with emphasis on low power and signal integrity.Francesco Menichelli was born in Rome in 1976. He received the Electronic Engineering degree in 2001 at the University of Rome “La Sapienza”. From 2002 he is a Ph.D. student in Electronic Engineering at “La Sapienza” University of Rome.His scientific interests focus on low power digital design, and in particular in level tecniques for low power consumption, power modeling and simulation of digital systems.Mauro Olivieri received a Master degree in electronic engineering “cum laude” in 1991 and a Ph.D. degree in electronic and computer engineering in 1994 from the University of Genoa, Italy, where he also worked as an assistant professor. In 1998 he joined the University of Rome “La Sapienza”, where he is currently associate professor in electronics. His research interests are digital system-on-chips and microprocessor core design. Prof. Olivieri supervises several research projects supported by private and public fundings in the field of VLSI system design.     

A Hardware/Software Co-Design of MP3 Audio Decoder

The Moving Picture Experts Group (MPEG) audio coding standard offers three levels of compression algorithms where the MPEG Layer III (MP3) has the best quality but with the most complexity. There are several complex coding techniques involved in MP3 audio decoding algorithm, therefore, it is difficult to make an efficient architecture design. This paper presents a hardware/software co-design method for the implementation of MP3 audio decoder, which meets the real-time requirement of MP3 standard. The software and hardware part of this decoder is partitioned into a pre-processing and a post-processing unit respectively. The pre-processing unit with a programmable parser processor is developed for the implementation of intensive decision making operations needed for audio bitstreams. The post-processing unit with a dedicated hardware of modified fast algorithm is designed for the regular and computation-intensive operations in MP3 audio decoding flow. The architecture achieves a high throughput with a reduced memory requirement and hardware complexity. With a two-level pipeline approach, it allows a high hardware utilization and is suitable to low power implementation. The proposed decoder system has been designed and implemented using VLSI cell-based approach. The die size is 3.5 × 4.45 mm² with the maximum operation frequency of 20 MHz.Tsung-Han Tsai was born in Chunghua, Taiwan, R.O.C. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1990, 1994, and 1998 respectively. Dr. Tsai was an Instructor (1994–1998) and an Associate Professor (1998–1999) of the department of electrical engineering at Hwa Hsia College of Technology and Commerce. From 1999 to 2000, he was an Associate Professor of electronic engineering at Fu Jen University. Currently, he is an Assistant Professor in the department of electrical engineering at National Central University. He is also a member of IEEE and Audio Engineering Society (AES). Dr. Tsai has been awarded 8 patents and more than 70 refereed papers published in international journals and conferences. His research interests include VLSI signal processing, video/audio coding algorithms, DSP architecture design, wireless communication and System-On-Chip design.Ya-Chau Yang was born in Tainan, ROC in 1976. He received the B.S. and M.S. degrees both in electrical engineering from Fu-Jen University in 1999 and 2001, respectively. In 2002, he was as software engineer of Foundry Access in Cadence Design Systems. Currently he is a design engineer at ActVision Technology Inc, where he works on MPEG audio decoder IP design. His interests include MPEG audio coding algorithms, VLSI signal processing/architecture and computer architecture.Chun-Nan Liu was born in Taichung, Taiwan, R.O.C., in 1978. He received the B.S. degrees in electrical engineering from National Central University, Taiwan, in 2000. He is currently pursuing the Ph.D. degree from the Department of Electrical Engineering, National Central University, Taiwan. His area of interests are audio signal processing and VLSI signal processing.     

A 1.8 V CMOS fourth-order Gm-C bandpass sigma-delta modulator dedicated to front-end ultrasonic receivers

A 4th order bandpass sigma-delta modulator for ultrasound applications is presented. By cascading two second-order identical Gm-C bandpass filters, a 4th-order modulator was designed with high power-efficiency, stability, tunability and programmability. The modulator is dedicated for application with intermediate frequency of 3 MHz and bandwidth of 200 kHz. Implemented in a standard 0.18 μm CMOS technology, the post-layout simulation of the modulator gives a dynamic range of 78 dB. Chip measurements are reported after successfully tuning the modulator to operate at four-time of its folded specifications. The final SNR achieves 58 dB at 0.75 MHz with 50 kHz bandwidth. The modulator consumes 2.5 mW from 1.8 V power supply. Moreover, a programming method is introduced and corresponding circuit is designed to change the central frequency of the modulator between 3 and 20 MHz for scanning different regions of the body. However the 200 kHz bandwidth limits the modulator only for Dobbler mode applications, the effective facilities of programmability are valuable property to expand this application to other wide band applications in future. Lisheng Qin received the B.Sc. degree in electrical engineering from Tianjin University, China in 1992. He was with Polystim Neurotechnologies Laboratory from 2001 to 2005 and received the M.Sc. degree in electronics engineering from Ecole Polytechnique de Montreal, Canada in 2005. He is now with Apexone Microelectronics Inc. as Analog/Mixed-Signal Design Engineer. Kamal El-Sankary received the B.Sc. degree in electrical engineering from the Lebanese University, Lebanon in 1997 and the M.Sc. degree in electronics engineering from University of Quebec in Trois Rivieres, Canada, in 2001. He is currently pursuing the Ph.D. degree in microelectronics at Ecole Polytechnique de Montreal, Canada. His research interests include analog/mixed-signal circuits design and signal processing. Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics. His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the Microelectronics Strategic Alliance of Quebec (Regroupement stratégique en microélectronique du Québec - ReSMiQ). He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter, the International IEEE-NEWCAS conference, and Polystim neurotechnologies laboratory at the Ecole Polytechnique de Montreal. He is cofounder of the International Functional Electrical Stimulation Society (IFESS), and the IEEE International conference on Electronics, Circuits and Systems (ICECS). Dr. Sawan is involved in the committees of many national and international conferences and other scientific events. He published more than 300 papers in peer reviewed journals and conference proceedings and is awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society, President of the biomedical circuits and systems (BioCAS) technical committee of the IEEE CAS Society, and he is representative of IEEE-CAS in the International Biotechnology council. He received the Barbara Turnbull 2003 award for spinal cord research, the Medal of Merit from Lebanon, and the Bombardier Medal from the French Association for the advancement of sciences. Dr. Sawan is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE.     

VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers

An adaptive equalizer for ATSC standard HDTV receivers is developed and implemented in VLSI. This equalizer is based on the G-pseudo algorithm that combines the advantages of the decision directed and blind algorithms. It also conducts ghost cancellation for the reception of NTSC analog TV signals. A programmable error calculation unit is employed for a flexible implementation of several equalization algorithms. The filter coefficients have a long internal word-length for a satisfactory operation in the blind adaptation mode, but only parts of them are used for output calculation to reduce the hardware complexity. The performance of the system for seven GA reference channels is evaluated according to the adaptation algorithms, the number of delays for the adaptation, and the word-length of the filter coefficients. The chip area and power consumption according to the time multiplexing ratio are estimated.Wonyong Sung received the B.S. degree in electronic engineering from the Seoul National University in 1978, the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST) in 1980, and the Ph.D. degree in electrical and computer engineering from the University of California, Santa Barbara, in 1987.From 1980 to 1983, he worked at the Central Research Laboratory of the Gold Star (currently LG electronics) in Korea. During his Ph.D. study, he developed parallel processing algorithms, vector and multiprocessor implementation, and low-complexity FIR filter design. He has been a member of the faculty of the Seoul National University since 1989. From May of 1993 to June of 1994, he consulted the Alta Group for the development of the Fixed Point Optimizer, automatic word-length determination and scaling software. From January of 1998 to December of 1999, he worked as a chief of the SEED (System Engineering and Design center) in Seoul National University. He was an associate editor of the IEEE Tr. Circuits and Systems II from 2000 to 2001, is a design and implementation technical committee member of the IEEE Signal Processing Society, and is a VLSI systems and application technical committee member of the IEEE Circuits and Systems Society. He was the general chair of the IEEE Workshop on Signal Processing Systems in 2003. He founded a venture company, Edumedia Technologies, in 2000, and has developed a handheld educational device for kids, SpeakingPartner, for mass production.His major research interests are the development of fixed-point optimization tools, implementation of VLSI for digital signal processing, and development of multimedia software for handheld devices and VLIW digital signal processors.Youngho Ahn received the B.S. and M.S. degrees in electronic engineering from Seoul National University, Seoul, Korea, in 1997 and 1999 respectively. From 1999 to 2000, he was with Samsung Electronics, Kyunggi-Do, Korea, where he was involved in the ASIC design and development of ATSC digital television receivers. Since 2001, he has been with GCT Semiconductor, Inc., where he works in the communications IC design group. His research interests include wireless communications and ASIC design of communications systems.Eunjoo Hwang was born in Taegu, Korea on April 7, 1974. She received the B.S and M.S degrees in electrical engineering from Seoul National University in 1997 and 1999, respectively. Currently, she works for Silicon Image in Sunnyvale, California, USA as a digital circuit design engineer. Her research interests include blind equalization, joint timing recovery algorithm and storage network design.     

A time-to-first spike CMOS image sensor with coarse temporal sampling

Conventional voltage-based CMOS image sensors inherently have a dynamic range of about 60 dB. To extend the dynamic range, a two-degree of freedom time-based CMOS image sensor is proposed. Instead of reading analog voltages off chip, a time representation is used to record when the photodetector voltage passes a timing-varying threshold. The time measurements are combined with the reference voltage waveform to reconstruct the image. Experimental results on a prototype 32 × 32 pixel array CMOS image sensor verify that the two-degree of freedom sampling technique is feasible for ultra-wide dynamic range imaging. A measured 115 dB dynamic range at 30 fps is obtained. Qiang Luo received the B.S. (with honor) and M.S. degrees in electrical engineering from Fudan University, Shanghai, China, in 1995 and 1998, respectively, and the Ph.D. degree in electrical engineering from University of Florida, Gainesville, FL, in 2002. In 2001, he was with Texas Instruments Inc., Dallas, TX, where he was an intern engineer working on ultra-wide dynamic range CMOS image sensors. From 2002 to 2004, he was with National Semiconductor Corporation, Santa Clara, CA, where he was a staff circuit design engineer and worked on the design of high performance CMOS image sensors. He is currently with the Marvell Semiconductor Inc, Sunnyvale, CA, where he is working on the development of advanced DVD servo IC. His research interests include high-speed mixed-signal IC design, CMOS image sensors, DVD servo IC and device physics. Dr. John G. Harris received his BS and MS degrees in Electrical Engineering from MIT in 1983 and 1986. He earned his PhD from Caltech in the interdisciplinary Computation and Neural Systems program in 1991. After a two-year postdoc at the MIT AI lab, Dr Harris joined the Electrical and Computer Engineering Department at the University of Florida (UF). He is currently an associate professor and leads the Hybrid Signal Processing Group in researching biologically-inspired circuits, architectures and algorithms for signal processing. Dr. Harris has published over 100 research papers and patents in this area. He co-directs the Computational NeuroEngineering Lab and has a joint appointment in the Biomedical Engineering Department at UF. Zhiliang J. Chen received Ph.D. degree in electrical engineering from University of Florida in 1994. From 1994 to 2004, he was with Texas Instruments where he worked as Senior Member of Technical Staff and Design Branch Manager. In 2002 he was expatriated to COMMIT, a Texas Instruments JV company in China, as director of RF & Analog Base Band department. In 2004, he left Texas Instrument and found On-Bright (Shanghai) Corporation where he serves as president of the company. Dr. Chen currently held 22 US patents and has published morn than 10 journal papers. He was a recipient of the Best Paper Award from the 1997 ESD/EOS symposium.     

A State-Space Approach to Multiuser Parameters Estimation Using Central Difference for CDMA Systems

In this paper, it is shown that a state-space model applies to the code-division multiple-access (CDMA) channel, and Central Difference Filter (CDF) produces channel estimates with the minimum mean-square error (MMSE). This result may be used as compare to Extended Kalman Filter (EKF) which used as channel estimator in CDMA system. The main purpose of this paper is to compare robustness of channel estimator for realistic rapidly time-varying Rayleigh fading channels. To overcome the highly nonlinear nature of time delay estimation and also improve the accuracy, consistency and efficiency of channel estimation, an iterative nonlinear filtering algorithm, called the CDF has been applied in the field of CDMA System. The proposed channel estimator has a more near-far resistant property than the conventional Extended Kalman Filter (EKF). Thus, it is believed that the proposed estimator can replace well-known filters, such as the EKF. The Cramer-Rao lower bound (CRLB) is derived for the estimator, and simulation result show that it is nearly near-far resistant and clearly outperforms the EKF. Jang Sub Kim was born June 15, 1974, in Yeongdeok, Korea. He received the M.S. degree in school of electrical and computer engineering from Sungkyunkwan University, Seoul, Korea. He is currently with the School of Information and Communication Engineering, Sungkyunkwan University, where he was a Ph. D. student since 1999. His research interests include code-division multiple access, channel estimation, position location, and wireless communications. Seokho Yoon (S‘99–M‘1) received the B.S.E. (summa cum laude), M.S.E., and Ph.D. degrees in electrical engineering from KAIST, Daejeon, Korea, in 1997, 1999, and 2002, respectively. From April 2002 to June 2002, he was with the Department of Electrical Engineering and Computer Sciences, Massachusetts Institute of Technology, Cambridge, MA, and from July 2002 to February 2003, he was with the Department of Electrical Engineering, Harvard University, Cambridge, MA, as a Postdoctoral Research Fellow. In March 2003, he joined the School of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea, where he is currently an Assistant Professor. His research interests include spread spectrum systems, mobile communications, detection and estimation theory, and statistical signal processing. Dr. Yoon is a member of the IEEK and KICS. He was the recipient of a Bronze Prize at Samsung Humantech Paper Contest in 2000. Dong-Ryeol Shin (M‘97) was born in Seoul, Korea, in 1957. He received the B.S., M.S. and Ph.D degree in electrical engineering from the Sungkyunkwan University in 1980, and the Korea Advanced Institute of Science and Technology (KAIST) in 1982 and the Georgia Institute of Technology in 1992, respectively. During 1992-1994, he had worked for Samsung Data Systems, Ltd., Korea. Since 1994, he has been with network research group at the Sungkyunkwan University, Korea, as a professor. His current research interests include wireless communications and ubiquitous computing.     

On Downlink Beamforming Methods: Capacity and Error Probability Performance

In space-division multiple access (SDMA), different beamforming or space-domain precoding techniques can be applied. We investigate two different space-domain precoding methods, the maximum capacity (MC) and the minimum mean square error (MMSE) precoders, for the downlink channel. It is shown that the MMSE precoding, which is practically implementable, can provide a reasonable performance in terms of the capacity and error probability, while the MC precoding is not practical (although it is optimum in terms of the capacity). Space-domain precoding methods are also applied to code-division multiple access (CDMA) systems.This work was supported by the HY-SDR Research Center at Hanyang University, Seoul, Korea, under the ITRC Program of MIC, Korea.Jinho Choi was born in Seoul, Korea. He recieved the B.E. degree (magna cum laude) in electronics engineering from Sogang University in 1989 and the M.S.E. and Ph.D. degree in electrical engineering from the Korea Advanced Institute of Science and Technology in 1991 and 1994, respectively. Currently he is a Senior Lecturer in the School of Electrical Engineering and Telecommunications,University of New South Wales, Australia. Dr. Choi received the 1999 Best Paper Award of Signal Processing from EURASIP.Seungwon Choi received the B.S. degree from Hanyang University, Seoul, Korea, in 1980 and the M.S. degree from Seoul National University, Seoul, in 1982, both the electronic engineering. He received the M.S. degree in computer engineering in 1985 and the Ph.D degree in electrical engineering in 1988 from Syracuse University, Syracuse, NY.From 1982 to 1984, he was with LG Electronics Co. Ltd., Seoul, where he helped developed the 8-mm camcorder system. From 1988 to 1989, he was with the Department of Electrical and Computer Engineering, Syracuse University, as an Assistant Professor. In 1989, he joined the Electronics and Telecommunications Research Institute, daejeon, Korea, where he developed the adaptive algorithm for real-time application in secure telephone systems. From 1990 to 1992, he was with yhe Communication Research Laboratory, Tokyo, Japan, as a science and Technology Agency Fellow, developing adaptive antenna array system and adaptive equalizing filters for applications in land-mobile communications. He joined Hanyang University, Seoul, in 1992 as an Assistant Professor. He is a Professor in the School of Electrical and Computer Engineering, Hanyang University. His research interests include digital communications and adaptive signal processing with a recent focus on the real-time implementation of smart antenna system for 3G mobile communication system.