基于ADS的无线接收机数模混合系统级仿真

采用自顶向下的方法，设计了工作于L波段的宽带无线接收机。该接收机采用数模混合的weaver结构。构造了接收机模拟前端和数字基带的各个功能模块，并用ADS(Advanced Design System)软件完成了接收链路的系统级混合信号仿真。     

Design Techniques of CMOS Ultra-Wide-Band Amplifiers for Multistandard Communications

This paper presents design techniques of CMOS ultra-wide-band (UWB) amplifiers for multistandard communications. The goal of this paper is to propose a compact, simple, and robust topology for UWB low-noise amplifiers, which yet consumes a relatively low power. To achieve this goal, a common-gate amplifier topology with a local feedback is employed. The first amplifier uses a simple inductive peaking technique for bandwidth extension, while the second design utilizes a two-stage approach with an added gain control feature. Both amplifiers achieve a flat bandwidth of more than 6 GHz and a gain of higher than 10 dB with supply voltages of 1.8-2.5 V. Designs with different metal thicknesses are compared. The advantage of using thick-metal inductors in UWB applications depends on the chosen topology.     

A 5–6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler

This paper describes a novel monolithic low voltage (1-V) CMOS RF front-end architecture with an integrated quadrature coupler (QC) and two subharmonic mixers for direct-down conversion. The LC-folded-cascode technique is adopted to achieve low-voltage operation while the subharmonic mixers in conjunction with the QC are used to eliminate LO self-mixing. In addition, the inherent bandpass characteristic of the LC tanks helps suppression of LO leakage at RF port. The circuit was fabricated in a standard 0.18-mum CMOS process for 5-6 GHz applications. At 5.4 GHz, the RF front-end exhibits a voltage gain of 26.2 dB and a noise figure of 5.2 dB while dissipating 45.5 mW from a 1.0-V supply. The achieved input-referred DC-offset due to LO self-mixing is below -110.7 dBm.     

一种高性能CMOS LVDS接收电路的设计

提出了一种符合IEEE Std 1596.3-1996[1]标准,适用于芯片间高速数据传输的低电压差分信号(LVDS)接收电路;有效地解决了传统电路结构在电源电压降至3.3 V或更低以后不能稳定工作在标准规定的整个输入共模电平范围内的问题,电路能在符合标准的0.05~2.35 V输入共模电平范围内稳定工作,传输速率可达1.6 Gb/s,平均功耗1.18 mW。设计基于HJTC(和舰科技)Logic 0.18μm 1.8 V/3.3 V CMOS工艺,使用3.3 V厚栅MOS管和1.8 V薄栅MOS管。     

CMOS光接收机主放大器设计

利用CMOS工艺设计一种用于SDH STM 4速率级(622 Mb/s)光纤用户网的光接收机放大电路。此电路由输入/输出缓冲、主放大单元、偏置补偿电路4部分组成。通过直接耦合技术提高增益,降低功耗;利用有源电感负载提高系统带宽。采用商用SmartSpice电路仿真软件和CSMC HJ 0.6μm工艺参数对该电路进行仿真。结果表明,该电路在5 V工作电压下中频增益为81 dB,3 dB带宽为470 MHz。     

应用于GPS接收机的宽带低噪声放大器

本文介绍了一种适用于GPS接收机的CMOS宽带低噪声放大器,带宽设计在1．16Hz-1．7GHz。采用源极电感负反馈结构,并在输入端加入了宽带匹配网络来扩展带宽,放大器提供30dB的增益,使用了两级放大,第二级采用了电流复用技术来节省功耗,最后一级使用了源极跟随器,用来阻抗匹配。采用TSMC55nmCMOS工艺,仿真结果表明,噪声系数小于1．3dB,S21大于29dB,S11小于-10dB,1．2V电源供电下功耗为20mW。     

1.3–1.55-μ m CMOS/InP Optoelectronic Receiver Using a Self-Aligned Wafer Level Integration Technology

A heterogeneous 10-Gb/s 1.3- to 1.55-mum optoelectronic receiver is designed and fabricated using a complementary metal-oxide-semiconductor transimpedance amplifier and an InGaAs-InP PIN (p-type, intrinsic, n-type diode) photodiode. The receiver is heterogeneously integrated based on a batch fabrication process which promises low fabrication cost. The receiver measures a transimpedance gain of higher than 50 dBldrOmega over a bandwidth of 6 GHz and demonstrates an open eye diagram with a 1.55-mum 10-Gb/s light source.     

A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and Multimedia Applications

This paper presents a direct conversion, multistandard TV tuner implemented on a 65 nm digital CMOS process occupying less than 7 . The tuner is compliant with several digital terrestrial, fixed and mobile TV standards, including DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB noise figure at VHF, UHF, and L-band, respectively, while the measured sensitivity at UHF for the QPSK-frac12 DVB-T mode is at the PCB connector. The implemented RF front-ends support both single-ended and differential inputs. An integrated - fractional-N synthesizer operating from 1.2 to 1.8 GHz achieves less than 1 integrated phase error, thus enabling a maximum SNR in excess of 37 dB for VHF and UHF. Multistandard capability is also enabled by programmable channel-select filters. Power consumption is less than 140 mW in DVB-T mode for all three bands.     

0.5-V 5.6-GHz CMOS Receiver Subsystem

The building blocks of a 0.5-V receiver, including a receiver front-end and a low-pass filter (LPF), are fabricated using 0.18- $mu{hbox{m}}$ CMOS technology. At 5.6 GHz, the receiver front-end achieves a voltage gain of 17.1 dB and a noise figure of 8.7 dB, while dissipating at 19.4 mW. The fifth-order low-pass Chebyshev filter achieves a corner frequency of 2.6 MHz and an input-referred noise of 28.5 nV/sqrt (Hz) at 6.8 mW. The receiver front-end is further integrated with the LPFs to form a highly integrated receiver subsystem at ultra-low voltage.      

一种高性能CMOS单片中频接收机

研制了一种CM O S低压低功耗中频接收机芯片,它包含混频器、限幅放大器、解调器以及场强指示、消音控制等模块,可用于短距离的FM/FSK信号的接收和解调。该接收机采用1st s ilicon 0.25μm CM O S工艺,芯片的测试结果表明整机接收灵敏度为-103 dBm,最高输入射频频率可以达到100 MH z,解调器的线性解调范围为±10 kH z,典型鉴频灵敏度为40 mV/kH z,输入FM信号(调频指数3,信号频率1 kH z)时解调信号的SFDR为41.3 dB。芯片的工作电源电压范围为2~4 V,工作电流3 mA,有效面积0.25 mm2。     

全集成CMOS SCA接收机单片化探讨

本文对调频副载波(SCA)广播接收机的单片化设计进行了探讨,提出了一种新的适合CMOS工艺的全集成SCA接收机结构。接收机采用Weaver-零中频结构实现下变频和二次解调功能,节省了片外镜像抑制滤波器,大大提高了接收机的集成度,降低了接收机的成本和功耗,显示了广阔的潜在应用前景。     

多模式卫星导航接收机中双频段LNA设计

设计出一款应用于多模式卫星导航接收机射频前端的双波段LNA,该电路可以工作在1.575GHz和1.267GHz两个波段附近,覆盖了当今各种卫星导航系统的载波频段.LNA的输入阻抗和输出阻抗均被匹配到50Ω,电路采用0.18μmCMOS工艺实现.测试结果表明该电路在1.575GHz和1.267GHz两个波段上噪声系数分别为0.88dB和0.78dB,功率增益分别为25.5dB和25.9dB,S11分别为-16dB和-12.5dB,1dB压缩点分别为-23.4dBm和-23.6dBm,1.8V供电电压条件下静态工作电流均为4.0mA.电路在上述两个频段上稳定性均满足要求.     

零中频UHF RFID接收机中的低噪声放大器设计

介绍了一个基于0.18μm标准CMOS工艺,可用于零中频UHF RFID(射频识别)接收机系统的900MHz低噪声放大器.根据射频识别系统的特点与要求对低噪放的结构、匹配、功耗和噪声等问题进行了权衡与分析,仿真结果表明:在1.2V供电时放大器可以提供20.8dB的前向增益,采用源端电感实现匹配并保证噪声性能,噪声系数约为1.1dB,放大器采用电流复用以降低功耗,每级电路从电源电压上抽取10mA左右的工作电流,并使反向隔离度达到-87dB.放大器的IP3为-8.4dBm,1dB压缩点为-18dBm.     

A CMOS Code-Modulated Path-Sharing Multi-Antenna Receiver Front-End

This paper presents the design and implementation of a novel multi-antenna receiver front-end, which is capable of accommodating various multi-antenna schemes including spatial multiplexing (SM), spatial diversity (SD), and beamforming (BF). The use of orthogonal code-modulation at the RF stage of multi-antenna signal paths enables linear combination of all mutually orthogonal code-modulated RF received signals. The combined signal is then fed to a single RF/baseband/ADC chain. In the digital domain, all antenna signals are fully recovered using matched filters. Primary advantages of this architecture include a significant reduction in area and power consumption. Moreover, the path-sharing of multiple RF signals mitigates the issues of LO routing/distribution and cross-talk between receive chains. System-level analyses of variable gain/dynamic range, bandwidth/area/power trade-off, and interferers are presented. Designed for the 5-GHz frequency and fabricated in 0.18 $mu$m CMOS, the 76 mW 2.3 mm$^{2}$ two-antenna receiver front-end prototype achieves a 10$^{-2}$ symbol error rate (SER) at 64, 77, and 78 dBm of input power for SM, SD, and BF, respectively, while providing 21–85 dB gain, 6.2 dB NF, and 10.6 dBm IIP3.      

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards     

A Wideband CMOS RF Front-End Using AC-Coupled Current Mirrored Technique for Multiband Multistandard Mobile TV Tuners

In this paper, a wideband CMOS radio frequency (RF) front-end for various terrestrial mobile digital TV applications such as digital video broadcasting-handheld, terrestrial digital multimedia broadcasting, and integrated services digital broadcasting-terrestrial is proposed. To cover VHF III, UHF, and L bands and reduce the silicon area simultaneously, it employs three low-noise amplifiers and single-to-differential transconductors and shares the rest of the RF front-end. By applying ac-coupled current mirrored technique, the proposed RF front-end has good wideband performance, high linearity, and precise gain control. It is fabricated in 0.18 mum CMOS process and draws 15 mA~20 mA from a 1.8 V supply voltage for each band. It shows a gain of more than 29 dB, noise figure of lower than 2.5 dB, IIP2 of more than 30 dBm, IIP3 of more than -10 dBm for entire bands.     

Analog AGC Circuitry for a CMOS WLAN Receiver

The IEEE 802.11a standard uses orthogonal frequency division multiplexing (OFDM) to allow high data rates in multipath WLAN environments. The high peak-to-average power ratio (PAPR) of OFDM signals, along with stringent settling-time constraints, make conventional closed-loop automatic gain control (AGC) schemes impractical for WLAN receivers. In a direct conversion receiver, AGC and channel-select filtering are performed by analog baseband circuitry. A baseband signal processor using a new open-loop analog gain-control algorithm for OFDM is described. The new AGC algorithm uses switched coarse gain-setting steps followed by an analog open-loop fine gain-setting step to set the final gain of variable gain amplifiers (VGAs). The AGC was implemented in a 0.18-$muhbox m$CMOS process using newly designed circuits including linear VGAs, RMS detectors, and current-mode computation circuitry. Simulation and measurement results verify that the new AGC circuit converges with gain error less than 1dB to the desired level within 5.6$muhbox s$.     

A 24 GHz 6-Bit CMOS Phased-Array Receiver

This letter presents a 24 GHz 6 b phased-array receiver implemented in 0.13 mum CMOS. This design is based on a novel active vector generator that results in wideband quasi-quadrature vectors, which are used to synthesize the desired phase response. The active phase shifter has measured rms gain and phase errors of <0.5 dB and < 2.8deg at 23-24.4 GHz, resulting in a 6 b resolution. The phased-array receiver has a gain of 14 dB, a NF of 6 dB, a 3-dB gain bandwidth of 4.7 GHz and wideband input and output match. The chip consumes 30 mA from a 1.5 V supply with dimensions of 0.66 times 1.25 mm² including pads (0.5 times 1 mm² without pads).     

单片集成CMOS光接收前端电路设计

文中采用SMIC 0.18μm CMOS工艺设计了适用于芯片间光互连的的接收机前端放大电路,将跨阻放大器(TIA)和限幅放大器(LA)集成于同一块芯片中.跨阻放大器采用调制型共源共栅(RGC)结构来提高其带宽,限幅放大器采用二阶有源反馈结构和有源电感负载来获得高的增益带宽积.整个接收机前端放大电路具有85dB中频增益,-3dB带宽为4.36GHz.芯片的面积为1mm×0.7mm,在1.8V电源电压下功耗为144mW.     

A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-μm CMOS

Super-regeneration is re-examined for its simplicity and power efficiency for low-power, short-range communication. A fully integrated super-regenerative receiver in 0.13-mum CMOS is designed to operate in the 2.4 GHz ISM band. A frequency synthesizer scheme tunes the passband. Successive approximation register (SAR) logic driving a current digital-to-analog converter (DAC) calibrates the quench signal to enhance the selectivity of a Q-enhanced filter and the sensitivity of super-regeneration. A single-chip prototype receiver occupies less than 1 mm², has a turn-on time of 83.6 mus, a channel spacing of 10 MHz, and a sensitivity of -90 dBm. A data rate of 500 kb/s is achieved with a power consumption of 2.8 mW, corresponding to energy consumption of 5.6 nJ per received bit.