电镜硅锂X－射线能谱仪的制备及修理技术

第一套电镜Ｓｉ（Ｌｉ）Ｘ射线探测器已经制成，探测器包括灵敏面积为２０ｍｍ￣２Ｓｉ（Ｌｉ）晶体、低温场效应晶体管、光反馈前置放大器、具有７．５μ铍窗的低温装置和７．５升液氮杜瓦瓶。对￣（５５）Ｆｅ５．９ｋｅＶ射线，能量分辨率为１５２ｅＶ。此外报道ＴＲＡＣＯＲ电镜Ｓｉ（Ｌｉ）Ｘ射线探测器修理的结果，修理后能量分辨率为１４８ｅｖ，与原来的结果一样。每天正常的液氮消耗量少于１立升。     

X射线能谱仪Si（Li）探测器的清污处理

本文报道了X射线能谱仪的清除Si(Li)探测器污染的方法     

电镜硅锂X—射线能谱仪的制备及修理技术

第一套电镜Ｘ射线探测器已经制成，探测器包括灵敏面积为２０ｍｍ＾２Ｓｉ（Ｌｉ）晶体、低温场效应晶体管、光反馈前置放大器、具有７．５μ铍窗的低温装置和７．５升液氮杜瓦瓶。对＾５５Ｆｅ５．９ｋｅＶ射线，能量分辨率为１５２ｅｖ。此外报道ＴＲＡＣＯＲ电镜Ｓｉ（Ｌｉ）Ｘ射线探测器修理的结果，修理后能量分辨率为１４８ｅＶ，与原来的结果一样。每天正常的液氮消耗量少于１立升。     

计算机网站的维护技术探讨

信息时代的到来使互联网广泛应用于各行业领域中,然而其中存在的网站安全问题也成为许多用户担忧的重要问题。大多计算机网站设计过程中便存在软件或硬件系统方面的缺陷,加上计算机应用过程中存在的外部病毒入侵或网络黑客使用户信息安全受到一定威胁,这就要求结合计算机网站维护内容采取相关的维护技术。本文主要对网站维护的实际意义、网站维护的主要对象与主要方式以及相关维护技术的应用进行探析。     

计算机故障诊断及维护技术分析

随着计算机技术应用的日益普及，其相关维修维护及故障诊断工作也显得尤为重要。计算机维修技术是在日积月累的实践中积累而成熟的，并通过分享而传播。文章首先分析了计算机故障维修的思路，阐述了常见的计算机故障诊断方法，最后以典型案例探讨了对计算机故障进行维护的技巧，以期给广大计算机使用者提供一定的理论参考。     

粘土矿物EDAX能谱仪定量分析方法的研究

粘土矿物EDAX能谱仪是粘土矿物化学成分分析重要技术之一。与传统化学分析方法相比，扫描电子显微镜加X射线能谱仪分析速度快，谱图直观，微区定位分析准确，样品用量少，损伤小，但对于粉末及颗粒样品的化学成分定量分析精确度较低，尤其是主量元素的定量分析与经典化学分析方法比较分析误差较大。为进一步改进和完善EDAX粘土矿物化学成分定量分析技术，我们初步建立了专门用于粘土矿物（粉末）EDAX定量分析的标样库，并综合使用TEM／SEM粉末试样制备技术改进了目前普遍采用的EDAX粉末样品制备技术。     

计算机机房管理与维护技术

随着科学技术的快速飞跃,计算机主导的办公方式已经成为主流的办公选择;随着技术的更新迭代,易于操作的办公、学习方式,也让人们对计算机的安全性、保密性有了更高要求。不论高校或企业,都是以计算机为信息保存的载体,若机房管理与维护技术安全无保障,则将导致内部数据的丢失,给企业、高校带来重大损失和信息泄露。因此,提升计算机管理部门的管理与维护技术,具有重要意义。     

计算机局域网技术的发展和维护

随着人们生活水平的不断提升,对网络的需求也逐渐增加,而计算机局域网技术在不断满足人们需求努力完善发展的同时,更要保证网络运行的质量,继而更好的提升局域网建设水平。对此本文就计算机局域网技术发展和维护展开分析,希望对于我国网络科技的可持续发展起到积极促进的作用。     

国产扫描电镜上安装X线能谱仪

扫描电子显微镜所成的像是由分解为近百万个的像元逐点依次记录而成的,因而使它在观察表面形貌的同时可进行成分和元素的分析。对于三透镜式扫描电子显微镜,还可以通过电子通道花样进行结晶学研究[1]。近几年,对一台八十年代初国产的BSM-25型扫描电子显微镜作了几方面的改进工作,其中包括高压纹波的减小、高亮度阴极的使用等措施[2,3],使原来15nm的极限分辨率提高到6nm左右;另外在自行研制的YWD-1A型扫描电镜上又进行了低真空条件下的高能电子反射衍射仪研究实验,成功地对一些材料的表面结构进行了分析确定[4]。近来,经过设计,在BSM-25…     

CAD techniques for microwave circuits

In little more than 10 years computer-aided design (CAD) of microwave circuits has moved from dumb terminals on mainframe computers to PCs, and now to powerful RISC workstations. Commercial CAD software now integrates the various stages of microwave circuit design: schematic capture, simulation and layout. This paper reviews the different CAD packages that are available for microwave circuit design. The basic principles employed in the modelling of microstrip circuits are introduced and the reasons for the extensive use of frequency-domain simulations are explored. The developments in nonlinear, electromagnetic and system-level simulation methods are described     

A simplified computer analysis for n-well guard ring efficiency in CMOS circuits

Based on solving the 2-D continuity and current transport equations for electrons injected into the substrate of a n-well CMOS, a quantitative evaluation of n-well guard ring efficiency in terms of the escape electron current is presented. Simulation results show that in the worst-case condition Auger recombination inherent in the heavily-doped substrate of epi-CMOS is responsible for the enhancement of n-well guard ring efficiency. Also, our simulations show that the substrate doping should be as high as possible and the epi-layer thickness should be as thin as possible. Thus a narrow well-type guard ring can be used in order to make efficient use of epi-CMOS for suppressing the escape electron current to a low level so as to preclude latch-up.     

Dielectric isolation techniques for integrated circuits

There has been an increasing interest in producing dielectrically isolated integrated circuits over the past five years for both bipolar and MOS. This impetus stems from the potential of such a technique to increase the operational speed of the circuit, particularly CMOS by reduction of the stray capacitance and a need to reduce the susceptibility of monolithic circuits to photocurrents generated by radiation in space and military environments. In general, early methods for producing dielectrically isolated circuits involved relatively costly lapping and polishing techniques which were generally low yield processes or the development of a completely new process e.g. silicon on sapphire. Recently, preferential anisotropic silicon etchants which may eliminate the mechanical process steps have been announced, as well as the possibility of ion implantation of heavy doses of nitrogen or oxygen at relatively high energies to produce the buried dielectric layer. These new processes will be compared with more traditional methods.     

Power distribution techniques for VLSI circuits

The onchip power distribution problem for highly scaled technologies is investigated. Metal migration and line resistance problems as well as ways to optimize multilayer metal technology for low resistance, low current density, and maximum wirability are also investigated. Fundamental lower limits and the limiting factors of the power-line current density and the voltage drop are studied. Tradeoffs between interconnect wirability and power distribution space are examined. Power routing schemes, as well as the optical number of metal layers and the optimal thickness of each layer, are examined. The results indicate that orders of magnitude improvements in current density and resistive voltage drop can be achieved using very few layers of thick metal whose thicknesses increase rapidly in ascending layers. Also, using the upper layers for power distribution and lower layers for signal routing results in the most wire length available for signal routing.     

A survey of power estimation techniques in VLSI circuits

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed     

A simple but efficient analog computer for simulation of high-speed integrated circuits

An analog computer is described which performs transient simulation of nonsaturated transistor circuits with little expense of time. The computer contains models of bipolar transistors and Schottky-barrier diodes as well as variable capacitors and resistors, all realized in plug-in technique. The parameters of the semiconductor devices are directly and continuously adjustable. Therefore, no special knowledge is required to operate the computer. For the display, a dual-trace oscilloscope with low bandwidth is sufficient because the analog time range lies above 0.1 ms. Compared with the digital computer simulation, this analog method has the advantages of lower costs and less simulation time, the latter allowing fast interaction between designer and computer. The good accuracy of the described simulation method is demonstrated by comparing the simulated and the directly measured transient response of an integrated subnanosecond E/SUP 2/CL gate. Also it is shown how the delay time of this gate depends on the transistor parameters.     

Measurement techniques for monolithic microwave integrated circuits

Introduces the basic technologies that are associated with measurements of monolithic microwave integrated circuits. The use of test fixtures and wafer probe stations at ambient room temperature is reviewed and their role at thermal and cryogenic temperatures is discussed. With the increasing need for performing non-invasive measurements, advances in experimental field probing techniques are explored     

Uniplanar techniques for monolithic microwave integrated circuits

`Uniplanar' techniques have recently been introduced for the design of monolithic microwave integrated circuits (MMICs). The aim of these techniques is to achieve a higher level of integration of circuitry and to overcome the need for through-substrate via holes and the related back-face processing steps. This is achieved by using coplanar waveguide (CPW), slotline, and miniature `thin-film microstrip' transmission-line media as opposed to conventional microstrip. The design and performance of a number of uniplanar MMIC couplers, amplifiers, and other test circuits fabricated using the GEC-Marconi (Caswell) foundry are described     

Dual-threshold voltage techniques for low-power digital circuits

Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks. MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented. A dual-V_t domino logic style that provides the performance equivalent of a purely low-V _t design with the standby leakage characteristic of a purely high-V_t implementation is also proposed