Sorting-based routing algorithms of a photonic ATM cell switch:HiPower

HiPower is a photonic ATM switch having a two-layered structure, consisting of an electrical control layer and an optical transport layer, realized by a detouring hypercube interconnection network structure. Four sorting-based routing algorithms suitable for high-speed hardware control of HiPower are proposed. They are evaluated by computer simulations in terms of delay and cell loss in the switch under uniform traffic distribution. The simulation results suggest that all four methods are acceptable in their traffic characteristics and that the DD method, in which the cell nearest to its destination is given the highest priority in routing, seems to be the most attractive from the hardware implementation viewpoint. It is also confirmed that subpriority sorting based on the number of detourings reduces the delay variance. Simulation results proving that the detouring hypercube network is a practical and powerful architecture for a two-layered ATM cell switch, thus, the HiPower providing high throughput, are given     

Ultrafast photonic ATM switch with optical output buffers

An ultrafast photonic asynchronous transfer mode (ATM) (ULPHA) switch based on a time-division broadcast-and-select network with optical output buffers is presented. The ULPHA switch has an ultra-high throughput and excellent traffic characteristics, since it utilizes ultrashort optical pulses for cell signals and avoids cell contentions by novel optical output buffers. Feasibility studies show that an 80×80 ULPHA switch with 1-Gb/s input/output is possible by applying the present technology, and that more than 1 Tb/s is possible by making a three-stage network using such switches. As an experimental demonstration, 4-bit 40-Gb/s optical cells were generated and certain cells were selected at an output on a self-routing basis. With its high throughput and excellent traffic considerations, the ULPHA switch is a strong candidate for a future large-capacity optical switching node     

Tandem-crosspoint ATM switch with input and output buffers

This letter proposes a high-speed input and output buffering asynchronous transfer mode (ATM) switch, named the tandem-crosspoint (TDXP) switch, The TDXP switch consists of multiple crossbar switch planes, which are connected in tandem at every crosspoint. The TDXP switch does not increase the internal line speed in eliminating head-of-line (HOL) blocking. In addition, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. It is shown that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput     

Broadcast-and-select photonic ATM switch with frequency divisionmultiplexed output buffers

A photonic ATM switch has been developed with frequency division multiplexed (FDM) output buffers. The switch has a broadcast-and-select network architecture using fixed-frequency-channel transmitters and a passive star configuration. Although it has a simple structure, it can provide either broadcast or multicast switching. The output buffers, which resolve cell contentions, are comprised of fiber delay lines that can easily handle signal speed of over 10 Gb/s. Experimental switching of two-multiplexed 10 Gb/s cells with a 2.8-dB power penalty demonstrated high-speed switching     

Design implementation of ATM switch with input priority anddistributed output buffers

A switch architecture for ATM is described which uses a simple priority module to resolve input contention and a distributed design to permit transfer of input cells to the first free output buffer. The switch has been synthesised using VHDL software and a target generic library and can operate at speeds >400 Mbit/s     

Delay analysis of multiserver ATM buffers

A discrete-time multiple-server queue with FIFO discipline and deterministic service times of one slot each is studied. A relationship between the mass-functions of the delay of an arbitrary customer, and the system contents, during an arbitrary slot is derived under the most general conditions possible     

Optical buffers for variable length packets

This letter addresses the problem of dimensioning fiber delay lines for optical buffers in a network scenario where packets are asynchronous and of variable length. The focus is placed on providing a simple analytical model to dimension the basic time unit of the fiber delay line, as the crucial parameter that determines the queueing performance     

Analysis of storage and retrieval policies for ATM buffers

To satisfy the different performance (QoS) requirements of the different types of ATM traffic, several control strategies have been described in the literature. The control strategies that operate on cell level are combinations of storage and retrieval priority policies. In the comparisons, two classes of traffic are distinguished, one class (LL) requiring a low loss probability and one class (LD) requiring a low average delay (jitter). By using the delay-loss plane — plotting the loss of the LL cells against the delay of the LD cells — the performance of the various storage and (state-dependent) retrieval policies has been compared for both stationary and time-varying traffic. In a relative ranking of the different policies, the LDOLL threshold policies give the best results, in addition to creating the possibility of setting the threshold according to the desired delay-loss trade-off.     

A multistage ATM switch with interstage buffers

Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.^1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log₂ N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log₂ N time periods. Performance analysis shows that the additional delay is small.     

Optimum architecture for input queuing ATM switches

An input queueing ATM switch architecture employing the contention resolution called 'scheduling algorithm' is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.<>     

Self-firing cell scheduler for input queueing ATM switches

The authors propose a simple cell scheduler for input queueing ATM switches. The proposed self-firing cell scheduler consists of N² processing elements connected by a two dimensional torus network, where each processing element can determine the diagonal by itself in a distributed manner. It allows a simple implementation for high speed ATM switches     

Large-scale WDM star-based photonic ATM switches

This paper describes the large-scale photonic asynchronous transfer mode (ATM) switching systems being developed in NTT Laboratories. It uses wavelength division multiplexing (WDM) techniques to attack 1 TB/s throughput. The architecture is a simple star with modular structure and effectively combines optical WDM techniques and electrical control circuits. Recent achievements in important key technologies leading to the realization of large-scale photonic ATM switches based on the architecture are described. We show that we can obtain a 320 Gb/s system that can tolerate the polarization and wavelength dependencies of optical devices. Our experiments using rack-mounted prototypes demonstrate the feasibility of our architecture. The experiments showed stable system operation and high-speed WDM switching capability up to the total optical bandwidth of 12.8 nm, as well as successful 10 Gb/s 4×4 broadcast-and-select and 2.5 Gb/s 16×16 wavelength-routing switch operations     

ATM and wireless experiments for remote lectures

We examine our remote lecture experiments using ATM and UNII wireless devices. We discussed which functions should be improved in the current distance-learning system. The Unlicensed National Information Infrastructure/Shared Unlicensed Personal Radio Network (UNII/SUPERNet) wireless devices are introduced for achieving economical distance-learning systems. Two experiments of remote lectures are detailed: a wireless experiment between two buildings in the Philippines and an ATM experiment between Japan and the United States     

Wavelength routing-based photonic packet buffers and theirapplications in photonic packet switching systems

Photonic packet buffers are essential components in photonic packet switching systems. We present a wavelength routing-based photonic packet buffer based on a state-of-the-art arrayed-waveguide grating (AWG) multiplexer. We show how this new packet buffer can be effectively used in the implementation of photonic packet switching systems. We also propose and examine two different photonic packet switch architectures     

A high-performance input access scheme for ATM multicast switching

In this paper, we propose an input access scheme for input-queued ATM multicast switches, achieving high system throughput, low packet delay and packet loss probability. Multicast and unicast packets of each input port are separately queued. Multicast queues take priority over the unicast queues, and both types of queues are fairly served in a cyclic-priority access discipline. In particular, each unicast queue is handled on a window-service basis, and each multicast packet is switched in a one-shot scheduling manner. To evaluate the performance of the access scheme, we propose an approximate analysis based on a simplified cyclic-priority model for anN×N finite-buffer multicast switch possessing Bernoulli multicast and unicast arrivals, with window-service (for unicasting) and one-shot scheduling (for multicasting) both taken into account. Finally, we show simulation results to demonstrate the accuracy of the approximate analysis and the superiority of the scheme over existing schemes with respect to normalized system throughput, mean packet delay, and packet loss probability.An earlier version of this paper appeared in IEEE ICC'96.     

Parallel contention resolution control for input queueing ATM switches

Input queueing ATM switches requiring fast contentional resolution control have been negatively affected by long turn-around time (TAT) due to the distance between an input port controller and a centralised contention controller. A parallel contention resolution control for input queueing switches is presented. The proposed control allows a TAT of more than one cell slot, resulting in the potential development of a centralised contention controller for an ATM switch with an aggregate capacity of 1 Tbit/s.<>     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

Analysis of input and output queueing for nonblocking ATM switches

A switch model for ATM networks is analyzed. Its interconnection network is internally nonblocking and is provided with dedicated input and output queues, one per switch inlet and one per switch outlet. The switch operates with an internal speed-up: more than one packet per slot can be transferred from the head-of-line positions of the input queues to each output queue by the interconnection network. Two different operation modes are considered for the interaction between input and output queues: backpressure mode and queue loss mode. The analytical model developed for the evaluation of the switch performance under random traffic assumes an infinite size for the switch, arbitrary values for input and output queue size, as well as for the speed-up factor. Switch throughput, packet delay and loss performance are evaluated and the analytical model accuracy is assessed using computer simulation results     

Burst-based scheduling algorithms for non-blocking ATM switcheswith multiple input queues

This letter quantitatively evaluates two alternative approaches to the scheduling of traffic streams in a high-speed ATM switch with multiple input queues. Specifically, we compare a previously proposed algorithm, called parallel iterative matching (PIM)-which is a cell-based scheduling algorithm-with our newly proposed algorithm-which is a burst-based variation of the PIM scheduling algorithm. Extensive simulation results demonstrate that burst-based PIM scheduling outperforms cell-based PIM scheduling under a variety of realistic parameters     

EXPLOITation of an ATM testbed for broadband experiments andapplications

Based in Basel, Switzerland, the RACE II project R2061, `EXPLOIT', is making a major contribution towards achieving the RACE programme's aim of introducing integrated broadband communication (IBC) services on a European Community-wide basis by 1995. The author describes the interconnectivity features that are being developed to enable interworking with other `broadband islands', and the traffic experiments that will be performed to provide much-needed information from real sources on the ATM-sensitive areas of traffic control, resource management and performance