器件结构和材料质量对GaAs MESFET噪声系数的影响

本文从栅源串联电阻R_s和有效栅长L_f两方面论述了深槽自对准斜蒸栅结构可明显减小R_s与缩短L_f,有利于降低器件的噪声系数。 本文还用相关栅长L_a和器件在低温下的性能说明GaAs材料的质量对器件噪声系数的影响。提高GaAs半绝缘衬底和缓冲层质量以及与有源层交界面附近的迁移率,可较明显地缩短相关栅长L_a,降低器件噪声。 采用这一器件结构,并选用质量较高的GaAs材料,制得的MESFET,在12GHz下相关增益G_a为7.5dB,噪声系数NF_(min)为1.4dB,与理论预计值相符。     

4GHz低噪声GaAs MESFET参数研究

本文论述4GHz低噪声GaAs MESFET在缩短栅长L,减小寄生电阻(R_s+R_g)的同时需减小等效噪声电阻R_n,以获得较理想的增益和噪声性能.本文还叙述了器件主要参数的控制,并指出在亚微米栅长时栅边缘效应对器件噪声系数的影响.     

0.15μm Y型栅高In沟道GaAs PHEMT低噪声器件设计

设计了一种GaAs PHEMT低噪声器件。通过电子束直写手段实现了0.15μm Y型栅,对栅型优化以减小器件栅电阻和栅寄生电容。采用高In含量的沟道设计以改善沟道电子输运特性,采用InGaAs/GaAs复合帽层以改善欧姆接触特性,并通过低噪声工艺流程制作了4×50μm GaAs PHEMT器件。测试结果表明,器件fT达到80GHz,在10GHz处最小噪声系数小于0.4dB,相关增益大于10dB。对于0.15μm栅长GaAs PHEMT器件来说,这是很好的结果。     

低噪声高电子迁移率晶体管

采用直接描绘电子束刻蚀法制造了用于低噪声极高频(EHF)放大器的亚半微米栅长的高电子迁移率晶体管。调制掺杂的外延结构是用分子束外延法生长的,在10~(12)电子/cm~2的电子浓度时,室温下的霍耳迁移率为8000cm~2/V·sec,液氮温度下为77,600cm~2/V·sec。通过腐蚀通n~+GaAs接触层的凹楷的方法确定了窄达0.28μm的栅长。0.4μm栅长的耗尽型器件的直流跨导超过260mS/mm。对0.37μm栅长的器件,进行了噪声系数和相关增益的测量,在34GHz下,得到了2.7dB的噪声系数和5.9dB的相关增益。还制造了具有240mS/mm跨导的增强型器件,对0.35μm的栅长,在18GHz下,它们的噪声系数为1.5dB,相关增益为10.5dB。这些结果可以和已报导过的最好的0.25μm栅长的GaAsMESFET的噪声系数相匹敌。     

采用MOCVD的低噪声HEMT

用金属有机化学汽相淀积法(MOCVD)研制出了低噪声HEMTAlGaAs/GaAs异质结器件。这种HEMT的栅长为0.5μm、栅宽为200μm。室温下,频率为12GHz时,达到的最小噪声系数为0.83dB,相应增益为12.5dB。测量也证实了栅键合点的数目对不同栅宽的噪声系数影响的计算结果。在低温下工作时,观察到器件的噪声系数显著提高,特别是与常规GaAsMESFET相比,更是如此。一个为DBS接收系统设计的二极放大器,其初级使用了HEMT,在11.7～12.2GHz的范围内噪声系数低于2.0dB。     

X波段噪声系数1.4分贝的GaAs MESFET

<正>南京固体器件研究所已研制成功栅长0.5μm、栅宽280μm,以φ2mm陶瓷金属微带管壳封装的实用化的GaAs MESFET.在9.5GHz下测得最佳水平器件的噪声系数为1.4dB,相关增益大于7dB.大部分器件的噪声系数在1.5～2.5dB范围内.与日本NEC的NE388MESFET进行同等条件下测试对比,说明测试结果可靠.     

超低噪声毫米波PHEMT

以AlGaAs/InGaAs/GaAs为基础的十分之一微米栅长PHEMT器件在43GHz下提供了最优良的低噪声性能。测量的室温器件噪声系数为1.32dB(噪声温度=103K),相关增益6.7dB,在17K物理温度下,噪声系数为0.36dB(噪声温度=25K),相关增益为6.9dB,这是目前报道的43GHz下GaAs基器件的最低噪声系数。     

采用离子注入MOCVD缓冲层制作的MESFET

采用离子注入的金属有机化学汽相淀积(MOCVD)缓冲层制作了低噪声GaAs金属-半导体场效应晶体管(MESFET)。在12GHz下,0.5μm(栅长)×300μm(栅宽)的FET器件的噪声系数可达1.46dB,相关增益达到10.20dB。此结果证明,采用离子注入MOCVD缓冲层能制成极好的GaAs LNFET,它可以与采用AsCl_3汽相外延和分子束外延制作的类似器件所得的最佳结果相比拟。     

GaAs双栅MESFET的设计与性能分析

本文将双栅MESFET模拟成两个级联的单栅MESFET,用三端信号流通图来分析它的性能特征.并将双栅MESFET当作一个短的行波管来说明其工作原理的物理本质.可以看出,它是一种在微波领域中有着广泛用途的多功能器件.本文还讨论了GaAs双栅MESFET的设计.采用金属剥离工艺制作的双指状、深凹糟1微米栅的双栅MESFET,在4千兆赫下相关增益为20分贝,噪声系数为1.9分贝,在8千兆赫下相关增益为18分贝,噪声系数为2.8分贝.     

用分子束外延法制作的GaAs MESFET

本文报导了在分子束外延(MBE)生长的沟道层上制作的“T”形Ti/W/Au栅GaAs肖特基势垒场效应晶体管的噪声性能。标称栅长约为0.7μm,总栅宽250μm。典型噪声系数和相应增益在4GHz下分别为1.2dB和14dB;在12GHz下分别为1.9dB和8.5dB。据我们所知,这些值是关于用MBE生长的GaAs制作的器件迄今所报导的最好结果。这些初步结果表明MBE用于高质量的GaAsFET是很有希望的。     

A noise model for high electron mobility transistors

A model to explain the noise properties for AlGaAs/GaAs HEMT's, AlGaAs/InGaAs/GaAs pseudomorphic HEMT's (P-HEMT's) and GaAs/AlGaAs inverted HEMT's (I-HEMT's) is presented. The model Is based on a self-consistent solution of Schrodinger and Poisson's equations. The influence of the drain-source current, frequency and device parameters on the minimum noise figure F_min and minimum noise temperature T_min, for different HEMT structures are presented. The study shows that P-HEMT's have a better noise performance than the normal and inverted HEMT's. The present model predicts that a long gate P-HEMT device will exhibit a better noise performance than a conventional HEMT. There is a range of doped epilayer thickness where minimum noise figure is a minimum for pseudomorphic HEMT's which is not observed in conventional and inverted HEMT's. The calculated noise properties are compared with experimental data and the results show excellent agreement for all devices     

Optimal noise figure of microwave GaAs MESFET's

The optimal value of the minimum noise figure Foof GaAs MESFET's is expressed in terms of either representative equivalent circuit elements or geometrical and material parameters in simple analytical forms. These expressions are derived on a semiempirical basis. The predicted values of Fofor sample GaAs MESFET's using these expressions are in good agreement with the measured values at microwave frequencies. The expressions are then applied to show design optimization for low-noise devices. This exercise indicates that shortening the gate length and minimizing the parasitic gate and source resistances are essential to lower Fo. Moreover, a simple shortening of the gate length may not bring an improved Founless the unit gate width is accordingly narrowed. The maximum value of the unit gate width is defined as the width above which the gate metallization resistance becomes greater than the source series resistance. Short-gate GaAs MESFET's with optimized designs promise a superior noise performance at microwave frequencies throughKband. The predicted values of Foat 20 GHz, for example, for a half-micrometer gate device and a quarter-micrometer gate device are 3 and 2 dB, respectively. These devices could be fabricated with the current technology.     

Noise characteristics of InGaP-gated PHEMTs under high current and thermal accelerated stresses

The degradation mechanisms of the noise characteristics of InGaP-gated low-noise pseudomorphic high-electron mobility transistors (PHEMTs) under accelerated stresses through dc and thermal stresses are investigated. The devices used were metal-organic chemical vapor deposition-grown In/sub 0.49/Ga/sub 0.51/P/In/sub 0.15/Ga/sub 0.85/As/GaAs low noise PHEMT structures with the gate dimensions of 0.25/spl times/160 /spl mu/m/sup 2/. The key noise/effect parameters of devices including 1) related to the deep-trap behavior in device, 2) source/gate resistances, and 3) gate to source capacitance and intrinsic transconductance are discussed. Based on the dc characteristics under dc and thermal stresses, the variations of the current-voltage curve, the diode characteristics (Schottky gate) with related trapping/detrapping phenomena induced by impact ionization and the variation of the depletion in gate-drain region are also investigated. The high reliability of InGaP low noise PHEMTs is demonstrated by the extremely small variations of the minimum noise figure and the associated power gain at 12 GHz after dc and thermal stresses.     

A comprehensive analytical model for III-V compound MISFET's

A one-dimensional analytical model for III-V compound deep-depletion-mode MISFET's is developed. The model calculates transconductance, drain resistance, and gate capacitance beyond current saturation where these devices are normally operated-a regime not treated by other MISFET models. It is shown that insulator thicknesses less than 50 nm and surface state densities less than 1 × 10¹²eV^-1. cm^-2will be required for optimum MISFET devices. In a comparison of the expected performance differences between GaAs, InP, and InGaAs FET devices with similar geometries, it is shown that InP and InGaAs MISFET's will have lower gate capacitance, a greater cut-off frequency, and up to 2-dB improvement in minimum noise figure compared with a GaAs MESFET. Device characteristics predicted by this model agree with measured values to an accuracy of ±20 percent, which is well within the accuracy with which the modeled input parameters can be measured. This represents a factor of two improvement in accuracy when compared to other MISFET models. The model predicts the characteristics expected for a MESFET device in the limit of zero insulator thickness.     

Noise in two-tier matrix amplifiers

A noise theory for the two-tier matrix amplifier is developed that permits the computation of the amplifier's noise figure as a function of the active device and circuit parameters. The computed results based on the noise parameters of a GaAs MESFET with gate dimensions 0.25 μm×200 μm are discussed. In addition, a comparative study is done on the performance data from a 2×4 matrix amplifier and its equivalent two-stage distributed amplifier. Finally, the noise characteristics of two 2×4 matrix amplifiers incorporating GaAs MESFETs processed on either ion-implanted or VPE (vapor-phase epitaxial) substrate material are compared with those measured on actual amplifiers     

RF noise in 0.18-/spl mu/m and 0.13-/spl mu/m MOSFETs

Studied the gate finger number and gate length dependence on minimum noise figure (NF/sub min/) in deep submicrometer MOSFETs. A lowest NF/sub min/ of 0.93 dB is measured in 0.18-/spl mu/m MOSFET at 5.8 GHz as increasing finger number to 50 fingers, but increases abnormally when above 50. The scaling gate length to 0.13 /spl mu/m shows larger NFmin than the 0.18-/spl mu/m case at the same finger number. From the analysis of a well-calibrated device model, the abnormal finger number dependence is due to the combined effect of reducing gate resistance and increasing substrate loss as increasing finger number. The scaling to 0.13-/spl mu/m MOSFET gives higher NF/sub min/ due to the higher gate resistance and a modified T-gate structure proposed to optimize the NF/sub min/ for further scaling down of the MOSFET.     

Comparison of GaAs MESFET noise figures

A method of comparing noise figures of GaAs MESFET's is presented. The noise measure M graphed against gate length for devices having the lowest value of M gives a figure of merit graph against which other devices may be compared. This is useful in determining the relative value of material and process, improvements for a given gate length.     

Low-noise HEMT using MOCVD

Low-noise HEMT AlGaAs/GaAs heterostructure devices have been developed using metal organic chemical vapor deposition (MOCVD). The HEMT's with 0.5-µm-long and 200-µm-wide gates have shown a minimum noise figure of 0.83 dB with an associated gain of 12.5 dB at 12 GHz at room temperature. Measurements have confirmed calculations on the effect of the number of gate bonding pads On the noise figure for different gate Widths. Substantial noise figure improvement was observed Under low-temperature operation, especially compared to conventional GaAs MESFET's. A two-stage amplifier designed for DBS reception using the HEMT in the first stage has displayed a noise figure under 2.0 dB from 11.7 to 12.2 GHz.     

Noise associated with interdigitated gate structures in RFsubmicron MOSFETs

CMOS technologies have gained considerable attention and have raised expectations for employment in RF transceivers. The shrinkage of the MOSFET device dimensions along with the relatively wide gate electrode devices needed to accommodate RF applications lead to reconsideration of the noise properties of submicron MOSFETs. In this paper, we present the noise properties associated with interconnect resistors of an interdigitated structure and the resulting noise source (strong function of the number of fingers) is evaluated against the other noise sources present in the device such as channel thermal noise, induced gate noise, and resistive gate voltage noise. Short channel effects have been taken into account for the evaluation of these noise sources and two-port analysis performed in order to calculate minimum noise figure and optimum input resistance for noise matching