A Single-Die 124 dB Stereo Audio Delta-Sigma ADC With 111 dB THD

This paper presents a highly power-efficient stereo delta-sigma ADC designed for high-precision applications, with measured inter-channel isolation over 130 dB. This design adopts a single-loop, fifth-order, 33 level analog modulator with positive and negative feedforward paths. An interpolated multilevel quantizer with unevenly weighted quantization levels replaces a conventional 5-bit flash type quantizer. These new techniques suppress signal dependent energy inside the delta-sigma loop, reduce internal channel coupling and power consumption. Manufactured in 0.35 mum double poly, three metal CMOS process, the single-die chip includes two analog modulators, on-chip bandgap reference circuit, decimation filter and serial interface circuits. The core die area is around 14.8 mm². The ADC achieves 124 dB dynamic range (A-weighted), -111 dB THD over 20 kHz bandwidth. Total power consumption is less than 330 mW.     

A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver

A 0.8 V third-order multibit $DeltaSigma$ DAC with headphone driver is described. It is the first sub-1 V audio $DeltaSigma$ DAC with integrated on-chip headphone driver. The dual-channel operation in digital section was efficiently realized with a time-interleaved single-channel hardware and extra registers. Using novel DAC architecture suitable for low-voltage operation, the analog section requires only one opamp per channel for the D/A conversion, low-pass filtering, and driving the headphone. Two prototype ICs (separate digital and analog chips), implemented in a 0.35$ muhbox{m}$ CMOS process, achieved an 88 dB dynamic range, while consuming 2.6 mW from a 0.8 V supply.      

一种基于SAR量化器的低功耗音频Δ-Σ调制器

基于0.18 μm CMOS工艺,采用离散3阶前馈结构,设计了一种低功耗音频调制器。采用4位SAR量化器,相比于Flash ADC类型的量化器,减少了比较器的个数,降低了量化器的功耗。与传统的利用有源加法器对输入信号和积分器输出进行求和的方式不同,该设计利用SAR量化器实现输入信号的求和,极大地降低了整个调制器的功耗。此外,调制器采用增益提高型低功耗放大器结构,相比于套筒式共源共栅放大器、折叠式共源共栅放大器等传统类型的放大器,节省了功耗。仿真结果表明,在20 kHz信号带宽、1.8 V电源电压下,调制器的SNDR为94.6 dB,SFDR为107 dB,功耗仅为145 μW。     

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 $mu$m CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.      

A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy

A 6-bit highly digital flash ADC is implemented in a 0.18 $mu{hbox {m}}$ CMOS process. The ADC operates in the subthreshold regime down to 200 mV and employs comparator redundancy and reconfigurability to improve linearity. The low-voltage sampling switch employs voltage boosting, stacking and feedback to reduce leakage. Common-mode rejection is implemented digitally via an IIR filter. The minimum FOM of the ADC is 125 fJ/conversion-step at a 0.4 V supply, where it achieves an ENOB of 5.05 at 400 kS/s. The clocked comparators' switching thresholds are adjusted through a combination of device sizing and stacking. A quadratic relationship between the amount of device stacking and the strength of an input network in the subthreshold regime is derived, demonstrating an advantage of stacking over device width scaling to adjust comparator thresholds.      

A 1.5 V 12-bit 16 MSPS CMOS Pipelined ADC with 68 dB Dynamic Range

A 1.5 V, 12-bit, 16 MSPS analog-to-digital converter was implemented in 0.25 μm 1P5 M standard CMOS process with MIM capacitors. The converter achieves a peak SNDR of 66.5 dB with 5.12 MSPS and that of 63.0 dB with 16.384 MSPS. The dynamic range is 68 dB under both sampling rates. The maximum INL of ±0.8 LSB and DNL of ±0.5 LSB were measured under 5.12 MSPS, while those of 16.384 MSPS decreased to ±3.1 and ±1.0 LSB, respectively. An embedded bandgap reference circuit that provides the conversion voltage range is also presented with 1.5 V supply voltage. The total power consumption of this converter was 138 mW under 16.384 MSPS or 97 mW under 5.12 MSPS. The total area of this chip is 2.8 × 2.5 mm. This chip was implemented without calibration or trimming approaches.     

基于0-35μm工艺的Delta—Sigma ADC实现

在众多音频模数转换器中,Delta-Sigma是一种很流行的结构,其内部采用位MD转换器,因此其对模拟信号处理部分的电路要求远远小于对整个电路的精度要求。在局部模块的精度较低时也能正常工作。Delta—Sigma A/D主要应用于中低带宽的音频信号,讨论采用AMSO．35μmPDK实现模数转换电路。该电路核心部分采用Folded-Cascodet结构的差动放大器,仿真结果表明该结构的电路能较稳定地工作于低频段。     

一种100dB输出动态范围的1.5bit功率数模转换器

介绍了一种1.5bit的双声道过采样数模转换器.它把过采样数模转换器和D类功率放大器这两部分集成在一起,不需要额外的低通滤波器即可直接驱动耳机扬声器等语音设备.它无需消耗直流功耗,对于常用的8Ω扬声器负载,其最大输出功率可达436mW,输出动态范围大于100dB.该电路采用TSMC 0.18μm工艺实现.芯片面积为0.28mm2,其中数字电路的电源电压为1.8V,D类功率放大器的电源电压为3.3V.     

A Sub-1V Fourth-Order Bandpass Delta-Sigma Modulator

A sub-1V fourth-order bandpass delta-sigma modulator is presented in this paper. Using the switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without using voltage multipliers or bootstrapping switches. A two-path structure is applied to relax the settling requirement. Implemented in a 0.25-m one-poly, five-metal standard CMOS process, the prototype modulator exhibits a signal-to-noise-plus-distortion ratio (SNDR) of 58.2 db and a dynamic range (DR) of 64 db in a 60 KHz signal bandwidth centered at 1.25 MHz while consuming 2.5 mW and occupying an active area of 2.11 mm².     

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC

A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm², and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.     

An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and $-$98 dB THD

A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. Realized in a 0.18 $mu{hbox{m}}$ CMOS technology, it provides 81 dB SNDR, 82 dB dynamic range, and $-$98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 $~$V power supply (analog power 4.4 mW, digital power 3.7$~$ mW). Its figure-of-merit is 0.25 pJ/conversion-step, which is among the best reported for discrete-time delta-sigma ADCs in wideband applications.      

一款调制器和过采样率可配置的单芯片1.2V 95-55dB动态范围的Delta-Sigma模数转换器设计

A single die 1.2 V multi-stage noise shaping（Mash） 2-2 delta sigma analog to digital converter（ADC）for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range（DR） for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb（CIC） filter and two half-band filters（HBF）. The serial peripheral interface（SPI） can be used to adjust the sampling frequency and the oversampling ratio（OSR）. The design was fabricated in a 0.13 m CMOS process with an area of 0.91 mm2and a total power of 5.2 mW. The measurement results show that the dynamic range（DR） of the proposed ADC can change from 55to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range（SFDR） and signal-to-noise distortion ratio（SNDR） can get 99 dB and 86.5 dB, respectively.     

一种具有84.8dB SFDR和72dB SNDR的14位80MS/s CMOS模数转换器

本文描述了一种基于0.35μm CMOS工艺的14位采样率80MS/s的流水线型模数转换器的设计. 所提出的电荷分享校正技术消除了与信号相关的电荷注入效应, 加上片内的低抖动时钟电路, 保证了模数转换器的高动态性能. 一种信号电容开关技术和高对称版图减小了电容失配, 确保了模数转换器的总线性度. 测试结果表明, 该模数转换器在36.7MHz输入频率下, 实现了11.6位的有效位, 84.8dB的无杂散动态范围(SFDR), 72dB的信号噪声失真比(SNDR), 在无校准情况下获得了＋0.63/－0.6 LSB的微分非线性和＋1.3/－0.9 LSB的积分非线性. 输入频率200MHz时,仍然可以保持75dB的SFDR和59dB的SNDR.     

一个0.9V低电压双端输出第二代电流传输器的设计

介绍一个0.9 V低电压双端输出第二代电流传输器(DOCCⅡ)的设计。输入级采用衬底驱动MOSFET有效地避免了阈值电压的限制;同时采用了局部正反馈技术提高了带宽增益,因此DOCCII获得了更好的电压跟随特性。该设计电路在标准0.18μm CMOS工艺下,采用Cadence Spectre和BSIM3v3模型对其进行了调试和仿真。仿真结果显示该DOCCII具有4.8MHz的带宽,同时具有比较高的线性度和很好的输入输出电阻。     

利用先进的热电偶和高分辨率△-∑ADC实现高精度温度测量

引言 热电偶广泛用于各种温度检测。热电偶设计的最新进展,以及新标准和算法的出现,大大扩展了工作温度范围和精度。     

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

This paper describes a wideband high-linearity $Delta Sigma $ ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled $Delta Sigma $ ADC were realized in a 0.18- $mu{hbox {m}}$ CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (${rm SFDR} > {hbox {100~dB}}$, ${rm THD}= -{hbox {98~dB}}$) and an SNDR of 79 dB in a 4.2 MHz signal band.      

一种基于开关型运放和双向循环移位DWA的0.9V Delta-Sigma模数转换器

This paper presents a low-power high-precision switched-opamp(SO)-based delta-sigma(△Σ) analog-to -digital converter(ADC).The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging (DCS-DWA) technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit(FOM) of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.     

一种430mW具有77.2dB SNR和97.6dB SFDR的16位170MS/s CMOS流水线型模数转换器

本文描述了一种采用0.18um CMOS工艺实现的16位170MS/s采样率的流水线型模数转换器。该设计采用了一种改进的数字校准算法并对采样前端进行了线性化处理,从而实现了很好的SFDR性能。该模数转换器采用了较大的满幅输入范围,从而大大缩减了采样电容的大小,这有利于实现低功耗和高采样率。测试结果显示,该模数转换器在10MHz输入时实现了77.2dBFS SNR和97.6dBc SFDR指标。并且,当输入信号频率升至300MHz时,SFDR依然能够保持在80dBc以上。该模数转换器采用1.8V电源电压,功耗为430mW,面积为17mm2     

A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR

This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious flee dynamic range (SFDR) performance and low power dissipation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration. The ADC, with a total die area of 3. 1 × 2.1 mm~2, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.