Material science for quantum computing with atom chips

In its most general form, the atom chip is a device in which neutral or charged particles are positioned in an isolating environment such as vacuum (or even a carbon solid state lattice) near the chip surface. The chip may then be used to interact in a highly controlled manner with the quantum state. I outline the importance of material science to quantum computing (QC) with atom chips, where the latter may be utilized for many, if not all, suggested implementations of QC. Material science is important both for enhancing the control coupling to the quantum system for preparation and manipulation as well as measurement, and for suppressing the uncontrolled coupling giving rise to low fidelity through static and dynamic effects such as potential corrugations and noise. As a case study, atom chips for neutral ground state atoms are analyzed and it is shown that nanofabricated wires will allow for more than 10⁴ gate operations when considering spin-flips and decoherence. The effects of fabrication imperfections and the Casimir–Polder force are also analyzed. In addition, alternative approaches to current-carrying wires are briefly described. Finally, an outlook of what materials and geometries may be required is presented, as well as an outline of directions for further study.     

Microtrap arrays on magnetic film atom chips for quantum information science

We present two different strategies for developing a quantum information science platform, based on our experimental results with magnetic microtrap arrays on a magnetic-film atom chip. The first strategy aims for mesoscopic ensemble qubits in a lattice of ~5 μm period, so that qubits can be individually addressed and interactions can be mediated by Rydberg excitations. The second strategy aims for direct quantum simulators using sub-optical lattices of ~100 nm period. These would allow the realization of condensed matter inspired quantum many-body systems, such as Hubbard models in new parameter regimes. The two approaches raise quite different issues, some of which are identified and discussed.     

芯片表面气泡瑕疵检测方法

为解决芯片工业生产过程的瑕疵检测问题,提出了一种快速准确的瑕疵检测方法.针对图像采集过程中光照不均匀问题,给出了一种基于均值切块的快速光照补偿方法;另外,为了进行气泡瑕疵的特征提取,给出了一种简单的线性图像融合方法;最后,利用最大熵分割方法分割融合图像,并对瑕疵点进行分割和标记.实验结果表明,在小幅度改变原图像的基础上...     

A new classification approach for neural networks hardware: from standards chips to embedded systems on chip

The aim of this paper is to propose a new classification approach of artificial neural networks hardware. Our motivation behind this work is justified by the following two arguments: first, during the last two decades a lot of approaches have been proposed for classification of neural networks hardware. However, at present there is not a clear consensus on classification criteria and performances. Second, with the evolution of the microelectronic technology and the design tools and techniques, new artificial neural networks (ANNs) implementations have been proposed, but they are not taken into consideration in the existing classification approaches of ANN hardware. In this paper, we propose a new approach for classification of neural networks hardware. The paper is organized in three parts: in the first part we review most of existing approaches proposed in the literature during the period 1990–2010 and show the advantages and disadvantages of each one. In the second part, we propose a new classification approach that takes into account most of consensual elements in one hand and in the other hand it takes into consideration the evolution of the design technology of integrated circuits and the design techniques. In the third part, we review examples of neural hardware achievements from industrial, academic and research institutions. According to our classification approach, these achievements range from standard chips to VLSI ASICs, FPGA and embedded systems on chip. Finally, we enumerate design issues that are still posed. This could help to give new directions for future research work.     

Feasibility of PSO-ANN model for predicting surface settlement caused by tunneling

The potential surface settlement, especially in urban areas, is one of the most hazardous factors in subway and other infrastructure tunnel excavations. Therefore, accurate prediction of maximum surface settlement (MSS) is essential to minimize the possible risk of damage. This paper presents a new hybrid model of artificial neural network (ANN) optimized by particle swarm optimization (PSO) for prediction of MSS. Here, this combination is abbreviated using PSO-ANN. To indicate the performance capacity of the PSO-ANN model in predicting MSS, a pre-developed ANN model was also developed. To construct the mentioned models, horizontal to vertical stress ratio, cohesion and Young’s modulus were set as input parameters, whereas MSS was considered as system output. A database consisting of 143 data sets, obtained from the line No. 2 of Karaj subway, in Iran, was used to develop the predictive models. The performance of the predictive models was evaluated by comparing performance prediction parameters, including root mean square error (RMSE), variance account for (VAF) and coefficient correlation (R ²). The results indicate that the proposed PSO-ANN model is able to predict MSS with a higher degree of accuracy in comparison with the ANN results. In addition, the results of sensitivity analysis show that the horizontal to vertical stress ratio has slightly higher effect of MSS compared to other model inputs.     

Feasibility of imperialist competitive algorithm to predict the surface settlement induced by tunneling

Surface settlement is considered as an adverse effect induced by tunneling in the civil projects. This paper proposes the use of the imperialist competitive algorithm (ICA) for predicting the maximum surface settlement (MMS) resulting from the tunneling. For this work, three forms of equations, i.e., linear, quadratic and power are developed and their weights are then optimized/updated with the ICA. The requirement datasets were collected from the line No. 2 of Karaj urban railway, in Iran. In the ICA models, vertical to horizontal stress ratio, cohesion and Young’s modulus, as the effective parameters on the MSS, are adopted as the inputs. The statistical performance parameters such as root mean square error (RMSE), mean bias error (MBE), and square correlation coefficient (R²) are presented and compared to validate the performance. The findings indicate that the developed ICA-based models with the R² of 0.979, 0.948 and 0.941, obtained from ICA power, ICA quadratic and ICA linear models, respectively, are the acceptable and accurate tools to estimate MSS, and furthermore prove their prediction capability for future research works in this field.

     

Investigations of the capillary effect for gripping silicon chips

Capillary forces in microsystems are very powerful. During wet etching they can cause sticking or even destruction of moving or underetched parts of the microstructure. But capillary forces can also be used in a controlled way for gripping and handling of micro objects. This paper shows that forces exerted on a silicon chip with dimensions of 4 × 4 mm² and a thickness of 600 m are approximately 200-times higher than the inertial force of the chip. The force exerted is dependent on the gap height and can be estimated for different drop sizes with simple estimation formulas or with solutions from differential equations. A numerical solution gives a better understanding of the non-linear behavior of a capillary liquid in a gap. The result of the investigation shows the behavior of the capillary effect in small gaps. For small gap widths and liquid volumes the force developed is overestimated by conventional formulas and calculations. Additionally the general behavior of liquids in microgaps are shown, which also can help to design other liquid based microsystems e.g. micro biological sensor systems.The author is thankful for the support given for this work by Prof. Dr.-Ing. L. Kiesewetter from the Technical University of Brandenburg/Germany.     

Matrix method for simulating the tunneling transfer

We develop an efficient approach for computer simulation of stationary scattering and tunneling transfer across an arbitrary one-dimensional potential barrier. New algorithms and programs were worked out and tested and the convergence of the method in question was examined.     

一种基于多层感知器的机器人快速推理学习方法

从多层感知器原理分析出发,该文提出一种适变学习因子法用于对学习算法的改进,并将改进的算法用于“逃避”机器人推理网络的实例样本的学习。仿真结果表明,改进后BP的算法可显著加速网络训练速度,并且学习过程具有较好的收敛性及较强的鲁棒性.     

On the integration of design and test for chips embedding MEMS

This article illustrates how fault-based, defect-oriented test approaches can be applied to the problem of testing the next generation of chips embedding MEMS     

Utilization of albumin-based sensor chips for the detection of metal content and characterization of metal–protein interaction by surface plasmon resonance

We report here the use of albumin-based biosensor chips for the determination of metal content and characterization of metal–protein interaction by surface plasmon resonance. Bovine serum albumin was immobilized onto a carboxymethylated dextran matrix and used for metal detection. The temperature for the analysis was defined and the highest interaction was observed at 25 °C. The albumin sensor chip binds cadmium, zinc or nickel in a concentration-dependent manner, but not magnesium, manganese and calcium. The optimal buffer condition used for the analysis contains 0.01 M HEPES, pH 7.4, 1 mM NaCl and 0.005% Tween-20. Using this condition, a linear calibration curve within the range of 10⁻⁸ to 10⁻⁴ M can be established for the metals. However, a dramatic increase in binding capacity was observed when metal concentration was higher than 10⁻⁴ M and reached a plateau at 10⁻² M. The detection limit for Cd can reach as low as 1 ppb. When measuring a solution containing two species of metal ions with the albumin chip, an additive effect was observed for Ni and Zn. However, 20–30% reduction in resonance response was found upon mixing Cd with Zn or Ni. These observations are consistent with the binding characteristics of albumin. The feasibility of measuring serum metal content by the albumin chip was examined. A linear calibration curve can be established if the samples are boiled and passed through a gel filtration column. The binding affinity of metal with albumin can also be achieved by using the sensor chip. The binding affinity follows the order of Ni > Zn > Cd. These results indicate that the albumin-based sensor chip is useful not only in the quantification of metal content, but also in the characterization of the biochemical properties of albumin.     

Arctangent entropy: a new fast threshold segmentation entropy for light colored character image on semiconductor chip surface

Pattern Analysis and Applications - When using the Tsallis entropy method to segment light colored character images on the semiconductor chip surface, it consumes relatively long CPU time. In order...     

Reducing the Dimensions of Texture Features for Image Retrieval Using Multi-layer Neural Networks

This paper presents neural network-based dimension reduction of texture features in content-based image retrieval. In particular, we highlight the usefulness of hetero-associative neural networks to this task, and also propose a scheme to combine the hetero-associative and auto-associative functions. A multichannel Gabor-filtering approach is used to derive 30-dimensional texture features from a set of homogeneous texture images. Multi-layer feedforward neural networks are then trained to reduce the number of feature dimensions. Our results show that the methods lead to a reduction of up to 30% while keeping or even improving the performance of similarity ranking. This has the benefit of alleviating the ill-effects of the high dimensionality of features in current image indexing methods and resulting in significant speeding up retrieval rates. Results using principal component analysis are also provided for comparison. Receiveed: 6 July 1998?,Received in revised form: 6 November 1998?Accepted: 15 December 1998     

Capillary self-alignment of polygonal chips: a generalization for the shift-restoring force

Capillary-driven self-alignment using droplets is currently extensively investigated for self-assembly and microassembly technology. In this technique, surface tension forces associated to capillary pinning create restoring forces and torques that tend to bring the moving part into the alignment. So far, most studies have addressed the problem of square chip alignment on a dedicated patch of a wafer, aiming to achieve 3D microelectronics. In this study, we investigate the shift-restoring forces for more complex moving parts such as regular—convex and non-convex—polygons and regular polygons with regular polygonal cavities. A closed-form approximate expression is derived for each of these polygonal geometries; this expression agrees with the numerical results obtained with the Surface Evolver software. For small shifts, it is found that the restoring force does not depend on the shift direction or on the polygonal shape. In order to tackle the problem of microsystem packaging, an extension of the theory is done for polygonal shapes pierced with connection vias (channels), and a closed form of the shift-restoring force is derived for these geometries and again checked against the numerical model. In this case, the restoring force depends on the shift direction. Finally, a non-dimensional number, the shift number, is proposed that indicates the isotropic or anisotropic behavior of the chip according to the shift direction.     

Fast and inexpensive method for the fabrication of transparent pressure-resistant microfluidic chips

The recent rise of high-pressure applications in microfluidics has led to the development of different types of pressure-resistant microfluidic chips. For the most part, however, the fabrication methods require clean room facilities, as well as specific equipment and expertise. Furthermore, the resulting microfluidic chips are not always well suited to flow visualization and optical measurements. Herein, we present a method that allows rapid and inexpensive prototyping of optically transparent microfluidic chips that resist pressures of at least 200 bar. The fabrication method is based on UV-curable off-stoichiometry thiol-ene epoxy (OSTE+) polymer, which is chemically bonded to glass. The reliability of the device was verified by pressure tests using CO₂, showing resistance without failure up to at least 200 bar at ambient temperature. The microchips also resisted operation at high pressure for several hours at a temperature of 40 °C. These results show that the polymer structure and the chemical bond with the glass are not affected by high-pressure CO₂. Opportunities for flow visualization are illustrated by high-pressure two-phase flow shadowgraphy experiments. These microfluidic chips are of specific interest for use with supercritical CO₂ and for optical characterization of phase transitions and multiphase flow under near-critical and critical CO₂ conditions.     

Synchronizing the IEEE 1149.1 test access port for chip leveltestability

IEEE STD 1149.9 is a widely accepted testability standard in the industry. Although its mandatory provisions focus narrowly on board level assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standard's TAP to be used at the system level for general system-level test and maintenance tasks and at the chip level for accessing chip-level testability features. Chip-level applications thus far have used the port for accessing the chip's scan design or for simple triggering of on-chip built-in self-test features via the RUNBIST instruction. Applications requiring general access to chipwide testability features that operate at the full chip-clock rate have been rare, primarily because of one of the standard's basic tenets-namely, its dedicated test clock. This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features