40Gb／s波分系统设备技术

随着40Gb／s端口路由器的出现,未来几年内40Gb／s波分系统设备将取代现有的10Gb／s波分系统设备,就像前几年10Gb／s波分系统设备取代2．5Gb／s波分系统设备一样。然而,40Gb／s波分系统有很多传输限制因素,包括光放大器自发辐射噪声、光纤非线性效应、色散、偏振模色散等等。为实现40Gb／s的波分传输,采取新型调制码型、可调色散补偿、偏振模色散补偿等措施至关重要。     

Transoceanic WDM System with More Than 100 Gb/s Capacity

This paper reviews several key technologies to realize a transoceanic wavelength-division-multiplexing (WDM) system with more than 100 Gb/s capacity. The key technologies include a novel gain equalization scheme, a broadband erbium-doped fiber amplifier, a chromatic dispersion compensation technique at a transmitter, and a RZ modulation format. Employing these new technologies, we successfully demonstrated a 32 channel 5.3 Gb/s (total capacity of 170 Gb/s) WDM signal transmission over 9879 km.     

10Gb/s GaAs PHEMT光接收机前置放大器

简要分析了光接收机分布式前置放大器所具有的宽带优势,研制出了一种利用南京电子器件研究所0．5μm标准GaAs PHEMT工艺实现的10 Gb/s分布式前置放大器。该前置放大器采用损耗补偿技术,由七个共源共栅级联的单元组成,测试结果表明,该分布式前置放大器可以工作在10 Gb/s速率上。     

40G比特/秒 FSK传输链接的理论和实证研究

A novel Frequency Shift Keying (FSK) transmitter that can operate at 40Gb/s and above is proposed. The transmission characteristics of a FSK signal at 40Gb/s are investigated under varying dispersion management. The resilience of compensation ratio and power level is obtained. We also experimentally demonstrate transmission over 100km SMF and transparent wavelength conversion based on a semiconductor optical amplifier.     

Polarization-insensitive wavelength conversion up to 10 Gb/s basedon four-wave mixing in a semiconductor optical amplifier

Polarization-insensitive wavelength conversion at 2.5 and 10 Gb/s using four-wave mixing in a bulk semiconductor optical amplifier is reported. At 10 Gb/s, a conversion range from 6.4-nm wavelength downshift to 4.8-nm upshift has been demonstrated. The conversion efficiency and signal-to-noise ratio versus conversion range are also characterized     

Compact 2.5 Gb/s Burst‐Mode Receiver with Optimum APD Gain for XG‐PON1 and GPON Applications

This letter presents a compact 2.5 Gb/s burst‐mode receiver using the first reported monolithic amplifier IC developed with 0.25 …m SiGe BiCMOS technology. With optimum avalanche photodiode gain, the receiver module can obtain a fast response, high sensitivity and wide dynamic range, satisfying the overhead timing and various power specifications for a 2.5 Gb/s next‐generation passive optical network (PON), as well as a legacy 1.25 Gb/s PON in the upstream.     

2.5 Gb/s laser-driver GaAS IC

A laser-diode driver GaAs IC incorporating an optional NRZ/RZ (non-return-to-zero/return-to-zero) conversion facility, having ECL (emitter-coupled logic) and SCFL (source-coupled FET logic)-compatible inputs and providing a 0-60-mA adjustable output current into a 50-Ω/5-V termination at bit rates up to 2 Gb/s NRZ and maintaining a clear eye opening of 50 mA at 2.5 Gb/s NRZ bit rate has been designed, using a commercial 1-μm gate-length (F_τ=12 GHz) GaAs MESFET foundry service. The high maximum output current is obtained by implementing the output driver as a cascode differential amplifier. The logic circuitry implemented using a novel, DCAL (diode-clamped active-load) SCFL family, which is based on gate-width scaling rather than on absolute values, so that the on-chip logic voltage swing is less sensitive to process variations than conventional SCFL. A 60% improvement in noise margin is also obtained. To verify laser driving performance a back-to-back optical-fiber transmission experiment was performed, giving good optical eye diagrams at 2.5 Gb/s. The electrooptical interplay between laser-diode driver and laser-diode has been demonstrated using SPICE simulations     

10Gb/s 0.18μm CMOS光接收机前端放大电路

介绍了利用TSMC 0.18μm CMON工艺设计的应用于SDH STM-64速率级(10Gb/s)光接收机前端放大电路。该电路由前置放大器和作为主放大器的限幅放大器构成,其中前置放大器采用RGC形式的互阻放大器实现,限幅放大器采用改进的Cherry—Hooper结构。模拟结果表明该电路可以工作在10Gb/s速率上。     

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25???m CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625-MHz clock are 9.4 and 46.3?ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. The recovered and frequency divided 625?MHz clock has a phase noise of ?83.8 dBc/Hz at 20?kHz offset in response to 2.5?Gb/s PRBS input data (2²³?C1), and the 2.5?Gb/s PRBS data has been demultiplexed into four 625?Mb/s data. The power dissipation is only 0.3?W under a single 3.3 V supply (excluding output buffers).     

5Gb/s 0.25μm CMOS限幅放大器

采用TSMC 0.25μm CMOS技术设计实现了高速低功耗光纤通信用限幅放大器.该放大器采用有源电感负载技术和放大器直接耦合技术以提高增益,拓展带宽,降低功耗并保持了良好的噪声性能.电路采用3.3V单电源供电,电路增益可达50dB,输入动态范围小于5mVpp,最高工作速率可达7Gb/s,均方根抖动小于0.03UI.此外核心电路功耗小于40mW,芯片面积仅为0.70mm×0.70mm.可满足2.5,3.125和5Gb/s三个速率级的光纤通信系统的要求.     

Inline amplifier transmission experiments over 4500 km at 2.5 Gb/s

An inline amplifier system was constructed with erbium-doped fiber amplifiers spaced at 100 km and 80 km intervals. The system transmits 2.5 Gb/s signals over 2500 km with continuous-phase frequency-shift-keying heterodyne detection and over 4500 km with intensity-modulation direct detection. With respect to amplifier output signal power levels, it is experimentally shown that there exists a dynamic range within which long-distance signal transmission can be achieved with only small receiver sensitivity degradation. The range's upper and lower limits are determined by fiber nonlinearities and amplifier noise characteristics, respectively     

An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 m CMOS

A pipelined analog-to-digital converter (ADC) uses switched-capacitor stages that settle in two steps that occur sequentially in time. The first step of settling places charge onto the load capacitance using charge pumps, and the second fulfills the settling requirements using typical negative feedback around an operational amplifier. Hence, the design combines the efficiency of a fast charge-transfer phase with the gain and noise-immunity advantages of amplifier-driven settling. Improved conversion efficiency results from a higher ratio of current delivered to the load to that consumed in static biasing. Additional circuitry constrains critical amplifier node voltages during the charge transfer, facilitating a graceful transition to amplifier-driven settling. The two-step settling technique is demonstrated in a 2.5 bit/stage 10-bit pipelined ADC that consumes 11.1 mW while sampling a 21.3 MHz input signal at 42 MS/s. The resulting SNDR is 55.6 dB $rm (ENOB = 8.94)$ and the SFDR is 67.5 dB.      

Performance and scalability of a single-stage SOA switch for 10/spl times/10 gb/s wavelength striped packet routing

This letter reports successful routing of 10/spl times/10 Gb/s multiwavelength optical packets using single-stage semiconductor optical amplifier switches. Performance under switching is assessed with up to ten wavelengths with particular emphasis being placed on the limit of operation. A 15.2-dB power margin is demonstrated which allows at least eight port connections with a commercially available 0-dBm output 10-Gb/s transmitter and -21-dBm sensitivity receiver.     

Constraints on the design of single-channel, high-capacity (>10Gb/s) soliton systems

We have examined the design constraints of single-channel soliton systems operating at high data rates (>10 Gb/s). While Gordon-Haus timing jitter is the most important effect for 10 Gb/s transoceanic systems, it is fiber perturbations arising from discrete in-line amplification that severely limit the transmission distance and amplifier spacing at higher data rates. Dispersion-decreasing fiber or distributed optical amplification, both of which locally balance dispersion and fiber nonlinearities, could eliminate this constraint and extend the regime of stable soliton transmission     

12路并行30Gb/s 0.18μm CMOS光接收前端放大器

给出了一个采用TSMC 0.18μm CMOS工艺设计并实现的12路30Gb/s并行光接收前端放大器.电路设计采用RGC结构和噪声优化技术,克服了CMOS光检测器大寄生电容造成的带宽不够的问题.测试结果表明,在2pF的寄生电容下单信道传输速率达到了2.5Gb/s,在0.8mVpp输入下得到了清晰的眼图.提出了一种同时采用p+保护环(PGR)、n+保护环(NGR)和深n阱(DNW)的并行放大器隔离结构,有效地抑制了并行放大器之间的串扰,减小了放大器之间的衬底耦合噪声.测量结果表明,这种结构与PGR和PGR+NGR相比,在1GHz时放大器之间的隔离度分别提高了29.2和8.1dB,在2GHz时放大器之间的隔离度分别提高了8.1和2.5dB.芯片采用1.8V电源供电,单路前端放大器的功耗为85mW,12路总功耗约为1W.     

2.5Gb/s SDH/SONET指针处理器芯片实现

提出了一种2.5Gb/s同步光纤网络SDH/SONET中指针处理器芯片实现结构.指针处理器执行指针解释、通路开销性能监测功能,产生新的与系统时钟同步的STM/STS帧.指针解释模块对输入STM/STS通道的H1/H2指针进行解释,支持48通道的指针解释和每个通道的通路开销监测.采用4路总线流水线结构,77.76MHz的系统时钟,即可实时处理2.5Gb/s的SDH/SONET数据.采用TSMC 0.13μm工艺流片,技术指标符合ITU-T标准.     

5-Gb/s XOR optical gate based on cross-polarization modulation insemiconductor optical amplifiers

We demonstrate a new design for a XOR optical gate operating in the GHz regime using the cross-polarization modulation effect in a semiconductor optical amplifier. Dynamic and optically controlled polarization rotation in the devices is used to control the output power of the device. Static extinction ratio of the order of 20 dB can be obtained. Bit rate doubling at rate of 1.2 and 2.5 Gb/s have been demonstrated     

Optical demultiplexing at 6 Gb/s using a semiconductor laser amplifier as an optical gate

A semiconductor laser amplifier (SLA) has been employed successfully for optical demultiplexing in two-channel optical time division multiplexed system experiments at 6 and 2 Gb/s. Demultiplexing of 6-Gb/s (2-Gb/s) signals was demonstrated with a power penalty of 1.6 dB (3.0 dB) at bit error rates of 10/sup -9/. It is also shown that a reduction of the generated amplified spontaneous emission can be obtained by optical gating/demultiplexing for systems incorporating inline amplifiers. A 0.5-dB improvement in sensitivity was achieved as a result of using an SLA for demultiplexing from 2.0 to 1.0 Gb/s in a system with one inline Er/sup 3+/-doped fiber amplifier.<>     

Fabrication of Transimpedance Amplifier Module and Post‐Amplifier Module for 40 Gb/s Optical Communication Systems

The design and performance of an InGaAs/InP transimpedance amplifier and post amplifier for 40 Gb/s receiver applications are presented. We fabricated the 40 Gb/s transimpedance amplifier and post amplifier using InGaAs/InP heterojunction bipolar transistor (HBT) technology. The developed InGaAs/InP HBTs show a cut‐off frequency (f_T) of 129 GHz and a maximum oscillation frequency (f_max) of 175 GHz. The developed transimpedance amplifier provides a bandwidth of 33.5 GHz and a gain of 40.1 dBΩ. A 40 Gb/s data clean eye with 146 mV amplitude of the transimpedance amplifier module is achieved. The fabricated post amplifier demonstrates a very wide bandwidth of 36 GHz and a gain of 20.2 dB. The post‐amplifier module was fabricated using a Teflon PCB substrate and shows a good eye opening and an output voltage swing above 520 mV.     

A 34 Gb/s Distributed 2:1 MUX and CMU Using 0.18$muhbox m$CMOS

A 34 Gb/s 2:1 serializer consisting of a CMOS MUX and CMU using a 0.18$muhbox m$SiGe BiCMOS process is presented. The serializer is based on distributed amplifier topology realized using spiral inductors. The circuit also includes an on-chip 2-channel$2^7-1$PRBS generator. The 34 Gb/s serial output has single-ended voltage swing of 380 mV with rise/fall time of 13 ps, and measured ISI is less than 5 ps p-p.