基于MOS管的新型转换开关在集成电路测试中的应用

为了克服继电器在集成电路测试板上触点烧蚀故障率较高,断开时易产生电磁干扰和开关时间过长等缺点,提出了一种基于MOS管的新型转换开关电路,能更加有效地测试芯片,显著降低芯片的成本。本文详细讨论了集成电路测试的要素和基本原则,继电器在测试板上的应用及其局限性,基于MOS管的新型转换开关电路的特点及控制原理。仿真结果表明,该电路在10v电源电压下开关的转换速度为70μs,工作频率可达100kHz以上,灵敏度高,适用于集成电路测试。     

In-process voltage stressing to increase reliability of MOS integrated circuits

Time-dependent dielectric breakdown of gate oxides is one of the principal failure mechanisms of MOS integrated circuits. Voltage stressing of completed devices, which has been used to screen oxide defects and to thereby increase product reliability, is less effective with scaled high-density MOS integrated circuits because of limitations in the voltage which can be applied. Inprocess voltage stressing of silicon wafers, prior to completion of wafer processing, offers a feasible technique for achieving an effective voltage screen. Several possible techniques for inprocess voltage stressing are described, and the advantages and limitations of these are outlined. Data are presented showing typical fast-ramp dielectric breakdown distributions for MOS transistor arrays with an oxide thickness of 35 and 50 nm. Time-dependent dielectric breakdown distribution data on devices from the same wafers indicate that with all MOS transistors of an integrated circuit connected in parallel, as in one type of inprocess voltage stressing, defective oxide sites can be screened in periods of time ranging from a few seconds to hours. Inprocess voltage stressing, by decreasing susceptibility of completed devices to time-dependent dielectric breakdown, can substantially increase MOS integrated circuit reliability.     

设计高频高压场效应晶体管的一些考虑

高频高压场效应晶体管(LDMOS)是功率MOS器件中同时具有高频高压性能的一种器件,也是目前广泛用于HVIC(高压集成电路)及PIC(功率集成)电路的器件之一。本文从结构上描述了器件的高频、高压特性,并提出了一些可提高这些性能的措施和设计思想。     

A method for the measurement of the turn-on condition in MOS transistors

Metal-oxide-silicon (MOS) integrated circuits usually consist of MOS transistors and interconnections. Both, interconnections and MOS transistors are built up of diffused regions in the bulk substrate and conductive strips (metal or polycrystalline silicon) on top of the oxide. For proper electrical operation the interconnection paths should not exhibit MOS transistor effects, i.e. should not induce inversion layers at the silicon-silicon dioxide interface. Furthermore from a designer's point of view it will be desired that some transistors operate in the saturated mode and others in the non-saturated mode. This implies that a method for the determination of the turn-on of channel conduction is highly desirable for designers of MOS integrated circuits. Using a straightforward definition of turn-on, a fast and simple measurement method will be presented for the determination of the relation between gate voltage and diffused region voltage for MOST structures in the turn-on condition.     

MOS-bipolar monolithic integrated circuit technology

A technique for the fabrication of p-channel MOS transistors and bipolar transistors within monolithic integrated circuits is described. Total process compatibility has been achieved without compromising either the n-p-n bipolar or p-channel MOS characteristics. The technology developed is similar to that used for conventional integrated circuits until the channel oxidation step, A low temperature oxidation followed by a high temperature anneal process that produces negligible changes in preceding diffusion profiles was used to form this oxide. Bias temperature tests of MOS capacitors have shown the oxide to be reproducibly free of contamination. A high slew rate MOS bipolar operational amplifier has been designed and fabricated on 0.045- by 0.045-in chip using the new technology. Typical characteristics are slew rate =80 V/µs voltage gain = 70 dB. The MOS transistors are used as active loads and level shifters in this circuit and provide a much improved frequency response over conventional circuits using p-n-p lateral transistors.     

Limitations in microelectronics — II. Bipolar technology

The physical phenomena which will ultimately limit miniaturization of planar bipolar integrated circuits are examined. The maximum packing density is obtained by minimizing the supply voltage and the size of the devices. The minimum transistor size is determined by junction breakdown, punch through and doping fluctuations. For circuits that are fully active the maximum number of circuit functions per chip is determined by power dissipation. The packing density of read-only memories becomes limited by the area occupied by devices and interconnections. The limitations of MOS and bipolar technologies are compared. It is concluded that read-only memories will reach approximately the same performance and packing density with MOS and bipolar technologies, while fully active circuits will reach the highest levels of integration with dynamic MOS or complementary MOS technologies.     

Silicon-gate technology

Silicon-gate technology provides an advantageous approach for implementing large-scale integrated arrays of field-effect transistors. Its advantages?principally resulting from the low threshold voltage and the self-aligned gate structure buried under an insulator?ease the problem of interfacing these circuits to bipolar integrated circuits and increase both their performance and functional density, making MOS integrated circuits easier and more economical to use. This article reviews recent progress with this technology and shows its application to the construction of complex digital functions as illustrated by a memory circuit.     

Fast-access BiCMOS SRAM architecture with a VSSgenerator

A high-speed BiCMOS ECL (emitter coupled logic) interface SRAM (static RAM) architecture is described. To obtain high-speed operation for scaled-down devices, such as MOSFETs with a feature size of 0.8 μm or less and with a small MOS level, a new SRAM architecture featuring all-bipolar peripheral circuits and CMOS memory cells with V_SS generator has been developed. Two key circuits, a V_SS generator and a current switch level converter, are described in detail. These circuits reduce the external supply voltage to the internal MOS level, thus permitting high-speed SRAM operation. To demonstrate the effectiveness of the concept, a 256 kb SRAM with an address access time of 5 ns is described     

Calculator-aided design of MOS integrated circuits

A set of programs has been developed for the characterization of the d.c. and transient behavior of MOS integrated circuits. The d.c. analysis program calculates and plots the voltage transfer and power dissipation characteristic of a MOS inverter approached from a new point of view. The algorithm enables the characterization of basic MOS IC cells on desktop calculators. The program for the transient characterization calculates and plots the output waveform of three simple MOS cells most often occurring in MOS IC's.The MOS transistor is simulated in terms of a four-terminal large signal model described by device processing parameters. Complex MOS IC's can be also characterized by appropriate combining of these programs.     

GaAs基E/D PHEMT技术单片集成微波开关及其逻辑控制电路

利用GaAs基E/D PHEMT技术单片集成微波开关及其逻辑控制电路的制作工艺和设计方法,采用0.8μm GaAsE/D PHEMT工艺,制备出性能良好的解码器功能内置的DC～10GHz SPDT MMIC,基本实现逻辑电路与开关电路的集成.开关电路在DC～10GHz内插入损耗小于1.6dB,隔离度大于24dB;整个电路只需要1位控制信号,有效地减少了开关电路的控制端口数目,节省了芯片面积,为GaAs多功能电路的研究奠定了基础.     

Computer analysis of the double-diffused MOS transistor for integrated circuits

The effective length of an MOS transistor can be made narrow by using double diffusion similar to a bipolar transistor. Computations were conducted for an n-channel double-diffused transistor with different surface concentrations, channel lengths, channel gradients, surface-states densities, and substrate concentrations. A shorter channel length and a higher surface-state density, e.g.langle1, 1, 1ranglecrystal, gave a higher drain current and transconductance. The maximum transconductance in many cases occurs at low gate voltages. The computations indicate that a gain-bandwidth product in the gigahertz range can be expected when the graded channel region is less than 1 µm. The difference between an n-type substrate and a p-type substrate is not substantial. The analysis is also useful in predicting the performance of any integrated logic circuit using the diffused enhancement transistor as the active switch and a depletion-mode transistor (without a diffused channel) as the load device. The computation indicates that satisfactory performance can be obtained using a load device with the same geometry and an ON voltage of only a fraction of a volt, This revelation indicates that double-diffused channel MOS transistors not only give higher speed but also smaller chip area for integrated circuits and a lower supply voltage (hence less power dissipation).     

Integration of 5-V CMOS and High-Voltage Devices for Display Driver Applications

Reduced surface field lateral double-diffused MOS transistors for the driving circuits of plasma display panel and field emission display in the 120 V region have been integrated for the first time into a low-voltage 1.2 μm analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers and also the cost of fabrication. The lateral double-diffused MOS transistor with a drift length of 6.0 μm and a breakdown voltage greater than 150 V was self-isolated to the low voltage CMOS ICs. The measured specific onresistance of the lateral double-diffused MOS is 4.8 mΩ·cm² at a gate voltage of 5 V.     

Comparing MOS and bipolar integrated circuits

In terms of speed and speed/power performance, bipolar integrated circuits are superior to metal-oxide-semiconductor integrated circuits. This superiority is based on the high transconductance inherent in bipolar transistors and is technology-independent. For the MOS case, transconductance is highly technology-dependent, and hence the performance difference will probably diminish in the future. Comparisons of the two technologies in their mid-1966 forms are made; the bipolar performance advantage in most cases is between 10 and 100. MOS integrated circuits have an area-per-function advantage ratio of about 5 for equivalent-function circuits, but a ratio of between 5 and 10 when circuits exploiting the unique MOS properties are considered. In addition, MOS processing is simpler than bipolar processing by approximately 40 percent.     

Generalized theory and realization of a voltage-controlled negative resistance MOS device (lambda MOSFET)

A generalized theoretical approach used to predict circuits which exhibit the three-terminal negative resistance MOS characteristic is presented. The main structure of the positive feedback circuit is accomplished by connecting the drain and gate terminals of an n-channel enhancement mode MOSFET with the input and output terminals of an inverter circuit. The characteristic parameters such as the peak current, the peak voltage, the negative resistance, and the valley voltage are derived in a generalized form. Based on the theoretical predictions, several high density integrated circuits that give rise to a voltage-controlled negative resistance characteristic were fabricated and are described.     

An MOS transistor model for analog circuit design

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model     

A monolithic 200-V CMOS analog switch

A new high-voltage CMOS technology is described which can increase the operating voltage of these circuits to more than 200 V. This represents approximately an order of magnitude improvement over present-day commercially available CMOS devices. The technology is straightforward to implement and uses n-channel MOS transistors and high-voltage p-channel devices. As an example of the capability of the technology, a monolithic quad CMOS analog switch has been fabricated which can handle 200-V, 0.3-A analog signals, with a dynamic range in excess of 150 dB.     

一种低电压、高增益电荷泵

电荷泵在低压电路中扮演着重要的角色。作为片上电荷泵,其面临的主要问题是：电压增益、电压纹波和面积效率。该文提出了一种新型的电荷泵电路,它采用辅助电荷泵、电平转移电路结构来产生不同摆幅的时钟,该时钟被用来驱动开关管的栅极,以有效控制开关管的电导,提高电压增益。由于采用PMOS管作为开关管,传输过程中避免了阈值电压损失。仿真结果显示,与以往文献中提到的电荷泵结构相比,该电荷泵具有更高的电压增益,开启时间短,纹波小,在低压应用环境优势更为突出。     

Ion-implanted complementary MOS transistors in low-voltage circuits

Simple but reasonably accurate equations are derived which describe MOS transistor operation in the weak inversion region near turn-on. These equations are used to find the transfer characteristics of complementary MOS inverters. The smallest supply voltage at which these circuits will function is approximately 8kT/q. A boron ion implantation is used for adjusting MOST turn-on voltage for low-voltage circuits.