1-V power supply high-speed digital circuit technology withmultithreshold-voltage CMOS

1-V power supply high-speed low-power digital circuit technology with 0.5-μm multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-μW/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-μm CMOS process     

A low supply voltage high PSRR voltage reference in CMOS process

This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm², a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm/°C and a standard deviation of 20 mV without trimming     

A high-speed low-power tri-state driver flip flop for ultra-lowsupply voltage GaAs heterojunction FET LSI's

This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage, which is 1/5 of the minimum value reported for D-FFs so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage     

A small chip size 2 W, 62% efficient HBT MMIC for 3 V PCNapplications

This work describes the L-band low voltage (⩾1.6 V) power performance of AlGAs/GaAs heterojunction bipolar transistors (HBTs), their modeling and the design of a 2-W monolithic microwave integrated circuit (MMIC) for 3-V wireless mobile PCN applications (1800 MHz). The two-stage MMIC achieves 62% power-added efficiency (PAE) and 33 dB of linear gain, at a very small chip size of 1.2 mm². To our knowledge this is the best combination of power performance data for wireless applications demonstrated so far for a MMIC. The chip size is about a factor of four smaller than comparable MMIC's known before. The MMIC offers the potential both for low cost production due to small chip size, single voltage supply, and high performance at the same time     

A GaAs MOSFET with a liquid phase oxidized gate

Low leakage current density (as low as 10^-8 A/cm² at an applied voltage of 5 V) and high breakdown electrical field (larger than 4.5 MV/cm) of the liquid phase chemical-enhanced oxidized GaAs insulating layer enable application to the GaAs MOSFET. The oxide layer is found to be a composite of Ga₂O₃, As, and As₂O₃. The n-channel depletion mode GaAs MOSFET's are demonstrated and the I-V curves with complete pinch-off and saturation characteristics can be seen. A transconductance larger than 30 mS/mm can be achieved which is even better than that of MESFET's fabricated on the same wafer structure     

High-Frequency Si-MOSFET's

Silicon (Si-) MOSFET's with 0.8-mu m channel, made by conventional technology and optimized for microwave applications, have noise figures of 3.7 dB at 4 GHz and maximum frequencies of oscillation of 10 to 12 GHz. The noise and radio-frequency (RF) small signal performance are only slightly affected by double ion implantation of the channel region, used to shift the threshold voltage from - 2 V to +0.2 V. Excess noise is generated in the implanted MOSFET's for lower V/sub DS/ values than in unimplanted ones. The variation of the noise parameters with drain current is lower in implanted devices. The RF equivalent circuit analysis indicates negligible parasitic lead resistances, but high feedback capacitance. A comparison with GaAs MESFET's of the buried channel type showed the Si-MOSFET's to have lower third-order harmonic distortion when driven by a 1-GHz signal source.     

A 23-ns 4-Mb CMOS SRAM with 0.2-μA standby current

A 4-Mb CMOS SRAM having 0.2-μA standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics at a low operating cycle time without access delay. A 0.5-μm CMOS, four-level poly, two-level metal technology with a polysilicon PMOS load memory cell, yielded a small cell area of 17 μm² and the very small standby current. A quadruple-array, word-decoder architecture allowed a small chip area of 122 mm²     

Sub-half-micrometer width 2-D MESFET

Two-dimensional (2-D) MESFET's having sub-half-micron channel widths have been fabricated on double-δ-doped Al_0.24Ga _0.76As/In_0.18Ga_0.82As/GaAs heterostructures. The 2-D MESFET operates like a normal transistor at room temperature but uses very few electrons in the channel (about 500 at peak current and 5 at threshold). Also, the Narrow Channel Effect (NCE) and Drain-Induced Barrier Lowering (DIBL) (two effects which limit the minimum power operation in conventional devices) have been practically eliminated. The 0.4 micron wide device had an ON/OFF current ratio of 10⁵, a peak transconductance of 100 mS/mm, a threshold voltage of 0.3 V, a saturation voltage of 0.2 V, and a subthreshold ideality factor of 1.1. The 2-D MESFET DCFL inverter had a switching voltage and noise margin of 0.35 V and 0.26 V, respectively, at 0.8 V supply. These room temperature results suggest that the 2-D MESFET is an excellent candidate for future low power digital electronics applications     

Advantages of metallic-amorphous-Silicon-gate FET's in GaAs LSI applications

A Schottky barrier as high as 1 V is obtained for contact between a ternary amorphous film, a-Si-Ge-B, and an n-type GaAs crystal. A metallic-amorphous-silicon-gate FET (MASFET) was made using the amorphous film as a gate contact. GaAs MASFET characteristics are superior to GaAs MESFET characteristics in application to LSI's with a DCFL configuration because the DCFL circuits with the GaAs MASFET's provide a logic level as high as 0.94 V and widen the circuit operation margin. Full operation is obtained from a 1 Kword × 2 bit SRAM with GaAs MASFET's, which is considered to be mainly due to the wide operation margin. The measured propagation delay time of the DCFL inverter is 34 ps at supply voltageV_{DD} = 1.5V and power consumption of 1.9 mW/gate.     

An analog beam-forming circuit for ultrasound imaging usingswitched-current delay lines

A mixed-signal integrated circuit implements 1120 analog memory points arranged in 16 independent fully programmable delay lines in a 0.8 μm CMOS technology. It demonstrates the feasibility of large scale mixed-mode circuits using the switched current technique. The die area of the chip is 72 mm² and incorporates 16 rather large and complex analog blocks, which take advantage of special design techniques developed in order to keep power consumption at a reasonable level and to eliminate second-order effects due to long power and signal lines. At the nominal 64 MHz sampling rate, harmonic distortion is -48 dB, dynamic range is above 60 dB, and power consumption is 1.22 W from a single 5 V supply     

A high efficiency GaAs MCM power amplifier for 1.9 GHz digitalcordless telephones

A GaAs MCM power amplifier has been developed for 1.9-GHz digital cordless telephones. Power-added efficiency of 40.2% and P_1dB of 22.2 dBm have been obtained at drain supply voltage of 3.6 V. Adoption of the multilayer MCM structure, i.e., multilayer microwave integrated circuits (MuMIC), and on-chip ferroelectric capacitors successfully reduced the GaAs total chip area to be 1.1 mm². We consider that the MuMIC is the most effective candidate for high frequency circuits     

A supply-noise-insensitive CMOS PLL with a voltage regulator usingDC-DC capacitive converter

A 500-MHz supply-noise-insensitive CMOS phase-locked loop (PLL) with a voltage regulator using a capacitive dc-dc converter (VRCC) achieves a jitter level of 30-ps RMS for quiet supply, and 42-ps RMS for 600-mV supply noise, with a locking range of 110 to 850 MHz. The worst-case power supply noise rejection (PSNR) using the VRCC shows -45 dB in the mid-frequency band. The circuit is fabricated in a 0.35-μm 3.3-V standard digital CMOS process and occupies 2.3 mm². The power consumption at 3.3 V including buffer is 42 mW at 500 MHz     

Quasi-normally-off MESFET logic for high-performance GaAs IC's

The stringent pinchoff voltage control required by the normally-off GaAs FET logic approach appears to be a very serious limitation to its LSI capability. This paper presents the operation and performance of a more tolerant logic IC approach intented to succeed in manufacturing high-performance digital GaAs IC's with LSI complexities. The so-called "quasi-normally-off" MESFET's are utilized, i.e., transistors operating as enhancement-mode devices but having a pinch-off voltage indifferently positive or negative (-0.3 to +0.2 V typically). As well as the genuine normally-off logic, quasi-normally-off digital IC's require a single power supply with a small voltage value (about +3 V). Six alternative circuit configurations, which exhibit different complexity-performance tradeoffs, have been studied by computer simulation. Furthermore, file performance capability of this logic was experimentally tested on 11-stage ring-oscillator circuits fabricated with 1 × 35 µm gate MESFET's. Minimum propagation delays in the range 95-135 ps (depending on the logic gate configuration) and speed-power products of 200-250 fJ (atV_{DD} = 2.5V) were achieved. From these results, propagation times in the range 100-200 ps and figures of merit of 50-200 fJ can be expected for logic gates with 10-20-µm FET geometry and LSI-circuit fan-in/loading conditions.     

Sound design of low power nested transconductance-capacitancecompensation amplifiers

An amplifier design approach is presented which is based on an all region MOS transistor model. Low power analogue circuits are designed using the presented approach. For illustrative purposes a nested transconductance-capacitance compensated (NGCC) operational amplifier is designed. Verification was carried out using a CMOS chip prototype which yields an op-amp with 105 dB gain, a 1.05 MHz gain-bandwidth product, 0.28 mW power consumption and 0.137 mm² active area for a 2 V supply voltage and 10 kΩ/20pF load     

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns     

Low-power video encoder/decoder chip set for digital VCRs

This paper describes the realization of a video encoder/decoder chip set for the consumer use digital video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 digital component video signal into the standard-definition digital VCR (DV) format or decode the DV format signal into a component video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-μm 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-μm CMOS technology, contains about 500 k transistors on 71 mm² and 79 mm² die, respectively     

A 6-GHz Low-Power BiCMOS SiGe:C 0.25 μ m Direct Digital Synthesizer

A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This letter discusses the BiCMOS design improvements used for the phase accumulator and the phase-to-amplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-level BiCMOS logic, and the phase-to-amplitude conversion is completed through a bipolar differential pair. The circuit has been processed in a BiCMOS SiGe:C 0.25 mum technology. The power consumption is 308 mW and it operates from a 2.8 V supply. The chip core area is 1 mm².     

A new low-power GaAs two-single-port memory cell

This paper describes an experimental static memory cell in GaAs MESFET technology. The memory cell has been implemented using a mix of several techniques already published in order to overcome some of their principal drawbacks related to ground shifting, destructive readout, and leakage current effects. The cell size is 36×37 μm² using a 0.6-μm technology. An experimental 32 word × 32 bit array has been designed. From simulation results, an address access time of 1 ns has been obtained. A small 8 word×4 bit protoype was fabricated. The cell can be operated at the single supply voltage from 1 up to 2 V. The evaluation is provided according to the functionality and power dissipation. Measured results show a total current consumption of 14 μA/cell when operated at 1 V     

High performance monolithic GaAlAs/GaAs photodiode arrays for voltage-controlled semiconductor switches

Monolithic GaAlAs/GaAs photodiode arrays (PDA's) have been developed as control elements for voltage-controlled switching applications. A p-type GaAs absorbing layer and an n-type GaAlAs window layer were grown by LPE on a semi-insulating GaAs substrate. Individual photodiodes were isolated and were series connected by an overlay metallization. A six cell PDA, having an active area of 1.28 mm², produces an open-circuit voltage of 5.3 V and a short-circuit current of 33 µA when subjected to a normally incident power flux of 50 mW/cm²at 865 nm. Such devices may be useful in a variety of voltage-controlled switching applications, opto-isolator circuits, and wherever low power, floating, voltage/bias sources are required.     

A 3.5 V, 1.3 W GaAs power multi-chip IC for cellular phones

A GaAs power multi-chip IC (MCIC) operable at a voltage of 3.5 V designed for cellular phones has been developed. The MCIC is able to deliver an output power of 1.3 W with a power-added efficiency of 60% in a frequency range from 890 to 950 MHz. This consists of two GaAs MESFET's, three GaAs passive matching chips, and a printed circuit board on which biasing networks are disposed. These are mounted on an aluminum nitride (AlN) package, occupying a half volume of conventional power hybrid IC's, i.e., only 0.4 cc. In order to improve the low voltage operation characteristics, a GaAs power MESFET operable at a low voltage of 3.5 V with an output power of 32 dBm and a power-added efficiency of 65% is developed, and microstrip lines having high impedance characteristics are incorporated also in order to minimize the conductor loss of matching network. The MCIC would be highly useful to develop compact cellular phones with advanced characteristics