板级设计中硬件连接部分的验证方法探讨

基于板极设计高速化,复杂化的发展趋势,缩短设计进入市场时间的方法无疑成为各个设计公司的焦点。现有的EDA工具可以帮助工程师在确定系统框架并完成原理图输入工作后进行电气规范规则等的检查来减少设计错误,但是EDA工具在硬件连接错误检查方面的功能有所欠缺。本文讨论了一种基于实用报表提取语言的数据库处理工具进行硬件连接检查的新方法的可行性以及优越性。     

用STATECAD快速设计有限状态机

有限状态机设计的关键是如何把一个实际的时序逻辑关系抽象成一个时序逻辑函数,传统的电路图输入法通过直接设计寄存器组来实现各个状态之间的转换,而用硬件描述语言来描述有限状态机,往往是通过充分发挥硬件描述语言的抽象建模能力,通过对系统在系统级或寄存器传输级进行描述来建立有限状态机。随着EDA工具的快速发展,通过CAD快速设计有限状态机自动化成为可能。     

基于压缩式改进迷宫算法的同构子电路提取

提出了一种用于集成电路逆向工程的高性能子电路识别算法。在搜索匹配过程中,采用改进的迷宫算法对电路中有效节点进行遍历,解决了实际电路中出现的缓冲器问题;采用压缩式存储方法,大大降低了算法的空间复杂度,可支持超大规模的集成电路。该算法将最终的结果以通用的EDIF文件格式输出,实现与Cadence等主流EDA工具无缝衔接。该算法已应用于实际工程项目中,可显著提高分析整理集成电路的工作效率。     

基于STM32的简易电路测试仪的设计

以高级语言描述、系统级仿真和综合技术为特征的第三代EDA工具为依托,以实现复杂电路内部故障原因的诊断为目的,提出了基于STM32单片机的简易电路测试仪。测试仪通过AD采集获得计算所需的电压数值,转换为电路参量后判断故障原因。主控板采用STM32F103ZET6,实现整个电路的控制。该测试仪可以对故障电路进行单一故障的诊断。应用了电压跟随器,使电路性能保持稳定。与人工检测相比,该设计具有灵活可控、可靠性高、智能诊断等优点。     

基于EDA技术的数字系统设计

EDA是现代电子数字系统设计的核心技术,其基于电子芯片设计自动化特征,可实现电路数字逻辑系统设计,简化电路硬件设计的结构,提高数字系统可靠性和灵活性。对EDA技术的特征进行分析,介绍EDA设计工具及技术要点,以基于EDA技术的数字系统实例分析为基础介绍EDA技术在数字系统设计中的具体应用,证明EDA技术在电子设计和数字逻辑系统设计中的实用性。     

数字电子钟的EDA实现详例

在QuartusII软件平台上结合我校自行研制的EDA课程设计实验板,完成了数字电子钟芯片的设计和硬件实现。侧重于逻辑电路的设计同时采用VHDL硬件描述语言辅助完成对电路的功能仿真。在设计过程中,重点探讨了数字电子钟的设计思路和功能模块划分,对设计过程中出现的问题详细进行分析。     

一种解同步电路优化设计方法的研究和实现

解同步电路设计方法可以与现有EDA工具较好地兼容,可以极大地提高异步电路的设计效率.基于解同步电路的抽象模型--控制图,提出了一种解同步电路优化设计方法,优化过程由解同步电路的性能评价函数作为指导,在不影响电路性能的前提下有效地减小电路控制通路的面积.选取了一系列标准测试电路进行了实验,最终解同步电路控制通路所需的局部控制器数量减少了54%,C门的数量减少了76.3%.采用该设计方法,设计实现了0.35μm工艺条件下的32位解同步乘法器,实验结果表明,相对于传统的解同步电路设计方法,提出的优化设计方法可以在保持电路性能的前提下有效地减小电路的面积.     

General decomposition of incompletely specified sequential machines with multi-state behavior realization

This paper is devoted to decomposition of sequential machines, discrete functions and relations. Sequential machine decomposition consists in representation of a given machine as a network of collaborating partial machines that together realize behavior of the given machine. A good understanding of possible decomposition structures and of conditions under which the corresponding structures exist is a prerequisite for any adequate circuit or system synthesis. The paper discusses the theory of general decomposition of incompletely specified sequential machines with multi-state behavior realization. The central point of this theory is a constructive theorem on the existence of the general decomposition structures and conditions under which the corresponding structures exist. The theory of general decomposition presented in this paper is the most general known theory of the binary, multi-valued and symbolic sequential and combinational discrete network structures. The correct circuit generator defined by the general decomposition theorem covers all other known structural models of sequential and combinational circuits as its special cases. Using this theory, in recent years we developed a number of effective and efficient methods and EDA tools for sequential and combinational circuit synthesis that consistently construct much better circuits than other academic and commercial state-of-the-art synthesis tools. This demonstrates the practical soundness of our theory. This theory can be applied to any sort of binary, multi-valued and symbolic systems expressed as networks of relations, functions or sequential machines, and can be very useful in such fields as circuit and architecture synthesis of VLSI systems, knowledge engineering, machine learning, neural network training, pattern analysis, etc.     

Guaranteeing good memory bounds for parallel programs

The amount of memory required by a parallel program may be spectacularly larger than the memory required by an equivalent sequential program, particularly for programs that use recursion extensively. Since most parallel programs are nondeterministic in behavior, even when computing a deterministic result, parallel memory requirements may vary from run to run, even with the same data. Hence, parallel memory requirements may be both large (relative to memory requirements of an equivalent sequential program) and unpredictable. Assume that each parallel program has an underlying sequential execution order that may be used as a basis for predicting parallel memory requirements. We propose a simple restriction that is sufficient to ensure that any program that will run in n units of memory sequentially can run in mn units of memory on m processors, using a scheduling algorithm that is always within a factor of two of being optimal with respect to time. Any program can be transformed into one that satisfies the restriction, but some potential parallelism may be lost in the transformation. Alternatively, it is possible to define a parallel programming language in which only programs satisfying the restriction can be written     

量子线路模拟器QuEST在多GPU平台上的性能优化

在当前量子计算的研究中,量子线路模拟器作为重要的研究工具,一直受到研究者们的高度重视.QuEST是一款开源的通用量子线路模拟器,能在单个CPU结点、多个CPU结点和单个GPU等多种测试平台上灵活运行.量子线路模拟固有的并行性使其非常适合在GPU上运行,并能获得较大的性能加速.但是其缺点在于所消耗的内存空间巨大,单个GP...     

T型路口全感应交通控制器的设计

伴随着集成电路(IC)技术的发展,电子设计自动化(EDA)逐渐成为重要的设计手段,已经广泛应用于模拟与数字电路系统等许多领域。利用EDA工具可以在电子设计的各个阶段、各个层次进行计算机模拟仿真,保证设计工程的正确性,可以大大降低设计成本,缩短设计周期。交通灯控制系统可以实现交叉路口的红、绿灯自动控制,基于FPGA的交通控制系统具有电路简单、实时快速擦写、运算速度快、故障率低、可靠性高,而且体积小等特点。系统通过功能扩展、接口扩展可同时控制多个路口的红绿灯变换,可根据需要实现实时、快速擦写应用程序。设计采用了VHDL的结构描述风格,依据功能将系统分为控制模块、计数模块、显示模块、译码等模块,仿真结果表明控制系统自动实现了灯色的交替和转换,以及倒计时显示。     

基于VHDL的交通信号灯设计与实现

EDA技术综合了现代电子技术和计算机技术的最新研究成果,其设计采用自顶向下的设计方法,通常采用硬件描述语言进行电子电路设计;VHDL语言以其强大的建模和逻辑综合功能成为EDA技术中应用最广泛的硬件描述语言之一。基于VHDL设计了交通信号灯。     

一种基于组的时序驱动布局规划方法

本文提出了一种基于组的时序驱动布局规划方法,它利用现有的EDA工具将网表划分为组,并充分利用设计师的体系结构经验进行布局、调整和优化。该方法能在设计早期获取较为准确的线负载模型,提高前端与后端的一致性,并且可以以组为单位规划电源和地的布局,提高布通率。该方法在已研制成功的32位嵌入式微处理器Estar的物理设计中得到实际应用。结果表明,该方法能够有效地改善关键路径时序和加快设计进程。     

Data memory organization and optimizations in application-specificsystems

In application-specific designs, customized memory organization expands the search space for cost-optimized solutions. Several optimization strategies can be applied to embedded systems with several different memory architectures: data cache, scratch-pad memory, custom memory architectures, and dynamic random-access memory (DRAM)