A high-voltage, high-temperature reverse conducting thyristor

This paper describes the structure and electrical characteristics of a silicon p-n-p-n inverter switch which has been fabricated to demonstrate the feasibility of obtaining both high-voltage and high-temperature capability in the same device while still maintaining reasonable dynamic properties. It was realized that in most inverter systems, feedback rectifiers are required, and thus the reverse blocking capability of a thyristor is not utilized. This was used to advantage in the design of a thyristor by integrating an anti-parallel rectifier into a conventional thyristor structure. Although this approach results in a thyristor having a negligible reverse blocking capability in comparison to commercially available power thyrisitors, the potential advantages of lower conduction losses, high maximum junction temperatures, and integrated antiparallel rectifier may be attractive for use in inverters. Reverse conducting thyristors designed in this fashion have been operated with reasonable turnoff times at a forward blocking voltage of 1000 volts while at case temperatures of up to 230°C.     

CVD-based tungsten carbide schottky contacts to 6H-SiC for very high-temperature operation

In this study, tungsten carbide, with its hardness, chemical inertness, thermal stability and low resistivity (25 μΩ cm)¹ is shown as a reliable contact material to n- and p-type 6H-SiC for very high temperature applications. WC films with thicknesses of 100–150 nm were deposited by chemical vapor deposition (CVD) from a WF₆/C₃H₈/H₂ mixture at 1173 K. A method to pattern CVD-tungsten carbide is suggested. TEM analysis of as deposited samples displayed a clear and unreacted interface. The electrical investigations of the p-type 6H-SiC Schottky contacts revealed a high rectification ratio and a low reverse current density (6.1 × 10⁻⁵ A cm⁻², −10 V) up to 773 K. On n-type, a low barrier (Φ_Bn=0.79 eV) at room temperature was observed. The low Φ_Bn value suggests WC to be promising as an ohmic contact material on highly doped n-type epi-layers. We will show a temperature dependence for the barrier height of tungsten carbide contacts that can be related to the simultaneous change in the energy bandgap, which should be considered when designing SiC devices intended for high temperature operation.     

Degradation behaviors of GaN light-emitting diodes under high-temperature and high-current stressing

A number of commercially available multiple-quantum well (MQW) InGaN/GaN blue LEDs with wavelengths of about 460 nm and a power of 1 mW were stressed at temperatures ranging from 25 to 120 °C at several accelerated DC currents. Both the forward and reverse current voltage characteristics as well as the electroluminescent spectra of the LEDs were monitored. These effects also resulted in the pronounced degradation of light efficiency and device operation lifetime. We found that the degradation of photonic characteristics, correlated very well with the generation-recombination current which is governed by the defect density. The device degradation is much faster at high temperatures. At nominal operation current and at room temperature, the light intensity degradation reaches a saturation level before the light dyes out. These results shed new lights upon the design and lifetime specifications for the emerging commercial solid-state lighting devices.     

A 475-V high-voltage 6H-SiC lateral MOSFET

High-voltage lateral MOSFET's on 6H- and 4H-SiC have been fabricated with 400-475 V breakdown voltage using the RESURF principle. An MOS electron inversion layer mobility of about 50 cm²/V-s is obtained on 6H-SiC wafers. This mobility is high enough such that the specific on-resistance of the 6H-SiC MOSFET's (~0.29-0.77 Ω-cm²) is limited by the resistance of the drift layer, as desired. However, the implanted drift layer resistance is about ten times higher than expected for the implant dose used. Design and process changes are described to decrease the on-resistance and increase the breakdown voltage. For 4H-SiC, extremely low mobility was obtained, which prevents satisfactory device operation     

6H-SiC MOS场效应晶体管的研制

报道了多晶硅栅 6 H- Si C MOS场效应器件的制造工艺和器件性能。 6 H- Si C氧化层的SIMS分析说明在氧化过程中 ,多余的 C以 CO的形式释放 ,铝元素逸出极少 ,氧化层中因有较多的铝而正电荷密度较大 ,Si C的氧化速率和掺杂类型关系不大。器件漏电流都有很好的饱和特性 ,最大跨导为 0 .36 m S/ mm ,沟道电子迁移率约为 14cm2 / V.s,但串联电阻效应明显。     

Electron Mobility in Bulk n-Doped SiC-Polytypes 3C-SiC, 4H-SiC,and 6H-SiC: A Comparison

Semiconductors - This communication presents a comparative study on the charge transport (in transient and steady state) in bulk n-type doped SiC-polytypes: 3C-SiC, 4H-SiC and 6H-SiC. The time...     

A double-gate-type static-induction thyristor

A double-gate-type static-induction thyristor (DG-SIThy) with a high blocking voltage and a high current rating has been fabricated. In this paper, a basic operational mechanism, a fabrication procedure, and the electrical characteristics of the DG-SIThy are described. In the DG-SIThy, both electron injection and hole injection are controlled by signals applied to two gale regions so that the DG-SIThy is capable of higher frequency operations than a single-gate SIThy. In the DG-SIThy, described here, both a cathode and a gate (first gate) regions have been fabricated on one side of a semiconductor wafer and both an anode and gate.(second gate) regions on another side. For realizing the DG-SIThy with a high blocking voltage and a high current rating, we have tried attentively to form a p-n junction on one side of the wafer without influencing the p-n junction on the other side, and have developed a new counter-doping technique for epitaxial growth and an improved package structure for a compression-mounted device. The DG-SIThy fabricated with these techniques has shown a for-Ward blocking voltage of 1000 V, an average current rating of 100 A, and a forward voltage drop of 1.44 V at the rated anode current. A turn-on time of 0.95 its and a turn-off time of 0.48 µs have been observed at the rated anode current and at anode voltages of 650 and 550 V, respectively. As already speculated, the DG-SIThy shows a higher switching speed and a lower forward drop than the single-gate SIThy.     

A novel 6H-SiC power DMOSFET with implanted p-well spacer

In this letter, we utilize a lower thermal budget with an aluminum doped p-well to minimize the effect of “step bunching” and a new structural design with deep spacer implants to prevent the JFET “pinching” action at small p-well spacings (5 μm) in planar vertical double implanted MOSFET (DIMOS) devices fabricated on 6H-SiC. A specific ON-resistance of 42 mΩ-cm² (further reducible by 35% through simple design modification), which represents a 100% reduction over devices which did not receive the spacer implants, is observed on the 2-μm channel devices. This novel scheme will allow increased packing densities for high power applications using the DIMOS structure in SiC     

钒掺杂形成半绝缘6H-SiC的补偿机理

研究了钒掺杂生长半绝缘6H-SiC的补偿机理.二次离子质谱分析结果表明,非故意掺杂生长的6H-SiC中,氮是主要的剩余浅施主杂质.通过较深的钒受主能级对氮施主的补偿作用,得到了具有半绝缘特性的SiC材料.借助电子顺磁共振和吸收光谱分析,发现SiC中同时存在中性钒(V4+)和受主态钒(V3+)的电荷态,表明掺入的部分杂质钒通过补偿浅施主杂质氮,形成受主态钒,这与二次离子质谱分析结果相吻合.通过对样品进行吸收光谱和低温光致发光测量,发现钒受主能级在6H-SiC中位于导带下0.62eV处.     

6H-SiC肖特基二极管的特性研究

采用缓慢氧化-稀释的HF刻蚀-沸水浸泡法(BW法)处理SiC表面,以减少其界面态。首次在100°C以下制备了6H-SiC肖特基二极管,其欧姆接触比接触电阻ρc=5～7×10-3Ω.cm2,理想因子n=1.20～1.25。同时,还制备了P型6H-SiC肖特基二极管,其欧姆接触采用950°C高温合金Al/SiC工艺获得,该样品衬底较大的串联电阻导致其正向压降偏高,理想因子较大。实验表明,BW法不仅能降低合金温度和工艺难度,而且能有效改善器件的电学特性。     

6H-SiC高压肖特基势垒二极管

在可商业获得的N型6H-SiC晶片上,通过化学气相淀积,进行同质外延生长,在此结构材料上,通过热蒸发,制作Ni/6H-SiC肖特基势垒二极管．测量并分析了肖特基二极管的电学特性,结果表明,肖特基二极管具有较好的整流特性：反向击穿电压约为450V,室温下,反向电压VR=-200V时,反向漏电流JL=5×10-4A*cm-2;理想因子为1.09,肖特基势垒高度为1.24—1.26eV,开启电压约为0.8V．     

钒掺杂形成半绝缘6H-SiC的补偿机理

研究了钒掺杂生长半绝缘6H-SiC的补偿机理.二次离子质谱分析结果表明,非故意掺杂生长的6H-SiC中,氮是主要的剩余浅施主杂质.通过较深的钒受主能级对氮施主的补偿作用,得到了具有半绝缘特性的SiC材料.借助电子顺磁共振和吸收光谱分析,发现SiC中同时存在中性钒(V4 )和受主态钒(V3 )的电荷态,表明掺入的部分杂质钒通过补偿浅施主杂质氮,形成受主态钒,这与二次离子质谱分析结果相吻合.通过对样品进行吸收光谱和低温光致发光测量,发现钒受主能级在6H-SiC中位于导带下0.62eV处.     

6H-SiC高压肖特基势垒二极管

在可商业获得的 N型 6 H - Si C晶片上 ,通过化学气相淀积 ,进行同质外延生长 ,在此结构材料上 ,通过热蒸发 ,制作 Ni/6 H- Si C肖特基势垒二极管 .测量并分析了肖特基二极管的电学特性 ,结果表明 ,肖特基二极管具有较好的整流特性 :反向击穿电压约为 45 0 V,室温下 ,反向电压 VR=- 2 0 0 V时 ,反向漏电流 JL=5× 10 - 4 A· cm- 2 ;理想因子为 1.0 9,肖特基势垒高度为 1.2 4— 1.2 6 e V ,开启电压约为 0 .8V     

Al掺杂6H-SiC铁磁性研究(英文)

使用物理气象沉积法生长了轻Al掺杂6H-SiC样品,并使用超导量子干涉磁强计(SQUID)对无腐蚀及腐蚀后的样品进行了测试,发现了腐蚀后的样品在室温下表现出铁磁性。经过计算,样品磁信号并非来源于腐蚀剂KOH及K2CO3。同时腐蚀后的样品形貌表明杂质聚集在腐蚀后的缺陷附近从而形成了一定的铁磁性,因此缺陷被腐蚀放大是样品形成铁磁性的主要原因。     

Hydrogen passivation in n- and p-type 6H-SiC

Hydrogen passivation effects are found to be much more prevalent in p-type 6H-SiC relative to n-type material. Reactivation of passivated B acceptors occurs at ~700°C, corresponding to a reactivation energy of ~3.3 eV. This is much higher than for passivated acceptors in Si, where reactivation occurs at ≤200°C. The incorporation depth of ²H from a plasma at 200°C is ≤0.1 μm in 30 min, corresponding to a diffusivity approximately two orders of magnitude lower than in Si at the same temperature. The average energy of ions in the ²H plasma has an influence on the peak concentration of incorporated deuterium and on its diffusion depth.     

电子和中子辐照n型6H-SiC的光致发光谱

对用电子能量为1.7, 0.5和0.4MeV的电子辐照和中子辐照后的n型6H-SiC样品进行低温光致发光研究. 对于Ee≥0.5MeV电子辐照和中子辐照后的样品,首次发现了位于478.6/483.3/486.1nm的S1/S2/S3谱线.对样品进行热退火研究表明S1/S2/S3谱线在500℃下消失,而退火温度高于700℃时D1中心出现.考虑到产生C空位和Si空位所需的位移阈能以及热退火行为,说明S1/S2/S3为初级Si空位初级缺陷,而D1中心为二次缺陷.     

一种新型的6H-SiC MOS器件栅介质制备工艺

采用干 O2 +CHCCl3(TCE)氧化并进干 /湿 NO退火工艺生长 6H-Si C MOS器件栅介质 ,研究了 Si O2 /Si C界面特性。结果表明 ,NO退火进一步降低了 Si O2 /Si C的界面态密度和边界陷阱密度 ,减小了高场应力下平带电压漂移 ,增强了器件可靠性 ,尤其是湿 NO退火的效果更为明显。     

半绝缘6H-SiC单晶的生长

用升华法生长出了电阻率高达1010Ω·cm的半绝缘6H-SiC体块晶体.用二次离子质谱(secondary ion mass spectrometry,SIMS)、辉光放电质谱(glow discharge mass spectroscopy,GDMS)测量了晶体和原料中的杂质浓度,包括硼、铝、钒.结果表明,钒的浓度会影响生长晶体的质量.分别用Pt和In做电极测试样品电阻率特性,发现不同的电极对测试结果有较大影响.     

A new lateral MOS-controlled thyristor

A lateral MOS-controlled thyristor (LMCT) structure that uses an MOS gate to turn it both on and off is presented. The device structure offers improved maximum turn-off current capability and forward voltage drop. The former is achieved by using a DMOS transistor and a parasitic vertical p-n-p transistor, while the latter is achieved by eliminating a parasitic lateral p-n-p transistor in the conventional structure. The device utilizes the resurf technique to achieve high area efficiency, breakdown voltage, and reliability. Devices that have more than 250-V forward blocking capability were fabricated in dielectrically isolated silicon tubs using the standard bipolar-CMOS-DMOS process     

6H-SiC Schottky二极管的正向特性

提出了一种考虑Schottky结势垒不均匀性和界面层作用的SiC Schottky二极管(SBD)正向特性模型,势垒的不均匀性来自于SiC外延层上的各种缺陷,而界面层上的压降会使正向Schottky结的有效势垒增高.该模型能够对不同温度下SiC Schottky结正向特性很好地进行模拟,模拟结果和测量数据相符.它更适用于考虑器件温度变化的场合,从机理上说明了理想因子、有效势垒和温度的关系.