A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF–DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF–dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF–dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-$muhbox{m}$ 2P4M CMOS technology. The whole chip occupies a die area of $490 times 780 mu hbox{m}^{2}$ and consumes only 2.1 $muhbox{W}$ in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a $-$14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.      

A 0.18-$muhbox{m}$ CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

A fully integrated 2-MHz Gaussian frequency-shift keying (GFSK) analog front end for low-IF receivers is presented. The analog GFSK demodulation uses a Bessel-based quadrature discriminator and a differentiator-based data decision circuit, eliminating the need for analog–digital converters while enabling high sensitivity and large frequency offset tolerance. The analog front end consists of a fifth-order Butterworth low-pass prefilter, a seven-stage limiter, a quadrature discriminator with a fourth-order Bessel phase-shift network, a fourth-order Butterworth low-pass postfilter, and a differentiator-based data decision circuit. The prefilter, Bessel phase shifter, postfilter, and differentiator are built using identical $Gm{-}C$ cells and tuned across process variations with a single master–slave phase-locked loop. The GFSK analog front end is implemented in a 1.8-V 0.18-${rm mu}hbox{m}$ CMOS process, recovering 1-Mb/s input data from a 2-MHz GFSK signal with maximum frequency deviation of $pm$160-kHz, frequency offset tolerance from $-$ 38% to $+$ 47%, and input sensitivity of $-$53 dBm and consuming 7 mA of current.      

Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional- $N$ PLLs

This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma $(Delta Sigma)$ fractional-$N$ PLL. The proposed CP circuit achieves good up/down current matching, while the proposed linearization method enables the PFD/CP system to operate at an improved linear region. The proposed techniques are demonstrated in the design of a 2.4-GHz $Delta Sigma$ fractional-$N$ PLL. The experimental results show these techniques considerably improve the in-band phase noise and fractional spurs. In addition, the proposed gated-offset CP topology further lowers the reference spurs by more than 8 dB over the conventional fixed-offset approach. This chip is implemented in the TSMC 0.18- $mu$m CMOS process. The fully-integrated $Delta Sigma$ fractional-$N$ PLL dissipates 22 mW from a 1.8-V supply voltage.      

A 60 kb/s–10 Mb/s Adaptive Frequency Hopping Transceiver for Interference-Resilient Body Channel Communication

An interference-resilient 60 kb/s–10 Mb/s body channel transceiver using the human body as a signal transmission medium is designed for multimedia and medical data transaction in body-area network. The body antenna effect which interferes with signals in the human body channel is examined. The body-induced interferences degrade the SIR of the signal to $-$22 dB in the worst case. In order to overcome the body antenna effect, a 4-channel adaptive frequency hopping scheme using the 30–120 MHz band is introduced to the body channel transceiver. A direct-switching modulator using dual frequency synthesizers and a DLL-based demodulator are proposed for 10 Mb/s FSK and the 4.2 $mu hbox{s}$ hopping time. The transceiver fabricated with 0.18 $mu hbox{m}$ CMOS withstands $-$28 dB SIR and its operating distance is over 1.8 m with $-$ 25 dB SIR. Its energy consumption is 0.37 nJ/b with $-$65 dBm sensitivity.      

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

Equivalent Circuit Model for the Gate Leakage Current in Broken Down $hbox{HfO}_{2}/hbox{TaN/TiN}$ Gate Stacks

We propose an equivalent circuit model for the post-breakdown (BD) current–voltage ( $I$–$V$) characteristics in $hbox{HfO}_{2}/hbox{TaN/TiN}$ gate stacks in n-MOSFETs. The model consists of two opposite-biased diodes with series resistances and a shunt leakage path. The circuit admits analytical solution using the Lambert $W$-function and is tested for both negative and positive gate biases in the voltage range of $-$1.5 to $+$1.5 V. We also show the versatility of the proposed approach to deal with the post-BD $I$– $V$ when source and drain contacts are grounded or floating and analyze the obtained results in terms of the charge available for conduction.      

Fast Characterization of Threshold Voltage Fluctuation in MOS Devices

Random microscopic fluctuations in the number and location of dopant atoms can cause a large variation in the threshold voltage $(V _{T})$ of a MOS device. In this paper, we present a technique for fast characterization of random threshold voltage mismatch in MOS devices. Our $V _{T}$ scatter characterization method measures threshold voltage shift by monitoring the change in gate-to-source voltage $V _{GS}$ for a fixed drain current $I _{DS}$ and drain-to-source voltage $V _{DS}$ . We present circuit schematics to characterize $V _{T}$ scatter by measuring $V _{GS}$ variation for a large set of devices arranged in an individually addressable array. We report experimental results of $V _{T}$ scatter measurement from test chips fabricated in 65-nm silicon-on-insulator and 65-nm bulk CMOS processes. We also measure and report the magnitude of local device current mismatch caused by $V _{T}$ fluctuation.      

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3$sigma $) over the temperature range from $-{hbox{22}},^{circ}{hbox{C}}$ to 85$,^{circ}{hbox{C}}$ . Fabricated in a baseline 65$~$nm CMOS technology, the frequency reference circuit occupies 0.11$ hbox{mm}^{2}$ and draws 34 $ muhbox{A}$ from a 1.2 V supply at room temperature.      

A Long-Range UHF-Band Passive RFID Tag IC Based on High- $Q$ Design Approach

We present a fully integrated long-range UHF-band passive radio-frequency-identification tag chip fabricated in 0.35-$muhbox{m}$ CMOS using titanium (Ti/Al/Ta/Al)–silicon Schottky diodes. The diodes showed low turn-on voltages of 95 and 140 mV for diode currents of 1 and 5 $muhbox{A}$, respectively. In addition, the Schottky diodes exhibited low-resistive loss, and a high-$Q$ -factor design approach was exploited to achieve a long read range for the tag integrated circuit (IC). An optimized voltage multiplier resulted in an excellent sensitivity of $-$ 14.8 dBm and corresponding power-conversion efficiency of 36.2% for generating an output voltage of 1.5 V at 900 MHz. The range analysis of the measured multiplier performance indicated an operating range of more than 9 m at 4-W Effective Isotropically Radiated Power reader power. The subthreshold-mode operation of an ASK demodulator allowed ultralow power operation. Under power consumption as low as 27 nW, the demodulator supported a data rate of 150 kb/s and a modulation depth of 40%. A new architecture for generating a stable system clock (2.2 MHz) for the tag IC was employed to deal with supply voltage and temperature variations. Measurements showed that the clock generator had an error of 0.91% from the center frequency owing to an 8-b digital calibration scheme.      

A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology

A 10-Gb/s low-power analog equalizer for a 10-m coaxial cable has been realized in 0.13- $muhbox{m}$ CMOS technology. To compensate the cable loss of 20 dB at 5 GHz, this equalizer with an interleaved active feedback topology is proposed without using inductors. Moreover, additional capacitive and resistive source degenerations are incorporated to meet low-frequency losses. This circuit consumes only 14 mW (excluding the output buffer) from a 1.2-V supply with the output swing up to 400 $hbox{mV}_{rm pp}$, and it occupies $0.38 times 0.34 hbox{mm}^{2}$. For 8-, 9-, and 10-Gb/s pseudorandom binary sequences (PRBSs) of $2^{31} - 1$, the measured maximum peak-to-peak jitters are 26, 34, and 40 ps, respectively, and the measured bit error rate (BER) is less than $10^{-12}$.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active- ${rm G}_{rm m}{-}{rm RC}$ biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The $-$ 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The $-$3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 $mu{rm m}$ CMOS technology with ${V}_{THN}approx 0.25 {rm V}$ and ${V}_{THP}approx 0.3 {rm V}$, the filter operates with a supply voltage as low as 0.55 V. The filter $({rm total} {rm area}=0.47 {rm mm}^{2})$ consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.      

A 1.8 V 900 $mu$ W 4.5 GHz VCO and Prescaler in 0.18 $mu$m CMOS Using Charge-Recycling Technique

This letter presents a charge-recycling VCO and divider in 0.18 $mu$m CMOS technology. The power consumption of the proposed circuit is significantly reduced by stacking the low-voltage divider on the top of the low-voltage VCO, and hence, the VCO reuses the current from the divider. To enhance the reliability of the proposed circuit under supply voltage variation, transistor sharing and adaptive body-biasing techniques are employed. It allows the proposed circuit to operate down to 1.45 V of supply voltage without degrading the FoM. Experimental results show that the proposed circuit achieves 900 $mu$W of power consumption and ${-}184$ dBc/Hz of FoM at 1.8 V.      

A V-Band CMOS VCO With an Admittance-Transforming Cross-Coupled Pair

A novel circuit topology suitable for the implementation of CMOS voltage-controlled oscillators (VCOs) at millimeter-wave frequencies is presented in this paper. By employing transmission line segments to transform the admittance of the additional cross-coupled pair, the proposed LC-tank VCO can sustain fundamental oscillation at a frequency close to the $f _{max}$ of the transistors. Using a standard 0.18 $muhbox{m}$ CMOS process, a V-band VCO is realized for demonstration. The fabricated circuit exhibits a frequency tuning range of 670 MHz in the vicinity of 63 GHz. The measured output power and phase noise at 1 MHz offset are $-hbox{15~dBm}$ and $-hbox{89~dBc}/hbox{Hz}$ , respectively. Operated at a 1.8 $~$V supply voltage, the VCO core and the output buffer consume a total DC current of 55 mA.      

A Low Voltage Quadrature VCO Implemented With Series Frequency Doublers

Using the transformer coupling technique, this letter presents a new quadrature voltage-controlled oscillator (QVCO) with bottom series-coupled transistors. The proposed CMOS QVCO has been implemented with the TSMC $0.13~mu{rm m}$ 1P8M CMOS process, and the die area is $1.03 times 0.914~{rm mm}^{2}$. At the supply voltage of 1.0 V, the total power consumption is 3.56 mW. The free-running frequency of the QVCO is tunable from 5.43 GHz to 5.92 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz frequency offset is $-117.98~{rm dBc/Hz}$ at the oscillation frequency of 5.5 GHz and the figure of merit (FOM) of the proposed QVCO is $-187.27~{rm dBc/Hz}$.      

A Low Voltage and Low Power Bottom-Series Coupled Quadrature VCO

This letter presents a new low power quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) with split-source tail inductors. The bottom-series coupling transistors are in parallel with the tail inductors and require no dc voltage headroom. The proposed CMOS QVCO has been implemented with the TSMC 0.18 $mu{rm m}$ CMOS technology and the die area is $0.512times 1.065 {rm mm}^{2}$. At the supply voltage of 1.1 V, the total power consumption is 2.545 mW. The free-running frequency of the QVCO is tunable from 4.38 to 4.71 GHz as the tuning voltage is varied from 0.0 V to 0.6 V. The measured phase noise at 1 MHz frequency offset is $-$120.8 dBc/Hz at the oscillation frequency of 4.4 GHz and the figure of merit (FOM) of the proposed QVCO is $-$ 189.61 dBc/Hz.      

A 25-MHz Self-Referenced Solid-State Frequency Source Suitable for XO-Replacement

Recent trends in the development of integrated silicon frequency sources are discussed. Within that context, a 25-MHz self-referenced solid-state frequency source is presented and demonstrated where measured performance makes it suitable for replacement of crystal oscillators (XOs) in data interface applications. The frequency source is referenced to a frequency-trimmed and temperature-compensated 800-MHz free-running $LC$ oscillator (LCO) that is implemented in a standard logic CMOS process and with no specialized analog process options. Mechanisms giving rise to frequency drift in integrated LCOs are discussed and supported by analytical expressions. Design objectives and a compensation technique are presented where several implementation challenges are uncovered. Fabricated in a 0.25-$mu$m 1P5M CMOS process, and with no external components, the prototype frequency source dissipates 59.4 mW while maintaining ${pm} 152$ ppm frequency inaccuracy over process, ${pm} 10hbox{%}$ variation in the power supply voltage, and from ${-}$ 10 $^{circ}$ C to 80 $^{circ}$ C. Variation against other environmental factors is also presented. Nominal period jitter and power-on start-up latency are 2.75 ps$_{rm rms}$ and 268 $mu$s, respectively. These performance metrics are compared with an XO at the same frequency.      

Delta-Sigma Modulation for Direct Digital Frequency Synthesis

This paper compares different $DeltaSigma$ modulation techniques for direct digital frequency synthesis (DDS). $DeltaSigma$ modulators such as MASH, feedforward, feedback, and error feedback have been implemented in both the phase and frequency domains in a CMOS DDS prototype IC fabricated in a 0.35-$mu$m CMOS technology with core area of $1.7times 2.1 {hbox {mm}}^{2}$ and total current consumption of 75 mA. Measured DDS performance demonstrates that the frequency domain $DeltaSigma$ modulation technique achieves better output spectrum purity than the phase domain method. Moreover, a programmable feedforward $DeltaSigma$ modulator is proposed to achieve different in-band and out-band noise shaping effects for DDS applications.      

A Wideband PLL-Based G/FSK Transmitter in 0.18 $mu$m CMOS

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed Sigma-Delta modulated Phase Rotator $(SigmaDelta{hbox{-PR}})$. By properly combining the multi-phase signals from the PLL output, the $SigmaDelta{hbox{-PR}}$ effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed $SigmaDelta{hbox{-PR}}$ adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the $SigmaDelta{hbox{-PR}}$ on the TX output noise is also analyzed in this paper. The proposed TX with the $SigmaDelta{hbox{-PR}}$ is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 $muhbox{m}$ CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of $-$11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.      

Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor $alphaleq 1$ is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of $alpha$ on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of $alpha$ ($alpha=$ 0, 0.5, and 1) in a 0.5 $mu{hbox {m}}$ CMOS technology with $pm$1.65-V supply voltage. Experimental results show (for $alpha=1$ ) a THD of $-$ 57 dB $({rm HD}2=-70 {hbox {dB}})$ at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 $muhbox{A/V}$ and a power consumption of 3.2 mW.