Thermal characteristic of Cu-Cu bonding layer in 3-D integrated circuits stack

Copper (Cu) thermo-compression bonding of wafers can be used to fabricate multi-layer three-dimensional (3-D) integrated circuits (ICs). This work examines the thermal characteristic of the Cu bonding layer and demonstrates experimentally that Cu bonding layer can act as a spreading layer that helps in heat dissipation of bonded 3-D ICs stack more efficiently compared to silicon dioxide bonding layer. The use of Cu bonding layer in a double-layer stack of ICs provides better cooling by as much as 9 °C compared to oxide bonding interface.     

Bonding parameters of blanket copper wafer bonding

A reliable copper wafer bonding process condition, which provides strong bonding at low bonding temperature with a short bonding duration and does not affect the device structure, is desirable for future three-dimensional (3-D) integration applications. In this review paper, the effects of different process parameters on the quality of blanket copper wafer bonding are reviewed and summarized. An overall view of copper wafer bonding for different bonding parameters, including pressure, temperature, duration, clean techniques, and anneal option, can be established. To achieve excellent copper wafer bonding results, 400°C bonding for 30 min. followed by 30 min. nitrogen anneal or 350°C bonding for 30 min. followed by 60 min. anneal bonding is necessary. In addition, by meeting the process requirements of future integrated circuit (IC) processes, the best bonding condition for 3-D integration can be determined.     

Scaling trends of power noise in 3-D ICs

Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling.     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

Investigations of solution variables in a contactless copper electrodeposition process for 3D packaging applications

A novel electrochemical method for contactless electrodeposition of copper onto silicon wafers has been investigated. Deposition parameters such as applied current, concentrations of deposition solution and supporting electrolyte were optimized to achieve high deposition rates as well as homogenous deposition of copper. Copper sulfate solution temperature of about 65 °C was shown to be suitable for achieving stable and high values of current density that translated to copper deposition rates of~2.4 µm/min with good deposition uniformity.     

Thermosonic bonding of gold wire onto silver bonding layer on the bond pads of chips with copper interconnects

A copper pad oxidizes easily at elevated temperatures during thermosonic wire bonding for chips with copper interconnects. The bondability and bonding strength of a gold wire onto a bare copper pad are seriously degraded by the formation of a copper oxide film. A new bonding approach is proposed to overcome this intrinsic drawback of the copper pad. A silver layer is deposited as a bonding layer on the surface of copper pads. Both the ball-shear force and the wire-pull force of a gold wire bonded onto copper pads with silver bonding layers far exceed the minimum values stated in the JEDEC standard and MIL specifications. The silver bonding layer improves bonding between the gold ball and copper pads. The reliability of gold ball bonds on a bond pad is verified in a high-temperature storage (HTS) test. The bonding strength increases with the storage time and far exceeds that required by the relevant industrial codes. The superior bondability and high strength after the HTS test were interpreted with reference to the results of electron probe x-ray microanalyzer (EPMA) analysis. This use of a silver bonding layer may make the fabrication of copper chips simpler than by other protective schemes.     

The influence of ultrasonic agitation on copper electroplating of blind-vias for SOI three-dimensional integration

Three-dimensional (3D) integration, which employs through-silicon-vias (TSVs) to electrically interconnect multiple-stacked chips, is a promising technology for significant reduction in interconnect delay and for hetero-integration of different technologies. To fabricate void-free TSVs, this paper presents a copper electroplating technique with the assistance of ultrasonic agitation to fill blind-vias, and discusses the influence of ultrasonic agitation on copper electroplating. Blind-vias with an aspect ratio of 3:1 are used for copper electroplating with both direct current (DC) and pulse-reverse current modes, combined with either ultrasonic agitation or mechanical agitation. Experimental results show that blind-vias with small aspect ratio can be completely filled using pulse-reverse current, regardless of the agitation methods. For DC, ultrasonic agitation is superior to mechanical agitation for copper electroplating in filling void-free vias. These results indicate that agitation, though is a secondary control factor to pulse-reverse current, can enhance mass transfer in blind-vias during copper electroplating and can improve the filling capability of copper electroplating.     

成型工艺对高介单层微波陶瓷电容器性能的影响

分别采用轧膜与流延两种成型工艺制备了SrTiO3高介单层微波陶瓷电容器材料,对比研究了两种成型工艺对其结构与性能的影响。研究表明:对于轧膜工艺而言,电容器陶瓷材料的εr和密度随着轧膜次数增加呈单峰效应,瓷料脱辊后轧膜70次左右可获得表面平整、结构致密、介电性能良好的电容器陶瓷材料。和流延工艺相比,轧膜工艺制备的电容器陶瓷材料εr较大,电容量温度变化率较小。     

Influence of slurry components on uniformity in copper chemical mechanical planarization

Many researchers studying copper chemical mechanical planarization (CMP) have been focused on mechanisms of copper removal using various chemicals. On the basis of these previous works, we studied the effect of slurry components on uniformity. Chemical mechanical planarization of copper was performed using citric acid (C₆H₈O₇), hydrogen peroxide (H₂O₂), colloidal silica, and benzotriazole (BTA, C₆H₄N₃H) as a complexing agent, an oxidizer, an abrasive, and a corrosion inhibitor, respectively. As citric acid was added to copper CMP slurry (pH 4) containing 3 vol% hydrogen peroxide and 3 wt% colloidal silica, the material removal (MRR) at the wafer center was higher than its edge. Hydrogen peroxide could not induce a remarkable change in the profile of MRR. Colloidal silica, used as an abrasive in copper CMP slurry containing 0.01 M of citric acid and 3 vol% of hydrogen peroxide, controlled the profile of MRR by abrading the wafer edge. BTA as a corrosion inhibitor decreased the MRR and seems to control the material removal around the wafer center. All the results of in this study showed that the MRR profile of copper CMP could be controlled by the contents of slurry components.     

基于造影图像的冠状动脉三维定量分析的研究

由于X射线造影成像把血管三维空间结构投影到二维图像上,基于二维造影图像的传统诊治方法存在很大局限性.本文在冠状动脉树三维重建的基础上,研究了冠状动脉的三维定量分析方法,提出血管直径、分支夹角和血管段长度的三维测量方法.并利用冠状动脉树实物模型进行实验,对二维和三维定量分析结果进行了比较.实验结果表明,三维定量分析能够有效地提高临床医学参数的测量精度.因此,在冠心病的临床诊断和介入治疗中,该方法能够可靠地诊断血管狭窄及选择和放置支架.     

基于三维测量模型的立体视觉传感器的现场标定技术

提出了基于双目立体视觉传感器三维(3-D)测量模型的传感器现场标定技术，并建立了标定数学模型。相关实验表明，这种标定方法简单，具有较高的标定精度，最大尺寸测量误差小于0．05mm，对标定环境及靶标的摆放姿态无严格要求。     

Influence of oxygen on the parameters of a thin film copper phthalocyanine field effect transistor

The influence of oxygen on the electrical parameters of a copper phthalocyanine thin film field effect transistor was investigated by means of temperature‐modulated field effect spectroscopy. It was found that both the dark electrical conductivity and threshold voltage of the source–drain current versus gate voltage dependence were changed after oxygen exposure. Both effects can be effectively utilised for gas sensing. Copyright © 1999 John Wiley & Sons, Ltd.     

嘉陵江水体平水期水质的三维荧光光谱监测分析

嘉陵江是重庆的重要饮用水源,其水质与城市居 民的生活和生态环境息息相关。为研究其水质及其变化,在重庆主城区嘉陵江段平水期3~5月,采用三维荧光技术对7个取样点的水体样品进行 分析,得到了溶解性有机质(DOM)含量变化引起的三维荧光光谱变化数据,水体样品存在 两个荧光峰分 布,荧光峰Ⅰ激发波长λ_ex=330~350nm,发射波长λ_em=400~450nm;荧光峰Ⅱ激发波长 E_ex=270~300nm, 发射波长λ_em=320~350nm。结果 表明,取样江段水样三维荧光谱中的荧光峰主要由类腐殖 质和类蛋白质形成;同时,由于受到气温、降雨、地理环境等因素的影响,3-5月各河段水 样的荧光指数(f450/50)分别 在1.41~1.57、1.30~1.47和1.42~1.68之间,由此可以判断,采样时 间段内水质污染主要是陆源性输入形成。     

The effect of sputtered W-based carbide diffusion barriers on the thermal stability and void formation in copper thin films

The W-based diffusion barriers W, WC and WCN barriers were investigated for Cu metallization. The thermal stability of the W, WC and WCN barriers was compared by X-ray diffraction and four point probe. It shows comparable stability for the W and WC barriers while the ternary WCN barrier has superior performance. The agglomeration of the Cu films (100 nm) on these barriers is quite different. The formation of voids was observed for the annealed copper film on the WC or WCN barriers and the activation energy values determined from Kissinger equation are low comparing with Cu on W barrier. Twins were also observed in the as-deposited and annealed Cu films on the WC and WCN barriers. The twin formation and its correlation with void formation for Cu films onto the C-containing diffusion barrier were discussed through the stress relaxation and stress-induced vacancy migration mechanism.     

金丝球焊复合键合工艺可靠性研究

对芯片铝焊盘上不同重叠面积的金丝球焊复合键合的可靠性进行研究,并与非复合键合进行对比.结果 表明,随着复合键合重叠面积的减少,键合拉力和界面生成的合金化合物面积均无明显变化,而剪切强度呈下降趋势.高温储存结果表明,复合键合拉力值满足国军标要求.复合键合有掉铝和弹坑缺陷隐患.经分析,原因是复合键合时施加的超声能量破坏了硅...     

The effect of oxygen content on the performance of low-voltage organic phototransistor memory

Optical writing and electrical erasing organic phototransistor memory (OPTM) is a promising photoelectric device for its novel integration of photosensitive and memory properties. The performance of OPTM can be influenced by the trap density of the gate dielectric layer. Here, we occupy tantalum pentoxide (Ta₂O₅), which is a prospective material in microelectronics field, as the gate dielectric. By increasing the oxygen content from 10% to 50% during the fabrication process of Ta₂O₅, it is found that the mobility and the photoresponsivity of OPTMs are significantly enhanced about 10 times and the retention time is greatly increased to 8.4 × 10⁴ s as well. As far as we know, this is the first example that the modulation of oxygen content can improve the OPTM performance. Furthermore, the change of the oxygen content gives rise to the alteration of the threshold voltage and memory window, of which the absolute values of all the threshold voltage are below 5 V which is low enough to reduce the power consumption. It is found that the oxygen content can influence the surface roughness and surface energy of Ta₂O₅ films, which alter the nucleation and orientation of semiconductor layers, change the contact resistance and modulate the electron trap density in the Ta₂O₅ films.     

MoO3修饰氧化石墨烯作为空穴注入层影响研究

研究了MoO₃修饰氧化石墨烯(GO)作为空穴注入层的影响。采用旋涂的方法制备了GO, 再真空蒸镀修饰层MoO₃,得到了空穴注入能力强和透过率高的复合薄膜。MoO₃的厚分 别采用0、3、5和8nm。通过优化MoO₃的厚度发现,当MoO₃的厚为5nm时,复合薄膜 的透过率达到最大值,在 550nm的光波长下透光率为88%,且此时采用 复合薄膜作为空穴注入层制备的结构为 ITO/GO/MoO₃(5nm)/NPB(40nm)/Alq₃(40nm)/LiF(1nm)/Al(100nm)的有机电致发光器件(OLED)性能 最佳。通过对OLED进一步的优化,改变Alq₃的厚度,分别取50、60和70nm,测量其电压 、电流、亮度、色坐标和电致发光(EL)光谱等参数发现,当Alq₃的厚为50nm时器件性能最 佳。最终制备了结构为ITO/GO/MoO₃(5nm)/NPB(50nm)/Alq₃(50nm)/LiF(1nm)/Al(100 nm)的OLED,在电压为10V时,最大电流效率达到5.87cd/A,与GO单独作为空穴注入层制备的器件相比,提高了50%。     

The effects of process conditions and substrate on copper MOCVD using liquid injection of (hfac)Cu(vtmos)

Copper MOCVD (metalorganic chemical vapor deposition) using liquid injection for effective delivery of the (hfac)Cu(vtmos) [1,1,1,5,5,5-hexafluoro-2,4-pentadionato(vinyltrimethoxysilane) copper(I)] precursor has been performed to clarify growth behavior of copper films onto TiN, <100> Si, and Si₃N₄ substrates. Especially, we have studied the influences of process conditions and the substrate on growth rates, impurities, microstructures, and electrical characteristics of copper films. As the reactor pressure was increased, the growth rate was governed by a pick-up rate of (hfac)Cu(vtmos) in the vaporizer. The apparent activation energy for copper growth over the surface-reaction controlled regime from 155°C to 225°C was in the range 12.7–32.5 kcal/mol depending upon the substrate type. It revealed that H₂ addition at 225°C substrate temperature brought about a maximum increase of about 25% in the growth rate compared to pure Ar as the carrier gas. At moderate deposition temperatures, the degree of a <111> preferred orientation for the deposit was higher on the sequence of <Cu/Si<Cu/TiN<Cu/Si₃N₄. The relative impurity content within the deposit was in the range 1.1 to 1.8 at.%. The electrical resistivity for the Cu films on TiN illustrated three regions of the variation according to the substrate temperature, so the deposit at 165°C had the optimum resistivity value. However, the coarsened microstructures of Cu on TiN prepared above 275°C gave rise to higher electrical resistivities compared to those on Si and Si₃N₄ substrates.     

FDTD法分析高速集成电路芯片内互连线

本文首次利用时域有限差分(FDTD)法分析了高速集成电路芯片内半导体基片上的有耗互连传输线的电特性.文中提出了有耗吸收边界条件,推导了不同媒质交界面上的边界条件通用格式.在FDTD分析的基础上,得到传输线各种参数的频变特性,为芯片内电路模拟提供了可靠的参数.     

AlCl_3溶液浸泡对非铬酸系铝箔化成速度及比电容的影响

在室温下,先用NaOH溶液对非铬酸系高纯阳极铝箔进行预处理,再用0.1 mol/L的AlCl3溶液浸泡20 min,然后对铝箔进行腐蚀,清洗及化成。研究了AlCl3溶液浸泡对铝箔化成速度及化成箔比电容的影响。结果显示:在530 V电压化成时,与普通铝箔相比,经AlCl3溶液浸泡过的铝箔的化成时间缩短约了3 min,化成箔的比电容提高了大约4.6%,达到0.612×10–6 F.cm–2。