SAR A/D转换器中电容失配问题的分析

在逐次逼近型(SAR)A/D转换器的设计过程中,电容网络的匹配精度对A/D转换器系统精度有着至关重要的影响。详细推导了电容失配误差与A/D转换器精度的关系表达式,给出了严密的理论证明,为电路设计人员选择工艺、版图方式、电路结构和电容大小提供了有力的理论基础。此论证方式也适用于电阻网络等其他二进制加权网络的精度计算。     

一种基于90nm工艺的10位电荷再分配型逐次逼近模数转换器IP

在比较了三种不同的分段式全电容D/A结构的基础上,介绍了一种10 bit电荷再分配型逐次逼近A/D转换器IP的设计.该转换器采用UMC 90 nm SP-RVT CMOS工艺.该转换器IP的特点是采用了一种利用边缘效应的边缘电容器来代替代价昂贵的PIP和MIM电容器,提高了该IP的工艺兼容性,降低了成本.后仿真结果显示,此A/D转换器在1 Msam-ple/S的速度下,有效位数可达9.6 bit,功耗仅为500μW.     

基于离散混沌系统的A/D转换器研究综述

近年来,利用混沌对初始条件的敏感依赖性进行模数转换,逐步形成了一个新的混沌应用的方向。总结了国内外模数(A/D)转换器研究的文献,综述该新型A/D转换器的基本原理、组成结构和优势,并分析优化混沌A/D转换器的方法。最后,通过对研究现状的归纳总结,对混沌A/D转换器在电容充放电、数学模型改进、转换精度等方面进行展望。     

一种高分辨率自校准单积分型A/D转换器

提出一种具有自校准功能的单积分型高精度A/D转换器.分析了电路原理和电路结构,阐述了如何通过自校准功能提高积分型A/D转换器的性能;给出了A/D转换器结构和测试波形.测试结果表明,设计的A/D转换器采样率为3.3 kSPS,分辨率为14位,相对精度可达0.01%.     

高速高精度A／D转换器结构浅析

全并行(闪烁型)A/D转换器和逐次逼近型A/D转换器不能同时达到很高的转换速度和分辨率。本文介绍了几种能同时实现高速高分辨率A/D转换的电路,并对二步式A/D转换器、分区式A/D转换器以及流水线型A/D转换器的基本原理、结构和误差作了一些分析。     

一种基于映射结构的新颖A/D转换器的研究和仿真

本文研究了一种新型的混沌A/D转换器,这是一种基于非线性映射结构的非流水式ADC,并提出基于开关电容的ADC电路设计.理论分析和实验仿真表明本文所提出的A/D转换器克服了流水结构A/D变换器多级之间的增益匹配和每级中A/D和D/A变换之间的匹配等主要影响精度的设计问题,具有对噪声干扰不敏感等特性,降低了对部分元器件的精度等要求,可能为高速高精度A/D转换器的设计提供一种新的途经.     

一种新颖的T型D/A电容网络的设计

为了克服权电容网络D／A转换器中电容容值相差悬殊的缺点．设计了一种新颖的T型电容网络D／A转换器。相比前者．电容器的电容量相差很小。     

一种电阻串加内插结构的16位D/A转换器

设计了一种10位电阻串分压加6位内插结构的16位电压输出型D/A转换器。高10位采用1 024个电阻串分压网络,低6位采用64个运放输入级内插结构,均采用温度计的方式进行线性叠加,从结构上保证了16位D/A转换器的单调性。该D/A转换器的输出运放采用了PMOS输入折叠式共源共栅加Class AB输出缓冲结构、多级嵌套式密勒补偿(NMCNR),实现了高直流增益和大电容负载下的稳定性。该16位D/A转换器基于0.6 μm CMOS工艺设计,在5 V电源电压下,仿真结果表明,微分非线性误差为0.35 LSB,积分非线性误差为3.05 LSB,建立时间为6.12 μs,无杂散度动态范围(SFDR)为93.41 dB,功耗为1.84 mW。在接470 pF电容负载的条件下,输出运放直流增益为150.63 dB,单位增益带宽为1.59 MHz,相位裕度为65.84°。     

一种用于高速高精度A/D转换器的时钟自举电路

设计了一种双电容结构时钟自举电路,分析了电路工作原理,用Cadence Spectre仿真器和0.35μm CMOS PDK进行电路前仿真和后仿真.仿真结果表明,设计的双电容结构时钟自举电路能使采样电路线性度达到110dB以上,该电路已用于16位A/D转换器的设计并流片.经测试,采用该结构的16位A/D转换器的SFDR为96.25dB(FS),信噪比为76.45dB(FS).     

TI SAR型A/D转换器在电力保护及测量行业的应用

A/D转换器概况,目前市场上主要有以下5种不同结构的A/D转换器：（1）逐次逼近寄存器型也称SAR型A/D转换器。这种结构的转换器通过输入的模拟信号与比较器逐次比较来输出数字信号,是目前应用最多的转换器类型。     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

没有管理者的密钥共享方案

一般的密钥共享方案中都假设有一个管理者,管理者的作用是分发密钥,因此对管理者的可信要求很高,而现实生活中很难找到符合要求的管理者.文中利用单调存取结构上的张成方案构造了一个没有管理者的密钥共享方案,并证明其是一个可行的实用的密钥共享方案.基于这个的方案,构造了一个分布式密钥生成器.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

一种新的多值A/D转换器

通过对三值 A/ D转换数学表示的分析 ,设计了二种三值 A/ D转换器电路。该转换器电路具有结构简单、低功耗、小型化和高信息密度等优点 ,它可进一步完善多值数字系统的研究     

单缸汽油发动机电控系统设计

针对传统发动机使用的化油器反应滞后、控制不精确、排放污染大的问题,以某款单缸化油器式汽油发动机为研究对象,设计了基于MC9S12XS128单片机的电子控制系统。文中分析了单片机对A/D转化信号的采集要求,设计了各个传感器的信号处理电路及驱动电路。通过对发动机工作过程的分析,对整个控制程序进行了模块化设计,并对主要模块的控制算法进行了阐述。实验结果表明,该系统使得发动机的动力性得到了提高,最大功率约提高了6.62%,同时提高了经济性,燃油消耗量（每小时油耗）降低了5.26%,验证了电控系统的有效性。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.