A 20-W stereo class-D audio output power stage in 0.6-/spl mu/m BCDMOS technology

This paper presents a highly power efficient 2/spl times/20-W class-D audio output power stage implemented in 0.6-/spl mu/m BCDMOS technology. The presented power stage is capable of driving 2/spl times/8-/spl Omega/ loads from a 20-V power supply at a power efficiency approaching 90%. Circuit details of thermal detection, over-current protection, and startup speaker click/pop are also presented. The performance of open-loop Class-D output stages are limited by the distortion mechanisms present within the power stage itself. A third-order PWM modulator was prototyped and used to dramatically improve the performance of the Class-D output stage by using feedback. The results of this work are also presented.     

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.     

A 25-MS/s 14-b 200-mW /spl Sigma//spl Delta/ Modulator in 0.18-/spl mu/m CMOS

The design of a fifth-order 4-b quantizer single-loop /spl Sigma//spl Delta/ modulator is presented that achieves 25-MS/s conversion rate with 84 dB of dynamic range and 82 dB of signal-to-noise ratio. Implemented in a 0.18-/spl mu/m CMOS technology, the 0.95-mm/sup 2/ chip has a power consumption of 200 mW from a 1.8-V supply.     

Integrated stereo /spl Delta//spl Sigma/ class D amplifier

A 2/spl times/40 W class D amplifier chip is realized in 0.6-/spl mu/m BCDMOS technology, integrating two delta-sigma (/spl Delta//spl Sigma/) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency.     

Noise-shaping sense amplifier for MRAM cross-point arrays

A sensing technique using a voltage-mode architecture, noise-shaping modulator, and digital filter (a counter) is presented for use with cross-point MRAM arrays and magnetic tunnel junction memory cells. The presented technique eliminates the need for precision components, the use of calibrations, and reduces the effects of power supply noise. To obviate the effects of cell-to-cell variations in the array, a digital self-referencing scheme using the counter is presented. Measured experimental results in a 180-nm CMOS process indicate an RMS sensing noise of 20 /spl mu/V for a 5-/spl mu/s sense time. Further increases in sense time are shown to increase the signal-to-noise ratio. The current used by the sense amplifier and counter was measured as 10 /spl mu/A when running at 100 MHz or 10 mA when 1000 sense amplifiers are used with a memory subarray having 1000 bitlines.     

A 2.2-mW CMOS bandpass continuous-time multibit /spl Delta/-/spl Sigma/ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications

A delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter featuring 68-dB dynamic range and 64-dB signal-to-noise ratio in a 1-MHz bandwidth centered at an intermediate frequency of 2 MHz with a 48-MHz sample rate is reported. A second-order continuous-time modulator employing 4-bit quantization is used to achieve this performance with 2.2 mW of power consumption from a 1.8-V supply. The modulator including references occupies 0.36 mm/sup 2/ of die area and is implemented in a 0.18-/spl mu/m five-metal single-poly digital CMOS process.     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver

A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase detector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop bandwidth. Fabricated in a 0.13-/spl mu/m CMOS technology in an area of 280/spl times/100 /spl mu/m/sup 2/, the clock and data recovery loop exhibits a frequency tracking range up to 2000 ppm. The bit error rate is less than 10/sup -12/ with a pseudorandom bit sequence of length 2/sup 31/-1. The power dissipation is 24 mW for clock and data recovery circuits from a single 1.2-V supply.     

A 0.7-V MOSFET-only switched-opamp /spl Sigma//spl Delta/ modulator in standard digital CMOS technology

A 0.7-V MOSFET-only /spl Sigma//spl Delta/ modulator for voice band applications is presented. The second-order modulator is realized using a switched-opamp technique. All capacitors are realized using compensated MOS devices operated in the depletion region. A combination of parallel and series compensated depletion-mode MOSCAPs is used to obtain high area efficiency. The circuit is fabricated in a 0.18-/spl mu/m CMOS process. The only components used are standard n-MOS and p-MOS transistors with threshold voltages of approximately 400 mV. All transistors are operated within the supply voltage window of 0.7 V; voltage boosting techniques are not used. The active area is 0.082 mm/sup 2/. The modulator achieves 67-dB signal-to-noise-and-distortion ratio, 70-dB signal-to-noise ratio, and 75-dB dynamic range at 8-kHz signal bandwidth and consumes 80 /spl mu/W of power.     

A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.     

Direct radio-frequency digital angle modulator

A radio frequency angle modulator is proposed with a direct digital data interface using 0.18 /spl mu/m CMOS technology. It consumes 42 mW, occupies a chip size of 0.936/spl times/0.935 mm, and shows a measured error vector magnitude of 0.55% at 2.468 GHz with 5.5 Mbit/s data rate.     

Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology

This paper examines the design and implementation of a fourth-order low-pass delta-sigma modulator using a systematic top-down design methodology. Special effort has been made to reduce the power consumption of the modulator through careful system-level modeling and synthesis of circuit specifications. Tradeoffs between circuit building block specifications, optimization time and computing resources are derived. This system-level modeling was tested through the successful implementation of a switched-capacitor delta-sigma analog-to-digital converter integrated circuit (IC) with an output rate slightly exceeding 2 MS/s, in a 1.8-V 0.18-/spl mu/m, single-polysilicon six-metal standard CMOS process. When sampled at 50 MHz, experimental results reveal that the IC achieves 77.6-dB dynamic range. The prototype consumes 18.8 mW of power, making it one of the lowest power dissipations in switched-capacitor implementations, and for applications where output rates exceed 2 MS/s. When compared to other state-of-the-art switched-capacitor modulators using a widely adopted figure of merit, the modulator dissipates less power and offers superior overall performance.     

A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

This paper presents the first implementation results for a time-interleaved continuous-time /spl Delta//spl Sigma/ modulator. The derivation of the time-interleaved continuous-time /spl Delta//spl Sigma/ modulator from a discrete-time /spl Delta//spl Sigma/ modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass /spl Delta//spl Sigma/ modulator is designed in a 0.18-/spl mu/m CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively.     

An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.     

Burst-mode clock and data recovery in optical multiaccess networks using broad-band PLLs

Broad-band phase-locked loops (PLLs) are proposed for burst-mode clock and data recovery in optical multiaccess networks. Design parameters for a charge-pump PLL-based clock and data recovery (CDR) with fast phase acquisition are derived using a time-domain model that does not assume narrow loop bandwidth or small phase errors. Implementation in a half-rate CDR circuit confirms a clock phase acquisition time of 40 ns, or 100 bits at 2.488-Gb/s rate, and data recovery at 1.244-Gb/s rate with a bit-error rate of 1/spl times/10/sup -10/ (2/sup 14/-1 pseudorandom binary sequence with Manchester-encoding). The CDR was fabricated in complementary metal-oxide-semiconductor 0.18-/spl mu/m technology in an area of 1/spl times/1 mm/sup 2/ and consumes 54 mW of power from a 1.8-V supply.     

Self-heating and trapping effects on the RF performance of GaN MESFETs

RF power performances of GaN MESFETs incorporating self-heating and trapping effects are reported. A physics-based large-signal model is used, which includes temperature dependences of transport and trapping parameters. Current collapse and dc-to-RF dispersion of output resistance and transconductance due to traps have been accounted for in the formulation. Calculated dc and pulsed I-V characteristics are in excellent agreement with the measured data. At 2 GHz, calculated maximum output power of a 0.3 /spl mu/m/spl times/100 /spl mu/m GaN MESFET is 22.8 dBm at the power gain of 6.1 dB and power-added efficiency of 28.5% are in excellent agreement with the corresponding measured values of 23 dBm, 5.8 dB, and 27.5%, respectively. Better thermal stability is observed for longer gate-length devices due to lower dissipation power density. At 2 GHz, gain compressions due to self-heating are 2.2, 1.9, and 0.75 dB for 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs, respectively. Significant increase in gain compression due to thermal effects is reported at elevated frequencies. At 2-GHz and 10-dBm output power, calculated third-order intermodulations (IM3s) of 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs are -61, -54, and - 45 dBc, respectively. For the same devices, the IM3 increases by 9, 6, and 3 dBc due to self-heating effects, respectively. Due to self-heating effects, the output referred third-order intercept point decreases by 4 dBm in a 0.30 /spl mu/m/spl times/100 /spl mu/m device.     

MQW DBR lasers with monolithically integrated external-cavity electroabsorption modulators fabricated without modification of the active region

In this letter, we report the design and operation of multiple-quantum-well distributed Bragg reflectors (MQW DBR) lasers with monolithically integrated external-cavity electroabsorption (EA) modulators without modification of the active region fabricated using only a single growth step. Devices were fabricated with operating wavelengths of 1.06, 1.07, and 1.08 /spl mu/m, which are red-shifted from the material gain peak wavelength (/spl lambda/=1.05 /spl mu/m) by 100, 200, and 300 /spl Aring/, respectively. The /spl lambda/=1.06-/spl mu/m device has a continuous-wave (CW) threshold current of 16 mA and a slope efficiency of 0.09 W/A from the modulator facet, while the /spl lambda/=1.08 /spl mu/m device has a CW threshold current of 33 mA and a slope efficiency of 0.40 W/A from the modulator facet. The /spl lambda/=1.06-, 1.07-, and 1.08-/spl mu/m device exhibits an extinction ratio of /spl ges/20 dB at a modulator bias of 1.0, 1.4, and 2 V, respectively.     

10-Gb/s modulator drivers with local feedback networks

A novel intrinsic collector-base capacitance (C/sub CB/) feedback network (ICBCFN) was incorporated into the conventional cascode and series-connected voltage balancing (SCVB) circuit configurations to implement 10-Gb/s modulator drivers. The drivers fabricated in 0.35-/spl mu/m SiGe BiCMOS process could generate 9 V/sub PP/ differential output swings with rise/fall time of less than 29 ps. Also, the ICBCFN was modified as an intrinsic drain-gate capacitance feedback network (IDGCFN) to implement drivers with differential output swing of 8 V/sub PP/ in 0.18-/spl mu/m CMOS process. The power consumption is as low as 0.6 W. The present work shows that the driving capability is greater than that of the currently reported silicon-based drivers.     

High-efficiency 1.3 /spl mu/m InAsP-GaInP MQW electroabsorption waveguide modulators for microwave fiber-optic links

High-efficiency electroabsorption waveguide modulators have been designed and fabricated using strain-compensated InAsP-GaInP multiple quantum wells at 1.32-/spl mu/m wavelength. A typical 200-/spl mu/m-long modulator exhibits a fiber-to-fiber optical insertion loss of 9 dB and an optical saturation intensity larger than 10 mW. The 3-dB electrical bandwidth is in excess of 20 GHz with a 50-/spl Omega/ load termination. When used in an analog microwave fiber-optic link without amplification, a RF link efficiency as high as -38 dB is achieved at 10 mW input optical carrier power. These analog link characteristics are the first reported using MQW electroabsorption waveguide modulators at 1.32 /spl mu/m.     

A 32-Mb chain FeRAM with segment/stitch array architecture

This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-/spl mu/m three-metal CMOS technology. A small die size of 96 mm/sup 2/ and a high cell/chip area efficiency of 65.6% are realized not only by the small cell size using capacitor-on-plug technology but also by two key techniques that utilize the three-metal process: 1) a compact memory cell block structure that eliminates plateline area and reduces block selector area and 2) the segment/stitch array architecture which reduces the area of row decoders and plate drivers. As a result, the average cell size shrinks to 1.875 /spl mu/m/sup 2/, which is smaller than a 0.13-/spl mu/m SRAM cell, and the chip size is reduced to 70% of the chain FeRAM of conventional configuration with two-metal process. Moreover, a power-on/off sequence suitable to the chain FeRAM is introduced to protect the memory cell data from the startup noise. Compatibility with low-power SRAM is a key issue for mobile applications. The low-standby-current bias generator is introduced and the standby current of the chip is suppressed to 3 /spl mu/A. The modified address access mode is also adopted to eliminate the need of intentional address transition after the startup of the chip. The chip enable access time was 50 ns and cycle time was 75 ns at 3.0-V V/sub dd/.