An analog CMOS front-end for a D2-MAC TV decoder

This paper describes the analog front-end of a fully integrated CMOS TV decoder, suitable for the reception of terrestrial as well as satellite signals, based on the D2-MAC transmission system. While the video reconstruction is undertaken using DSP, the front-end subsystem incorporates many linear and non-linear analog functions, including amplitude measuring, AGC, clamping, data slicing, clock recovery and of course, A/D conversion for the MAC signal processing. The chip is fabricated in 1-μ CMOS, and operates from a single 5-V supply     

A single-chip CMOS analog/digital mixed NTSC decoder

A single-chip CMOS LSI that integrates all analog-to-digital (A/D), digital-to-analog (D/A), peripheral, and digital signal processing circuits necessary for a digital National Television System Committee (NTSC) signal decoder is described. The LSI chip accepts composite NTSC video signals in analog form, digitizes them using the on-chip A/D converter, converts them to component RGB signals, and then converts the signals to analog form by using the on-chip D/A converters. The development of circuits that maximize use of the input digital data is discussed. A 6-b A/D circuit is used to reduce the circuit size. Circuits that help maintain acceptable picture quality despite 6-b resolution were developed. Besides analog NTSC signal input and RGB signal output, the IC can also input and output digital NTSC signals, Y/C (luminance, chrominance) signals, and RGB signals. Applications of the LSI are presented     

循环汉明码编译码器的设计与FPGA实现

分析了循环码的特性,提出一种循环汉明码编译码器的设计方案。编译码器中编码采用除法电路,译码采用梅吉特译码器,易于工程应用。对编译码器在FPGA上进行了实现,通过参数化设置,具有较高的码率,适用于(255,247)及其任意缩短码的循环汉明码,并给出了译码器的仿真和测试结果。结果表明:编译码器运行速率高、译码时延小,在Virtex-5芯片上,最高工作时钟频率大于270 MHz。在码组错误个数确定的系统应用中,可以有效降低误码率,一般可将误码率降低一个量级。实践表明,该设计具有很强的工程实用价值。     

A 0.35-/spl mu/m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code

This work presents the design and the test results of an analog decoder for the 40-bit block length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated in a three-metal double-poly 0.35-/spl mu/m CMOS technology, and includes an I/O interface that maximizes the decoder throughput. After the successful implementation of proof-of-concept analog iterative decoders by different research groups in both bipolar and CMOS technologies, this is the first reported prototype of an analog decoder for a realistic error-correcting code. The decoder was successfully tested at the maximum data rate defined in the standard (2 Mb/s), with an overall power consumption of 10.3 mW at 3.3 V, going down to 7.6 mW with the decoder core operated at 2 V, and an extremely low energy per decoded bit and trellis state (0.85 nJ for the decoder core alone).     

A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder

This paper describes a 4-state rate-1/2 analog convolutional decoder fabricated in 0.8-μm CMOS technology. Although analog implementations have been described in the literature, this decoder is the first to be reported realizing the add-compare-select section entirely with current-mode analog circuits. It operates at data rates up to 115 Mb/s (channel rate 230 Mb/s) and consumes 39 mW at that rate from a single 2.8-V power supply. At a rate of 100 Mb/s, the power consumption per trellis state is about 1/3 that of a comparable digital system. In addition, at 50 Mb/s (the only rate at which comparative data were available), the power consumption per trellis state is similarly about 1/3 that of the best competing analog realization (i.e., excluding, for example, PR4 detectors which use a simplified form of the Viterbi algorithm). The chip contains 3.7 K transistors of which less than 1 K are used in the analog part of the decoder. The die has a core area of 1 mm², of which about 1/3 contains the analog section. The measured performance is close to that of an ideal Viterbi decoder with infinite quantization. In addition, a technique is described which extends the application of the circuits to decoders with a larger number of states. A typical example is a 64-state decoder for use in high-speed satellite communications     

Lattice code decoder for space-time codes

We explore the lattice sphere packing representation of a multi-antenna system and the algebraic space-time (ST) codes. We apply the sphere decoding (SD) algorithm to the resulted lattice code. For the uncoded system, SD yields, with small increase in complexity, a huge improvement over the well-known V-BLAST detection algorithm. SD of algebraic ST codes exploits the full diversity of the coded multi-antenna system, and makes the proposed scheme very appealing to take advantage of the richness of the multi-antenna environment. The fact that the SD does not depend on the constellation size, gives rise to systems with very high spectral efficiency, maximum-likelihood performance, and low decoding complexity     

Threshold decoder and two feedback checkers for nonsystematic convolutional code (2,1,6)

A threshold decoder of the well known convolutional code (2,1,6) is proposed. Two simple approaches to reduce error propagation are presented. This decoder can be used when the communication channel does not require a more efficient and expensive decoder such as the Viterbi decoder.<>     

基于FPGA的IRIG-B(AC)时间码解码器的设计

为了解决IRIG-B(AC)码解码精度低的问题,提高解调系统的稳定性,提出了一种利用高性能FPGA实现解调IRIG-B(AC)码的解码器。通过调用FPGA的IP核生成乘法器与FIR低通滤波器,将B(AC)码中的交流分量滤除掉,然后根据其幅值进行解调。该解码器能够快速准确地解调出IRIG-B(AC)码的时间信息,并输出与此时间信息对应的秒脉冲,通过输出端口将解调出的时间信息传输到上位机显示。通过大量试验证明该解码器准确度高、稳定性强,能够满足各种应用场所对IRIG-B(AC)码授时的要求。     

2,1,7卷积码Viterbi译码器的一种设计方案

卷积码在通信系统中得到了极为广泛的应用.其中约束长度K=7,码率为1/2和1/3的Odenwalder卷积码已经成为商业卫星通信系统中的标准编码方法.提出了一种(2,1,7)卷积码Viterbi译码器的设计方案,该译码器采用全并行结构的加/比/选模块和回溯法以提高译码速度,重点介绍了幸存路径存储与交换单元的设计与实现.     

A 285-MHz pipelined MAP decoder in 0.18-/spl mu/m CMOS

Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm/sup 2/ IC is implemented in a 1.8-V 0.18-/spl mu/m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energy-efficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18-/spl mu/m designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4.3/spl times/ with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture.     

Bidirectional per-survivor processing decoder for space-timetrellis code

A novel decoder for a space-time trellis code (STTC) used in a TDMA downlink is developed which performs adaptive decoding with bidirectional per-survivor processing and soft-decision. Simulation results are given, which demonstrate the system performance improvement which can be realised using this proposed decoder     

MAP译码器的免归一化处理信息更新算法

在不改变译码性能的条件下,为了加快最大后验概率(Maximum A Posteriori Probability,MAP)译码器状态信息更新的速度和降低算法的复杂度,提出了一种用于Turbo码的MAP译码器的免归一化处理算法.算法采用二进制补码加法器和减法器将MAP译码过程中的状态信息投影到一个归一化圆上,当状态信息更新时所有的状态信息在归一化圆上移动,通过保持归一化圆上状态信息的正确关系来计算似然比.归一化过程中不用搜索或估计状态信息的最大值,通过简化状态信息归一化过程加速了MAP译码器的状态信息更新并降低了复杂度.所提算法在与传统算法译码性能相同的情况下,可以降低36.2％的计算复杂度和17.4％的关键路径延迟,达到MAP译码器实现中的高速、低复杂度目标.     

A built-in Hamming code ECC circuit for DRAMs

An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique     

VLSI implementation of a maximum-likelihood decoder for the Golay(24, 12) code

J.H. Conway and N.J.A. Sloane (1986) have introduced an algorithm for the exact maximum-likelihood decoding of the Golay (24, 12) code in the additive white Gaussian noise channel that requires significantly fewer computations than previous algorithms. An efficient bit-serial VLSI implementation of this algorithm is described. The design consists of two chips developed using path-programmable logic (PPL) and an associated system of automated design tools for three-μm NMOS technology. It is estimated that this decoder will produce an information bit every 1.6-2.4 μs. Higher speeds can be achieved by using a faster technology or by replicating the chips to perform more operations in parallel     

A universal lattice code decoder for fading channels

We present a maximum-likelihood decoding algorithm for an arbitrary lattice code when used over an independent fading channel with perfect channel state information at the receiver. The decoder is based on a bounded distance search among the lattice points falling inside a sphere centered at the received point. By judicious choice of the decoding radius we show that this decoder can be practically used to decode lattice codes of dimension up to 32 in a fading environment     

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 μm CMOS process. Experimental results obtained from it are presented     

Bit-interleaved Hamming code for linearly repeatered terrestrialSDH transmission systems

A bit-interleaved SEC shortened Hamming code is proposed for all SDH levels. The error caused by ASE noise in a 156 Mbit/s optical preamplifier is successfully corrected     

Fully-depleted SOI CMOS for analog applications

Fully-depleted (FD) SOI MOSFETs offer near-ideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFETs at high temperature or at gigahertz frequencies is outlined as well     

Joint (3,k)-regular LDPC code and decoder/encoder design

Recently, low-density parity-check (LDPC) codes have attracted a lot of attention in the coding theory community. However, their real-world applications are still problematic mainly due to the lack of effective decoder/encoder hardware design approaches. In this paper, we present a joint (3,k)-regular LDPC code and decoder/encoder design technique to construct a class of (3,k)-regular LDPC codes that not only have very good error-correcting capability but also exactly fit to high-speed partly parallel decoder and low-complexity encoder implementations. We also develop two techniques to further modify this joint design scheme to achieve more flexible tradeoffs between decoder hardware complexity and decoding speed.     

Low-complexity maximum-likelihood decoder for four-transmit-antenna quasi-orthogonal space-time block code

This letter proposes a very low-complexity maximum-likelihood (ML) detection algorithm based on QR decomposition for the quasi-orthogonal space-time block code (QSTBC) with four transmit antennas, called the LC-ML decoder. The proposed algorithm enables the QSTBC to achieve ML performance with significant reduction in computational load for any high-level modulation scheme.