A sixth-order continuous-time bandpass sigma-delta modulator fordigital radio IF

This paper presents a sixth-order continuous-time bandpass sigma-delta modulator (SDM) for analog-to-digital conversion of intermediate-frequency signals. An important aspect in the design of this SDM is the stability analysis using the describing function method. The key to the analysis is the extension of the linear gain model for the sampled quantizer with a phase uncertainty. The single-loop, one-bit SDM is tuned at 10.7 MHz, is sampled at 40 MHz, and achieves 67-dB signal-to-(noise+distortion) ratio in 200 kHz and 80 dB in 9 kHz. The third order intermodulation is at -82 dBc for a -13-dBFS input level. The 0.5-μm CMOS chip occupies 0.9×0.4 mm² and consumes 60 mW at 3.3 V (digital) and 5.0 V (analog). The sample frequency is variable and can be set from 30 to 80 MHz     

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator.A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator.The proposed modulator uses sampling capacitor sharing switched capacitor integrator,and achieves a very small feedback coefficient by a series capacitor network,and those two techniques can dramatically reduce capacitor area.Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation.This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and-1 MHz IF with 48 MHz clock.The chip is fabricated with SMIC 0.18 μm CMOS technology,it achieves a total power current of 2.1 mA,and the chip area is 0.48 mm2.     

A fourth-order bandpass sigma-delta modulator

The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta (ΣΔ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio     

A CMOS bandpass filter for low-IF bluetooth receivers

A CMOS fully integrated 12th-order bandpass filter for low interemdiate frequency Bluetooth receivers is presented. The design is optimized to meet the selectivity and dynamic range requirements of Bluetooth while consuming relatively low power. The filter is based on unity gain cells and utilizes linearized MOSFET resistors for tuning. It exhibits a bandwidth of 1 MHz and a programmable center frequency range of 2 to 4 MHz. Experimental results obtained from a standard 0.5-/spl mu/m CMOS chip show that the filter exhibits an in-band dynamic range of 53.3 dB at gain of 0 dB, and 52 dB at gain of 15 dB, while consuming a total current of 1.32 mA. Attenuations of more than 10, 38, and 55 dB, are achieved for blockers one, two, and three, respectively.     

Direct-conversion bandpass sigma-delta modulator

A bandpass sigma-delta modulation analogue-to-digital (A/D) converter that uses direct conversion to baseband with in phase and quadrature paths within the feedback loop is described. The bandpass input signal is processed with continuous-time circuitry and the I/Q baseband signals are processed with switched-capacitor circuits. Experimental and simulation results indicate that the passband centre frequency can be maximised while suppressing the effects of I/Q mismatches     

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply.     

A 1.8 V CMOS fourth-order Gm-C bandpass sigma-delta modulator dedicated to front-end ultrasonic receivers

A 4th order bandpass sigma-delta modulator for ultrasound applications is presented. By cascading two second-order identical Gm-C bandpass filters, a 4th-order modulator was designed with high power-efficiency, stability, tunability and programmability. The modulator is dedicated for application with intermediate frequency of 3 MHz and bandwidth of 200 kHz. Implemented in a standard 0.18 μm CMOS technology, the post-layout simulation of the modulator gives a dynamic range of 78 dB. Chip measurements are reported after successfully tuning the modulator to operate at four-time of its folded specifications. The final SNR achieves 58 dB at 0.75 MHz with 50 kHz bandwidth. The modulator consumes 2.5 mW from 1.8 V power supply. Moreover, a programming method is introduced and corresponding circuit is designed to change the central frequency of the modulator between 3 and 20 MHz for scanning different regions of the body. However the 200 kHz bandwidth limits the modulator only for Dobbler mode applications, the effective facilities of programmability are valuable property to expand this application to other wide band applications in future. Lisheng Qin received the B.Sc. degree in electrical engineering from Tianjin University, China in 1992. He was with Polystim Neurotechnologies Laboratory from 2001 to 2005 and received the M.Sc. degree in electronics engineering from Ecole Polytechnique de Montreal, Canada in 2005. He is now with Apexone Microelectronics Inc. as Analog/Mixed-Signal Design Engineer. Kamal El-Sankary received the B.Sc. degree in electrical engineering from the Lebanese University, Lebanon in 1997 and the M.Sc. degree in electronics engineering from University of Quebec in Trois Rivieres, Canada, in 2001. He is currently pursuing the Ph.D. degree in microelectronics at Ecole Polytechnique de Montreal, Canada. His research interests include analog/mixed-signal circuits design and signal processing. Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics. His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the Microelectronics Strategic Alliance of Quebec (Regroupement stratégique en microélectronique du Québec - ReSMiQ). He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter, the International IEEE-NEWCAS conference, and Polystim neurotechnologies laboratory at the Ecole Polytechnique de Montreal. He is cofounder of the International Functional Electrical Stimulation Society (IFESS), and the IEEE International conference on Electronics, Circuits and Systems (ICECS). Dr. Sawan is involved in the committees of many national and international conferences and other scientific events. He published more than 300 papers in peer reviewed journals and conference proceedings and is awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society, President of the biomedical circuits and systems (BioCAS) technical committee of the IEEE CAS Society, and he is representative of IEEE-CAS in the International Biotechnology council. He received the Barbara Turnbull 2003 award for spinal cord research, the Medal of Merit from Lebanon, and the Bombardier Medal from the French Association for the advancement of sciences. Dr. Sawan is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE.     

Elliptic filtering in continuous-time sigma-delta modulator

An improved continuous-time sigma-delta (/spl Sigma//spl Delta/) architecture with elliptic signal transfer function is presented. It is demonstrated that the UTRA/FDD band 1 interferer filtering can be fully achieved within the sigma-delta loop.     

A two-path bandpass sigma-delta modulator with extended noiseshaping

A three-stage bandpass sigma-delta (ΣΔ) analog-to-digital converter has been designed specifically for operation at low oversampling ratios. In the proposed architecture, the center frequency of the third stage is shifted slightly from that of the first two stages to achieve more efficient noise shaping across the signal band. An experimental modulator based on the proposed topology has been integrated in a 0.25-μm CMOS technology and achieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distortion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an f_s/4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and its active area is 4 mm²     

A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator

This paper describes a 0.35-/spl mu/m CMOS fourth-order bandpass analog-digital sigma-delta (/spl Sigma//spl Delta/) modulator for wide-band base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The /spl Sigma//spl Delta/ modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 mm/sup 2/ of silicon area.     

Digital based calibration technique for continuous-time bandpass sigma-delta analog-to-digital converters

In this paper, a calibration technique for Noise Transfer Function (NTF) optimization of Continuous-Time Bandpass Sigma Delta (CT BP ΣΔ) modulators is presented. The proposed technique employs a test tone applied at the input of the quantizer to evaluate the noise transfer function of the Analog-to-Digital Converter (ADC) using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed-mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal-to-Quantization Noise Ratio (SQNR) performance is extracted via an LMS software-based algorithm. Simulation results show that notch frequency of the NTF due to process variations and temperature tolerances can be tuned using the proposed methodology. The proposed global calibration approach can be used during the system start-up and the idle system time. The proposed approach uses a single in-band calibration tone, but it can be expanded using out-of band test tones for background calibration schemes.     

A 400-Ms/s frequency translating bandpass sigma-delta modulator

A bandpass Σ-Δ modulator is described in this paper that uses frequency translation inside the Σ-Δ modulator loop to take advantage of the attributes of both continuous-time and discrete-time circuits. A CMOS direct-conversion modulator digitizes a 200 kHz intermediate-frequency signal centered at 100 MHz and produces baseband I/Q outputs with a peak signal-to-noise ratio of 54 dB. Images due to I/Q mismatches are suppressed by 50 dB. This 0.35-μm digital CMOS chip operates from a 2.7/3.3-V supply, dissipates 330 mW, and occupies 3.2 mm²     

A novel image rejection architecture for quadrature radio receivers

In radio communications, a bandpass-to-lowpass transformation is needed to demodulate the received signal down to baseband. One crucial question in this context is how to effectively attenuate the image band signal. For this purpose, inphase/quadrature (I/Q) signal processing is widely utilized in today's radio receivers. In this paper, a novel structure for obtaining an image-free baseband observation of the received bandpass signal is presented. The starting point is to approximate the needed 90/spl deg/ phase difference between the I and Q branch signals using a simple time delay of one quarter of the carrier cycle. For narrowband signals, this approach can be used directly to attenuate the inherent "self-image". By using an interference canceller-type of compensation technique, this concept is here generalized to cover also wideband multichannel signals. Furthermore, a closed-form expression to explicitly characterize the obtainable image attenuation is derived. Efficient implementation structures for digital radios utilizing periodically nonuniform subsampling are presented, and the validity of the proposed approach is further illustrated through simulation and design examples.     

Low-distortion bandpass /spl Sigma/-/spl Delta/ modulator for wireless radio receivers

A low-distortion bandpass sigma-delta modulator is proposed. It was found that the key to improving linearity is to add a feedforward signal path in a double-delay resonator bandpass structure. The proposed technique improves the tonal behaviour even at low oversampling ratio and can be applied for any order of modulator. Based on the proposed architecture, a fourth-order single-bit sigma-delta modulator can achieve a dynamic range of 84 dB and a spurious free dynamic range of 98 dB at 10.71 MHz with a signal bandwidth of 200 kHz, making it ideal for a narrowband IF-sampled wireless receiver designed for compliance with GSM/GPRS standards.     

Two-step channel selection technique by programmable digital-double quadrature sampling for complex low-IF receivers

Presents a novel two-step channel selection technique to be adopted in complex low-IF receivers for enhancing the performance and efficiency of the front-end PLL-frequency synthesiser (PLL-FS), which will be mainly implemented by a proposed programmable digital-double quadrature sampling (D-DQS) scheme. Thus, the weaknesses of the PLL-FS in very small step-size operations including long locking time and large phase noise are significantly reduced. Simulation results of the D-DQS scheme are provided to demonstrated the feasibility of such a technique.     

A novel two-channel continuous-time time-interleaved 3rd-order sigma-delta modulator with integrator-sharing topology

This paper presents a 3rd-order two-path continuous-time time-interleaved (CTTI) delta-sigma modulator which is implemented in standard 90 nm CMOS technology. The architecture uses a novel method to resolve the delayless feedback path issue arising from the sharing of integrators between paths. By exploiting the concept of the time-interleaving techniques and through the use time domain equations, a conventional single path 3rd-order discrete-time (DT) ΔΣ modulator is converted into a corresponding two-path discrete-time time-interleaved (DTTI) counterpart. The equivalent CTTI version derived from the DTTI ΔΣ modulator by determining the DT loop filters and converting them to the equivalent continuous-time loop filters through the use of the Impulse Invariant Transformation. Sharing the integrators between two paths of the reported modulator makes it robust to path mismatch effects compared to the typical time-interleaved modulators which have individual integrators in all paths. The modulator achieves a dynamic range of 12 bits with an OverSampling Ratio of 16 over a bandwidth of 10 MHz and dissipates only 28 mW of power from a 1.8-V supply. The clock frequency of the modulator is 320 MHz but integrators, quantizers and DACs operate at 160 MHz.     

A 1-V 60-μW 85-dB dynamic range continuous-time third-order sigma-delta modulator

A 1-V third order one-bit continuous-time (CT) ΣΔ modulator is presented. Designed in the SMIC mixed-signal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ΣΔ modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dBdynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm~2.     

Sixth-order programmable bandwidth bandpass sigma-delta modulator implemented with transmission lines

An implementation of a sixth-order bandpass continuous time sigma-delta modulator using transmission lines is presented. A single tuning coefficient allows the exchange of resolution and bandwidth in this modulator, owing to the use of a two path transformation that exploits the similarity between transmission line modulators and discrete time modulators. The modulator tolerates two clock cycles of excess loop delay and a high clock jitter.     

Analog signal generator for BIST of wideband IF signals bandpass sigma-delta modulator

This paper presents improvements in generation of wideband and high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma-delta modulator chip. Via increasing the order of the one-bit bandpass sigma-delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma-delta modulator chip's production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.