Low-resistance bandgap-engineeredW/Si1-xGex/Si contacts

Bandgap-engineered W/Si_1-xGe_x/Si junctions (p⁺ and n⁺) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si_0.7Ge _0.3 layer which is implanted and annealed using RTA. The Si _1-xGe_x layer can then be selectively thinned using NH₄OH/H₂O₂/H₂O at 75°C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6×10^-9 A/cm² (areal), 7.45×10^-12 A/cm (peripheral) for p⁺/n and 3.5×10^-10 A/cm² (peripheral) for n⁺/p. W contacts were formed using selective LPCVD on Si_1-xGe_x. A specific contact resistivity of better than 3.2×10^-8 Ω cm² for p ⁺/n and 2.2×10^-8 Ω cm² for n⁺/p is demonstrated-an order of magnitude n⁺ better than current TiSi₂ technology. W/Si_1-xGe _x/Si junctions show great potential for ULSI applications     

Numerical simulation and comparison of Si BJTs andSi1-xGex HBTs

Using the Monte Carlo method for the solution of the Boltzmann transport equation, the authors analyze the low-field carrier mobilities of strained layer and bulk Si and Si_1-xGe_x alloys. Strained alloy layers exhibit higher low-field mobility compared with bulk Si at doping levels >10¹⁸ cm^-3 and for a Ge mole fraction x⩽0.2, while the unstrained alloy bulk low-field mobility is always lower than that of Si for any doping level or mole fraction. These mobilities are then used in a two-dimensional drift-diffusion equation solver to simulate the performance of Si BJTs (bipolar junction transistors) and Si_1-xGe_x HBTs (heterojunction bipolar transistors). The substitution of a Si_0.8 Ge_0.2 layer for the base region leads to a significant improvement in current gain, turn-on voltage, and high-frequency performance. Maximum unity current gain frequency f_T increases two times over that of an Si BJT if the bulk alloy mobility is used for the alloy base layer; it increases three times if strained-layer mobility is used. Maximum frequency of oscillation also improves, but not as dramatically as f_T     

The scaled performance of Si/Si1-xGexresonant tunneling diodes

Small area resonant tunneling diodes (RTDs) with strained Si_0.4Ge_0.6 potential barriers and a strained Si quantum well grown on a relaxed Si_0.8Ge_0.2 virtual substrate were fabricated and characterized. A room temperature peak current density (J_P) of 282 kA/cm² with a peak to valley current ratio (PVCR) of 2.43 were recorded for a 5×5 μm ² sample, the highest values reported to date for Si/Si_1-xGe_x RTDs. Scaling of the device size demonstrated a decrease in J_P proportional to an increase in the lateral area of the tunnel junctions, whereas the PVCR remained approximately constant. This observation suggests that the dc behavior of such Si/Si_1-xGe_x RTD design is presently limited by thermal effects     

Low- and high-field electron-transport parameters for unstrainedand strained Si1-xGex

Ohmic minority and majority drift mobilities as well as saturation velocities are reported for unstrained and strained Si_1-xGe _x alloys up to z=0.31. The electron-transport model is verified by measurements of the in-plane majority drift mobility in strained Si_1-xGe_x samples for various dopant and Ge concentrations. Saturation velocities are determined by full-band Monte Carlo simulations. There is no substantial decrease in the mobility perpendicular to the Si/SiGe interface for doping concentrations above 10¹⁹ cm^-3 and growing x. In contrast, the saturation-drift velocity is strongly reduced with x     

Electrical and material quality ofSi1-xGex/Si p-N heterojunctions produced bylimited reaction processing

Si_1-xGe_x/Si p-N heterojunctions prepared by a chemical vapor deposition technique, limited reaction processing (LRP) were characterized using DC electrical measurements, transmission electron microscopy (TEM), and X-ray topography. Heterojunctions with Si _1-xGe_x layer thickness ranging from 52 to 295 nm and a constant Ge fraction of 23% were fabricated to study the effect of increasing the number of misfit dislocations on the device characteristics. Devices with the thinnest layers (⩽120 nm) display forward characteristics with ideality factors of 1.01 and reverse leakage current densities of less than 4 nA/cm for a 5-V reverse bias. These thin-layer devices have dislocation spacings greater than 10 μm. Devices utilizing Si_1-xGe_x layers thicker than 200 nm have forward characteristics which clearly display the presence of recombination currents, and reverse leakage current densities greater than 290 nA/cm² at -5 V. The dislocation spacing in these devices is less than 1 μm. Ideal characteristics were found at room temperature in devices known to contain dislocations     

High-speed performance of Si/Si1-xGexheterojunction bipolar transistors

A theoretical investigation of Si/Si_1-xGe_x heterojunction bipolar transistors (HBTs) undertaken in an attempt to determine their speed potential is discussed. The analysis is based on a compact transistor model, and devices with self-aligned geometry, including both extrinsic and intrinsic parameters, are considered. For an emitter area of 1×5 μm², an f_t of over 75 GHz and f_max of over 35 GHz were computed at a collector current density of 1×10 ⁵ A/cm² and V_CB of 5 V     

Reduction of source/drain series resistance and its impact ondevice performance for PMOS transistors with raised Si1-xGex source/drain

P-channel MOS transistors with raised Si_1-xGe_x and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si_1-xGe_x and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si_1-xGe_x S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R_SD), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R_SD of devices with Si_1-xGe_x raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g_m) at an effective channel length of 0.16 μm. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si_1-xGe_x S/D structure very attractive for future sub-0.1 μm p-channel MOS transistors     

Si/Si1-x-yGexCy/Si heterojunctionbipolar transistors

We report the first Si/Si_1-x-yGe_xC_y /Si n-p-n heterojunction bipolar transistors and the first electrical bandgap measurements of strained Si_1-x-yGe_x C_y on Si (100) substrates. The carbon compositions were measured by the shift between the Si_1-x-yGe_xC_y and Si_1-xGe_x X-ray diffraction peaks. The temperature dependence of the HBT collector current demonstrates that carbon causes a shift in bandgap of +26 meV/%C for germanium fractions of x=0.2 and x=0.25. These results show that carbon reduces the strain in Si_1-x Ge_x at a faster rate than it increases the bandgap (compared to reducing x in Si_1-xGe_x), so that a Si _1-x-yGe_xC_y film will have less strain than a Si_1-xGe_x film with the same bandgap     

High performance Si/Si1-xGex resonanttunneling diodes

Resonant tunneling diodes (RTDs) with strained i-Si_0.4Ge_0.6 potential barriers and a strained i-Si quantum well, all on a relaxed Si_0.8Ge_0.2 virtual substrate were successfully grown by ultra high vacuum compatible chemical vapor deposition and fabricated using standard Si processing methods. A large peak to valley current ratio of 2.9 and a peak current density of 4.3 kA/cm² at room temperature were recorded from pulsed and continuous dc current-voltage measurements, the highest reported values to date for Si/Si_1-xGe_x RTDs. These dc figures of merit and material system render such structures suitable and highly compatible with present high speed and low power Si/Si_1-xGe_x heterojunction field effect transistor based integrated circuits     

Silicide/strained Si1-xGex Schottky-barrierinfrared detectors

By employing a thin silicon sacrificial cap layer for silicide formation, the authors successfully demonstrated Pd₂Si/strained Si_1-xGe_x Schottky-barrier infrared detectors with extended cutoff wavelengths. The sacrificial silicon eliminates the segregation effects and Fermi level pinning which occur if the metal reacts directly with Si_1-x Ge_x alloy. The Schottky barrier height of the silicide/strained Si_1-xGe_x detector decreases with increasing Ge fraction, allowing for tuning of the detector's cutoff wavelength. The cutoff wavelength was extended beyond 8 μm in PtSi/Si _0.85Ge_0.15 detectors. It is shown that high quantum efficiency and near-ideal dark current can be obtained from these detectors     

The effects of base dopant outdiffusion and undopedSi1-xGex junction spacer layers in Si/Si1-xGex/Si heterojunction bipolar transistors

The effects of base dopant outdiffusion and nominally undoped Si _1-xGe_x spacer layers at the junction interfaces of Si/Si_1-xGe_x/Si n-p-n heterojunction bipolar transistors (HBTs) have been studied. It has been found that small amounts of boron outdiffusion from heavily doped bases of nonabrupt interfaces cause parasitic barriers in the conduction band, which drastically reduce the collector current enhancement in the HBTs. Undoped interface spacers can remove the parasitic barriers, resulting in a strongly improved collector current enhancement     

Improved low temperature characteristics of P-channel MOSFETs withSi1-xGex raised source and drain

P-channel metal-oxide-semiconductor field-effect transistors with Si_1-xGe_x raised source and drain (RSD) have been fabricated and further studied for low temperature applications. The Si _1-xGe_x RSD layer was selectively grown by ANELVA SRE-612 ultra-high vacuum chemical vapor deposition (UHVCVD) system. Compared to devices with conventional Si RSD, improved transconductance and specific contact resistance were obtained, and these improvements become even more dramatic with reducing channel length. Well-behaved short channel characteristics with reduced drain-induced barrier lowering (DIBL) and off-state leakage current are demonstrated on devices with 100 nm Si_1-xGe_x RSD, due to the resultant shallow junction and less implantation damage. Moreover, temperature measurements reveal that Si_1-xGe_x RSD devices show more dramatic improvement in device performance at low temperature (-50 °C) operation, which can be ascribed to the higher temperature sensitivity of the Si_1-xGe_x sheet resistance     

High temperature formed SiGe p-MOSFETs with good devicecharacteristics

We have used a simple process to fabricate Si_0.3Ge_0.7/Si p-MOSFETs. The Si_0.3Ge _0.7 is formed using deposited Ge followed by 950°C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. A hole mobility of 250 cm²/Vs is obtained from the Si_0.3Ge_0.7 p-MOSFET that is ~two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 Å Si_0.3Ge_0.7 thermal oxide grown at 1000°C has a high breakdown field of 15 MV/cm, low interface trap density (D_it) of 1.5×10¹¹ eV^-1 cm^-2, and low oxide charge of 7.2×10¹⁰ cm^-2. The source-drain junction leakage after implantation and 950°C RTA is also comparable with the Si counterpart     

Strained-$hbox{Si}_{1 - x}hbox{Ge}_{x}/hbox{Si}$ Band-to-Band Tunneling Transistors: Impact of Tunnel-Junction Germanium Composition and Doping Concentration on Switching Behavior

Strained pseudomorphic Si/Si_1-xGe_x/Si gate-controlled band-to-band tunneling (BTBT) devices have been analyzed with varying Ge composition up to 57% and p+ tunnel-junction (source) doping concentration in the 10¹⁹-10²⁰ cm^-3 range. Measurements show the impact of these parameters on the transfer and output characteristics. Measurements are compared to simulations using a nonlocal BTBT model to analyze the mechanisms of device operation and to understand the impact of these parameters on the device switching behavior. The measured characteristics are consistent with simulation analysis that shows a reduction in energy barrier for tunneling (E_geff) and a reduction in tunneling distance with increasing Ge composition and source doping concentration. Increases in the pseudomorphic layer Ge content and doping concentration of the tunnel junction produce large improvements in the measured switching-behavior characteristics (I_on, slope, turn-on voltages, and sharpness of turn-on as a function of V_ds). Simulations are also performed to project the potential performance of more optimized structures that may be suitable for extremely low power applications (V_dd < 0.4 V).     

Suppression of boron penetration in p-channel MOSFETs usingpolycrystalline Si1-x-yGexCy gatelayers

Boron penetration through thin gate oxides in p-channel MOSFETs with heavily boron-doped gates causes undesirable positive threshold voltage shifts. P-channel MOSFETs with polycrystalline Si_1-x-yGe_xC_y gate layers at the gate-oxide interface show substantially reduced boron penetration and increased threshold voltage stability compared to devices with all poly Si gates or with poly Si_1-xGe gate layers. Boron accumulates in the poly Si_1-x-yGe_xC_y layers in the gate, with less boron entering the gate oxide and substrate. The boron in the poly Si_1-x-yGe_xC_y appears to be electrically active, providing similar device performance compared to the poly Si or poly Si_1-xGe_x gated devices     

Characteristics of p- and n-channelpoly-Si/Si1-xGex/Si sandwiched conductivitymodulated thin-film transistors

Both p- and n-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistors (CMTFTs) are demonstrated and experimentally characterized. The transistors use a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide a high on-state current. Results show that the transistors provide a high on-state current as well as a low leakage current compared to those of conventional offset drain TFTs. The p- and n-channel CMTFTs can be combined to form CMOS drivers, which are very suitable for use in low temperature large area electronic systems on glass applications     

A gate-quality dielectric system for SiGe metal-oxide-semiconductordevices

The authors present a high-quality dielectric system for use with Si_1-xGe_x alloys. The system employs plasma-enhanced chemical vapor deposited (PECVD) SiO₂ on a thin (6-8-nm) layer of pure silicon grown epitaxially on the Si_1-x Ge_x layer. The buffer layer and the deposited oxide prevent the accumulation of Ge at the oxide-semiconductor interface and thus keep the interface state density within acceptable limits. The Si cap layer leads to a sequential turn-on of the Si_1-xGe_x channel and the Si cap channel as is clearly observed in the low-temperature C-V curves. The authors show that this dual-channel structure can be designed to suppress the parasitic Si cap channel. The MOS capacitors are also used to extract valence-band offsets     

Strain-controlled Si-Ge modulation-doped FET with ultrahigh holemobility

A novel modulation-doped field effect transistor (MODFET) with a strain-controlled Ge channel, p-Si_0.5Ge_0.5/Ge/Si _1-xGe_x, is fabricated by molecular beam epitaxy (MBE). In order to enlarge the valence-band discontinuity, strain at the p-Si_0.5Ge_0.5/Ge interface is controlled by changing the composition of the relaxed Si_1-xGe_x layer. For this MODFET operated at around 77 K, an ultrahigh-field-effect mobility of ~9000 cm²/V-s is obtained     

A deep submicron Si1-xGex/Si vertical PMOSFETfabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si_1-xGe_x channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si_1-xGe_x /Si transistors can be fabricated with channel lengths below 0.2 μm without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si_1-xGe_x over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's     

Electrical properties of heavily doped polycrystallinesilicon-germanium films

The electrical properties of polycrystalline silicon-germanium (poly-Si_1-xGe_x) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented. The resistivity of heavily doped p-type (P⁺) poly-Si_1-x Ge_x is much lower than that of comparably doped poly-Si, because higher levels of boron activation and higher hole mobilities are achieved in poly-Si_1-xGe_x. The resistivity of heavily doped n-type (N⁺) poly-S_1-xGe_x is similar to that of comparably doped poly-Si for x<0.45; however, it is considerably higher for larger Ge mole fractions due to significant reductions in phosphorus activation. Lower temperatures (~500°C), as well as lower implant doses, are sufficient to achieve low resistivities in boron-implanted poly-Si_1-xGe_x films, compared to poly-Si films. The work function of P⁺ poly-Si_1-xGe_x decreases significantly (by up to ~0.4 Volts), whereas the work function of N⁺ poly-Si_1-xGe_x decreases only slightly, as Ge content is increased. Estimates of the energy bandgap of poly-Si_1-xGe_x show a reduction (relative to the bandgap of poly-Si) similar to that observed for unstrained single-crystalline Si_1-xGe_x for a 26% Ge film, and a reduction closer to that observed for strained single-crystalline Si _1-xGe_x for a 56% Ge film. The electrical properties of poly-Si_1-xGe_x make it a potentially favorable alternative to poly-Si for P⁺ gate-material applications in metal-oxide-semiconductor technologies and also for p-channel thin-film transistor applications