Digital Signature Proposal for Mixed-Signal Circuits

A new Built-In Self-Test structure, based on the information provided by the XY-operation (Lissajous curves) is introduced in this paper. A Digital Signature is obtained which is used to discriminate catastrophic as well as parametric defects. High Fault Coverage is achieved when applying the proposed BIST on an ITC'97 benchmark circuit where 92% of the catastrophic defects and 87.5% of the parametric defects analyzed produced digital signatures clearly distinguishable from the golden signature.     

Integrated Design and Test of Mixed-Signal Circuits

In this paper, the integration of design and test flows for mixed-signal circuits is discussed. The aim is to decrease test generation and debugging costs and time-to-market for the analogue blocks in mixed-signal circuits. A tool developed in order to automate the data sharing between design and test environments is described and the functionality of this tool is explained. The generation of a test plan consists of the selection of the separate test functions and addition of commands for control signal generation and tester routing. The usage of design data for each of these functions is explained and the tool is evaluated in the design and testing of a mixed-signal demonstrator circuit. Results from this experience are discussed.     

Process Deviations and Spot Defects: Two Aspects of Test and Test Development for Mixed-Signal Circuits

By their nature, mixed-signal circuits have to be tested for both structural integrity and parametric performance. For the example of data converters we review test pattern selection strategies geared towards structural and performance testing. We introduce a novel test pattern selection strategy that merges both objectives, and by that we achieve a significant reduction in the size of the set of test patterns applied on the production line.     

模拟电路的振荡测试技术

集成电路设计和制造技术的发展给电路测试带来了巨大的挑战,其中模拟电路的测试是电路测试的难点.目前在这一领域有许多致力于降低测试难度,节约测试成本的研究.介绍了一种称为"振荡测试"的模拟电路测试技术,从振荡电路的构造、测试响应的测量和分析等方面综述了振荡测试技术的研究现状,同时总结了振荡测试技术的优点,分析了当前存在的局限性,并对将来的发展进行了展望.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

用于数模混合电路中ADC测试的IP核设计

针对片上系统(SoC)中模数转换器(ADC)的测试,提出了一种测试IP核结构。IP核主要由模拟信号源、换位器和标准数模转换器(DAC)等组成,能够根据设计者不同的需求选择不同的测试方案。针对ADC的低位呆滞故障以及跳变故障的检测,提出了一种新的检测方法,解决了ADC低位故障检测困难的问题,该方法还可以用于对电压稳定度以及噪声的测量。通过对IP核数字电路部分的设计与仿真,证明IP核是可行的。     

Behavioral Modeling and Simulation of Mixed-Signal System-on-a-Chip using SystemC

We describe an efficient software framework for rapid behavioral modeling and simulation of mixed-signalSystem-on-a-Chip (SoC). The framework is based on the SystemC C++ class libraries and has beenproven to be a very effective tool for exploring different system-level architectures in the early stages of thedesign process. We also present the results of three case studies where we have used the framework: a 10-bit, 60Mega-sample/s pipelined ADC, 14-bit, 100 Mega-sample/s pipelined ADC with background calibration, and aCMOS camera-on-a-chip.     

Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits

A traditional specification-based core-level test method is no longer attractive in testing deeply embedded analog and mixed-signal circuits due to limited accessibility and resource issues. In order to overcome such difficulties, loopback testing has been considered as a promising solution when circuits include data conversion units; however its widespread adoption has been hindered due to fault masking, which may cause serious yield loss and test escape. The combination of seriously degraded components in a signal path and overqualified components in another signal path, may result in the overall performance of the loopback path being completely fault-free. This paper presents an efficient loopback test methodology which provides test accuracy equivalent to a traditional specification-based test. In our approach, a traditional loopback scheme is re-configured with an analog filter and an adder implemented on a Device Interface Board (DIB), and a multiple tone input is applied to the DUTs. The outcome of the proposed test is a set of performance parameters, allowing the evaluation of DUTs with respect to its specification, and efficient guidance of a self-repair mechanism. The mathematical analysis for the fault masking problem, based on linearity and noise parameters, is provided. In addition, various design parameters which may impact the accuracy of the proposed method are investigated. Both simulation and hardware measurements are presented to validate the proposed technique.     

一种实现数模混合电路中ADC测试的BIST结构

针对模／数转换器(ADC)数模混合电路的测试问题，提出了一种内建自测试(BIST)的测试结构，分析并给出了如何利用该结构计算ADC的静态参数和信噪比参数。利用该方法，既可以利用柱状图快速测试ADC的静态参数，又可利用FFT技术实现对ADC频域参数的分析，使得测试电路简单、紧凑和有效。     

一种数模混合SoC的系统级后仿真验证平台

针对传统大规模数模混合SoC后仿真验证过慢的问题,提出了一种数模混合SoC系统级后仿真验证平台。该平台充分利用主流EDA工具,在传统Verilog-cdl后仿真验证平台的基础上,将原本网表中耗时长的模块用Verilog模型替换,使用Verilog-cdl-Verilog仿真方法,明显加快了仿真速度。从验证环境搭建、系统脚本设计、仿真接口设计三个方面详述了仿真平台的设计流程,并通过指令集功能的仿真实现,证明了平台的可行性和可靠性。该验证平台有助于缩短大规模数模混合SoC的开发周期。     

基于SAT的组合电路自动测试向量生成

实现了基于可满足性(SAT)求解的方法,以解决固定型和时延故障的自动测试向量生成问题.详细讨论了如何利用电路的拓扑结构以及从ATPG到合取范式(CNF)的编码方法.CNF被输入到一个高效的SAT求解器zchaff中求解.在ISCAS85测试实例中验证了该算法的有效性.     

Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits

We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: (1) fault-list and test-set partitioning, and (2) vector re-ordering. Typically, the first few vectors of a test set detect a large number of faults. The remaining vectors usually constitute a large fraction of the test set, but these vectors are included to detect relatively few hard faults. We show that significant compaction can still be achieved by partitioning faults into hard and easy faults, and compaction is performed only for the hard faults. This significantly reduces the computational cost for static test set compaction without affecting quality of compaction. The second key idea re-orders vectors in a test set by moving sequences that detect hard faults to the beginning of the test set. Fault simulation of the newly concatenated re-ordered test set results in the omission of several vectors so that the compact test set is smaller than the original test set. Experiments on several ISCAS 89 sequential benchmark circuits and large production circuits show that our compaction procedure yields significant test set reductions in low execution times.     

Low Cost On-Line Testing Strategy for RF Circuits

This work proposes the use of a simple 1-bit digitizer as an analog block observer, in order to enable the implementation of on-line test strategies for RF analog circuits in the System-on-Chip environment. The main advantages of using a simple digitizer for RF circuits are related to the increased observability of the RF signal path and minimum RF signal degradation, as neither reconfiguration of the signal path nor variable load for the analog RF circuit are introduced. As an additional advantage, the same digitizer can be used to implement BIST strategies, if required. The feasibility of using a 1-bit digitizer for the test of analog signals has already been presented in the literature for low frequency linear analog systems. This paper discusses the implementation of an on-line test strategy for analog RF circuits in the SoC environment, and presents new results for on-line RF testing. Moreover, we also provide detailed analysis regarding the overhead of the test strategy implementation. Experimental results illustrate the feasibility of the proposed technique.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A. Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in VLSI Architecture and is also thesis director. His main research interests are integrated circuit architecture, embedded systems, signal processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.     

Multi-VDD Testing for Analog Circuits

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, all transistors are forced into various regions of operation. This has as advantage that the detection of faults is done for multiple supply voltages and corresponding quiescent currents, enhancing in this form the detectability of faults. We found that this method of structural testing yields fault coverage results comparable to functional RF tests making it a potential and attractive technique for production wafer testing due to its low cost, low testing times and low frequency requirements.José Pineda de Gyvez received the Ph.D. degree from the Eindhoven University of Technology. He is currently a principal scientist at Philips Research Laboratories, The Netherlands. Dr. Pineda was Associate Editor in IEEE Transactions on Circuits and Systems Part I and also Associate Editor for Technology in IEEE Transactions on Semiconductor Manufacturing. His research interests are in the general areas of design for manufacturability and analog signal processing.Guido Gronthoud received the electrical engineering degree from the Delft University in 1975. From 1976 to 1980 he worked at the Delft University on the design of Microwave systems. From 1980 he works with Philips. He has been working in the fields of circuit simulation and modelling for IC designs, CAD development for PCB design and electronic circuits and systems reliability. Since 1998 he is working on test innovation of digital and mixed-signal circuits. His interests are Defect Oriented Test, fault modeling and Process Related Test. He has authored and co-authored technical papers.     

混合信号电子产品的自动测试技术

电子产品微型化使自动测试成为必然,而边界扫描技术则使自动测试成为可能。文章分析了1149.4和1149.1标准的测试访问端口,以及测试逻辑结构和测试协议的异同,提出了模拟边界扫描单元ABM和数字边界扫描单元DBM的行为模型;在此基础上,详细阐述了两个标准在混合信号电子产品自动测试中的综合应用方法;最后,以典型的混合信号电路D/A转换器为例,对两个标准的综合应用进行了仿真验证。     

用于混合信号系统的模/数分块一体化测试技术

为了解决混合信号系统中三种模块:模拟、数字和存储器接口之间存在的难以测试的问题,讨论了一种模拟/数字一体化的测试技术,包括三种模块的测试方法、系统测试的分块、可测性设计(DFT)、自测试策略和方案等,并说明了互连测试和准静态电流IDDQ测试法可为该项新技术提供有效的解决方案.     

Structural Fault Based Specification Reduction for Testing Analog Circuits

Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.     

Fault Simulation for Analog Circuits Under Parameter Variations

Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4.     

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits

In this paper, we propose a controller resynthesis technique to enhance the testability of register-transfer level (RTL) controller/data path circuits. Our technique exploits the fact that the control signals in an RTL implementation are don't cares under certain states/conditions. We make an effective use of the don't care information in the controller specification to improve the overall testability (better fault coverage and shorter test generation time). If the don't care information in the controller specification leaves little scope for respecification, we add control vectors to the controller to enhance the testability. Experimental results with example benchmarks show an average increase in testability of 9% with a 3–4 fold decrease in test generation time for the modified implementation. The area, delay and power overheads incurred for testability are very low. The average area overhead is 0.4%, and the average power overhead is 4.6%. There was no delay overhead due to this technique in most of the cases.     

Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.