Multiband RF-sampling receiver front-end with on-chip testability in 0.13 μm CMOS

In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5–6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 μm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 2× subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.     

A 1.1 V 6.2 mW,wideband RF front-end for 0 dBm blocker tolerant receivers in 90 nm CMOS

This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90 nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves a high linearity in a wide band (0.5–6 GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below −8.8 dB up to 6 GHz. The measured single sideband noise figure at an LO frequency of 3 GHz and an IF of 10 MHz is 6.25 dB. The front-end achieves a voltage conversion gain of 4.5 dB at 1 GHz with 3 dB bandwidth of more than 6 GHz. The measured input referred 1 dB compression point is +1.5 dBm while the IIP3 is +11.73 dBm and the IIP2 is +26.23 dBm respectively at an LO frequency of 2 GHz. The RF front-end consumes 6.2 mW from a 1.1 V supply with an active chip area of 0.0856 mm².     

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm². The receiver achieves S11 input matching below ?10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.     

Inverter-based 1 V analog front-end amplifiers in 90 nm CMOS for medical ultrasound imaging

In this paper, we present the design and experimental evaluation of 1 V analog front-end amplifiers designed in 90 nm CMOS technology for capacitive micro-machined ultrasound transducers (CMUTs) for medical ultrasound imaging systems. We propose two front-end amplifier topologies based on an inverter-based cascode amplifier; the first is a continuous time amplifier and the second is a charge sampling amplifier (CSA). The proposed front-end amplifiers are designed to amplify the signals from CMUTs in the frequency bandwidth from 15 to 45 MHz with a centre frequency of 30 MHz. From the measurements, the continuous time single-ended transimpedance amplifier achieves a voltage gain of 19 dB, an output noise power spectral density of 0.042 (μV)/SQRT(Hz) at a centre-frequency of 30 MHz, and a total harmonic distortion of −23 dB at 450 mV p–p output voltage at 30 MHz input signal frequency. It draws only 598 μA per amplifier from a 1 V power supply. Its area measured only about 32 μm × 32 μm per amplifier. On the other hand, a sampling based front-end amplifier [CSA] achieves a transfer gain of 17.4 dB at an input signal frequency of 30 MHz and an upper 3 dB cut-off frequency of 46 MHz at a sampling clock frequency of 100 MHz. It consumes 586 μA per amplifier from a 1 V power supply and achieves a signal-to-noise (SNR) ratio of 45.7 dB with a peak-to-peak output signal amplitude of 500 mV at a sampling frequency of 100 MHz. It occupies an area of 1470.2 μm² (which is equivalent to 38 μm × 38 μm), which also includes the area of the switches for the CSA that will be used for the single CMUT element.     

Design of a wideband low-power continuous-time ΣΔ modulator in 90 nm CMOS technology

The design of a wideband low-power continuous-time (CT) sigma-delta modulator (ΣΔM) is presented. At system level, an improved direct design method is used which allows direct design of the modulator in continuous-time domain. The modulator employs a low-latency flash quantizer to minimize excess loop delay. Digital-to-analog (DAC) trimming technique is used to correct the quantizer offset error, which permits minimum-sized transistors to be used for fast and low-power operation. The modulator is designed in 90 nm CMOS process with single 1.0-V power supply. It achieves a dynamic range (DR) of 75 dB and a signal-to-noise-and-distortion-ratio (SNDR) of 70 dB in a 25 MHz signal bandwidth with 16.4 mW power dissipation.     

An area-efficient maximum-ratio-combining diversity receiver in 90 nm CMOS for free-space optical links

This paper presents a low-power imaging diversity front-end receiver employing the maximum-ratio-combining algorithm for free-space optical communication. It consists of seven signal channels and an output stage, each channel has a front-end transimpedance amplifier, a signal-to-noise ratio (SNR) estimator and a variable gain amplifier (VGA). The imaging receiver circuit was implemented in a 90 nm CMOS process. The maximum-ratio weighting is achieved with the SNR estimator and variable gain amplifier (VGA), which provides the signal with a gain proportional to the signal amplitude. The maximum ratio combining feature was demonstrated with two channels driven by photodiode emulation circuits for electrical characterization. The power dissipation for the whole chip is 43 mW from a single 1.2 V supply.     

A 65 nm CMOS LNA for Bolometer Application

Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer’s pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.     

An 8-bit 208 MS/s SAR ADC in 65 nm CMOS

An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a significant power saving over the conventional one. Moreover, the proposed architecture relaxes the settling time of DAC and subsequently improves the conversion rate. The ADC has been simulated in SMIC 65 nm 1.2 V CMOS technology. At a 1.2-V supply and 208 MS/s, the ADC consumes 2.7 mW and achieves an SNDR of 49.6 dB, an SFDR of 61.0 dB with 100 MHz inputs.     

A 6 mW 750 MHz anti-aliasing filter for receiver analog front-end

A low power high speed continuous-time filter for receiver application in standard 90 nm CMOS process is presented. A biquad cell based on the open-loop topology is implemented. Besides, a differential voltage buffer with additional gain boost, high linear voltage-to-voltage conversion and low output impedance is introduced. In this work, a fourth-order filter is implemented. Simulation results show the 750 MHz cutoff frequency with less than ?50 dB IM3 for a 300 mVpp input. The power consumption for this filter is 6 mW at a 1.2-V supply.     

A 20 Gbps inductorless CMOS optical receiver for short-distance VCSEL-based 850 nm optical links

This paper presents a circuit design and experimental results for a 20 Gbps CMOS inductorless optical receiver, a transimpedance amplifier (TIA) and a limiting amplifier, for a vertical-cavity surface emitting laser based 850 nm optical link. The proposed optical receiver apply a power supply noise canceling technique, an additional path from the power supply to the TIA output to generate a reversed phase signal that reduces the power supply noise, and bandwidth enhancement circuit design that dose not require internal inductors. The simulation results shows a power supply rejection ratio of ?96.6 dB at 10 MHz, a total gain of $82.8\,\hbox{dB}\Upomega$ and a ?3 dB bandwidth of 15.5 GHz. A test chip fabricated in 90 nm CMOS technology and demonstrated with a PIN photo-diode, a bandwidth of 17 GHz and a responsibility of 0.53 A/W. The measurement results show a 25 % eye opening and an input sensitivity of ?7.1 dBm at a bit error rate of 10^?12 with a 2⁹ ? 1 pseudo-random test pattern at 20 Gbps. The core circuit of the optical receiver occupies only an area of 0.02 mm².     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

High-speed single-channel SAR ADC with a novel control logic in 65 nm CMOS

This paper presents an 8-bit 320 MS/s single-channel successive approximation register (SAR) analog-to-digital converter (ADC) with low power consumption. Through a procedure of splitting all the most significant bit (MSB) capacitors except the least significant bit (LSB) capacitor into two equal sub-capacitors and reusing the terminal capacitor, the average switching energy and total capacitance can be reduced by about 87 and 50% respectively compared to the conventional procedure. Meanwhile, high-speed operation can be achieved by using a novel SAR control logic featuring efficient hardware cost and small critical path delay. In addition, this paper analyzes how to obtain the value of the unit capacitance which exhibits trade-offs between conversion rate, power consumption and linearity performance. The SAR ADC is simulated in 65 nm CMOS technology. It can achieve 48.63 dB SNDR, 63.61 dB SFDR at a supply voltage of 1.2 V and sampling frequency of 320 MS/s for near-Nyquist input, consuming 2.59 mW of power and with a FoM of 37 fJ/conversion-step.     

A 7-bit 40 MS/s single-ended asynchronous SAR ADC in 65 nm CMOS

This paper presents a 7-bit 40 MS/s single-ended asynchronous SAR ADC intended for in-probe use in medical applications, which requires small area and good power efficiency. A single-ended architecture is proposed for a moderate resolution for its simplicity. Together with a double reference technique, the architecture reduces the area of the technology-limited large capacitors. The speed is optimized by an asymmetric delay line embedded in the asynchronous digital logic, enabling a sampling frequency of 40 MS/s. The prototype is fabricated in a 65 nm CMOS technology. Measurement shows that at 1 V supply and 40 MS/s, the ADC achieves an SNDR of 39.73 dB and an ENOB of 6.3 bit, while consuming 298.6 µW, resulting in an energy efficiency of 94.74 fJ/conversion-step. The core circuit layout only occupies 0.017 mm².     

An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm². The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm² fJ/conversion-step.