The charge-coupled RAM cell concept

A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAM's.     

The charge-coupled RAM cell concept

A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAM's.     

Charge transfer in overlapping gate charge-coupled devices

A detailed numerical simulation of the free charge transfer in overlapped gate charge-coupled devices is presented. The transport are analyzed in terms of thermal diffusion, self-induced fields, and fringing fields under all the relevant electrodes and interelectrode regions with time-varying gate potentials. The results of the charge transfer with different clocking schemes and clocking waveforms are presented. The dependence of the stages of the charge transfer on the device parameters are discussed in detail. A lumped-circuit model of CCD that could be used to obtain the charge-transfer characteristics with various clocking waveforms is also presented.     

Charge transfer in charge-coupled devices in the presence of interface states

The transfer of charge from under a gate of a three-phase surface-channel charge-coupled device is analysed in terms of thermal diffusion, charge-gradient induced drift, fringing field drift, and interface state trapping. A method based on a piecewise approximation for the emission rate from interface states is proposed and used to derive the single-transfer characteristics in the presence of interface traps. It is shown that the emission rate exhibits a marked spatial dependence, which is a function of both fringing field profile and interface state density. It is also concluded that trapping effects are a strong limitation on the transfer efficiencies attainable in surface-channel charge-coupled devices at low and moderate frequencies.     

Numerical studies of the charge capacity of surface-channel charge-coupled devices

The signal charge distribution and electrostatic potential of a three-phase charge-coupled device are found in a self-consistent manner. The length of the center gate is varied to simulate processing variations and their effect on charge capacity. Potential profiles are shown for a variety of charge levels and gate dimensions. The full-well charge capacity scales with the geometric gate length (down to at least 1 μm) in our example, although the partly filled charge level does not scale. A simple one-dimensional estimate of the full-well capacity is shown to be accurate.     

The behavior of the continuously charge-coupled random-access memory (C/SUP 3/RAM)

This paper describes a new random-access memory which achieves a bit density comparable to CCD memories. This memory uses as storage elements single-transistor memory cells which are connected to a common bit line. The bit line is implemented with an MOS transmission line, which makes possible an almost lossless charge transport from the single-transistor memory cell to the read/write amplifier. Due to the almost lossless charge transport, the storage capacitance can be reduced and the bit density increased. The expected performance of a 32-kbit memory has been derived.     

Calculation of charge-handling capacity in twin-layer peristaltic charge-coupled devices

Charge-handling capacity is an important parameter in determining the dynamic range of a charge-coupled device (CCD). Based on depletion approximation, a one-dimensional charge storage capacity calculation is given for an n-channel twin-layer peristaltic CCD with constant layer dopings. The charge capacity is found to increase linearly with surface layer implant dose for lower level implant and saturate at higher level implant.     

Fault tolerance techniques for high capacity RAM

As the complexity and size of the embedded memories keep increasing, improving the yield of embedded memories is the key step toward improving the overall chip yield of a SOC design. The most well known way to improve the memory yield is by using redundant elements to replace the faulty cells. However, the repair efficiency mainly depends on the type, and the amount of redundancy; and on the redundancy analysis algorithms. Therefore, new types of redundancy based on divided bit-line (DBL), and divided word-line (DWL) techniques are proposed in this work. A memory column (row), including the redundant column (row), is partitioned into column blocks (row blocks), respectively. A row/column block is used as the basic replacement element instead of a row/column for the traditional approaches. Based on the new types of redundancy, three types of fault-tolerant memory (FTM) systems are also proposed. If a redundant row/column block is used as the basic replacement element, then the row block-based FTM (RBFTM)/column block-based (CBFTM) system is used. If both the DWL, and DBL techniques are implemented onto a memory chip, then the hybrid FTM (HFTM) system is achieved. The storage and remapping of faulty addresses can be implemented with a CAM (content addressable memory) block. To achieving better repair efficiency, a novel hybrid block-repair (HBR) algorithm is also proposed. This algorithm is suitable for hardware implementation with negligible overhead. For the HFTM system, the hardware overheads are less than 0.65%, and 0.7% for 64-Kbit SRAM, and 8-Mbit DRAM, respectively. Moreover, the repair rate can be improved significantly. Experimental results show that our approaches can improve the memory fabrication yield significantly. The characteristics of low power and fast access time of DBL and DWL techniques are also preserved.     

A theoretical and experimental analysis of the buried-source VMOS dynamic RAM cell

The buried-source dynamic RAM cell combines a VMOS transistor (VMOST) and a buried junction capacitor to make a one-transistor cell (1TC) providing large storage capacitance, long charge retention, and high density. The threshold voltage, breakdown voltage, and weak inversion current for the forward and reverse modes of operation of the VMOST and the junction capacitance are experimentally related to the nonuniform doping profile of the channel. Equations are developed for the VMOST short-channel threshold voltage and storage capacity of the cell. The charge capacity (per unit of cell area) of the buried-source cell is calculated to be 2.5 times that of the conventional 1TC cell. The cell charge retention time was measured at more than 1 s at 100°C, proving operation of the device as a dynamic memory element. The technology is capable of producing an 80-µm²cell using 4-µm minimum features, no cell contacts, and a single level of interconnect.     

The collector-coupled static RAM cell

The collector-coupled static RAM cell uses a schottky collector transistor switch with merged vertical n-p-n load. The cell is constructed with two dual Schottky collector transistors and one merged dual collector n-p-n transistor. It has been fabricated in an infant oxide isolated bipolar technology and bistability has been demonstrated over four orders of magnitude in cell current (10 nA相似文献   

The Hi-C RAM cell concept

This paper addresses a new MOS high-capacity dynamic RAM cell concept called the high capacity (Hi-C) RAM cell. This cell combines the charge-coupled RAM cell with the one-transistor (1-T) or double-level polysilicon (DP) structure, and its operation is identical to that of conventional dynamic RAM cells. A charge-capacity analysis was undertaken which indicates that the Hi-C cell has a charge storage capacity per unit area 50-100 percent greater than that of the regular 1-T or DP cells. It is also expected to have a leakage current lower than that of the 1-T and DP cells. Results of measurements on the first test structures show a 45-80-percent increase in charge capacity and up to 3× reduction in leakage current. In addition, the implant doses can be conveniently chosen so that the charge capacity of the Hi-C cell is maximized and independent of the n-type implant dose in the storage region. This is important regarding manufacturability. This new cell structure represents a significant breakthrough in increased charge capacity and decreased leakage current which should very favorably impact dynamic RAM packing density.     

Charge-control method of charge-coupled device transfer analysis

An analysis of charge transfer based on the "charge-control" approach has been made for charge-coupled devices (CCD's). A general closed-form equation for the charge transfer efficiency has been obtained that includes the major mechanisms of 1) charge-gradient induced drift, 2) thermal diffusion, 3) an external fringing field, and 4) charge loss due to traps or recombination. When the charge loss and fringing field terms are neglected, the results are in close agreement with the numerical solutions by Strain and Schryer. With the fringing field term included, the closed-form solution compares well with the numerical results by Heller, Chang, and Lo. The effect of charge loss on the transfer efficiency is studied and the temperature dependence of the efficiency, including the temperature dependent surface mobility, is discussed. The effect of a "fat" zero on the diminution of a digital one is discussed with and without charge loss to surface states. It is believed that the charge-control approach not only simplifies the mathematics involved, but also provides practical charge-coupled device and circuit design guides.     

Static RAM cell for ternary logic

A novel CMOS static RAM cell for ternary logic systems is described. This cell is based on the lambda diode. The operation of the cell has been simulated using the SPICE 2G program. The results of the simulation are given.     

Numerical methods for the charge transfer analysis of charge-coupled devices

Charge transfer phenomenon in charge-coupled devices is characterized by a nonlinear partial differential equation of the parabolic type, usually coupled with a very undesirable nonlinear boundary condition. In this study, special treatment is made to the boundaries such that the nonlinearity of the boundary condition does not appear in the final calculation. Four possible finite-difference schemes for this problem are described and results compared. Through numerical experimentations, the linearized Crank-Nicolson scheme is proved to exhibit superior quality and is recommended for the exclusive use in studying the charge transfer phenomenon in CCD. Using this scheme, the charge transfer phenomenon of a two phase overlapping gate CCD has been studied and numerical results are presented. Special emphasis is directed toward the relative importance of the self-induced drift, fringing field drift and thermal diffusion currents. Also, the usefulness of approximating a spatial fringing field pattern by a constant value to the charge transfer phenomenon is discussed.     

An experimental study of the BO-MOS dynamic RAM cell

A novel structure of a one-transistor dynamic MOS RAM cell is developed for higher integration. The buried-oxide MOS (BO-MOS) RAM cell consists of a planar MOSFET transfer gate and a storage capacitor of buried N⁺diffusion. This three-dimensional structure results in a cell size of6F^{2}with a minimum feature sizeFand the large capacitance ratio of storage to bit-line which is about 4 times that of a typical commercial 64-kbit RAM cell. The soft-error-immunity cell structure is also taken into account. Static device characteristics of the planar MOSFET transfer gate built on an epitaxial layer and the buried storage capacitance are investigated relating to doses of boron implantation to the channel and substrate. Dynamic WRITE/READ operations are performed with an experimental 4 × 10 cell array implemented withF = 4-µm features. The technology offers the possibilities of a high density dynamic MOS RAM with a single poly-Si process.     

Two-dimensional transient analysis of a buried-channel charge-coupled device

An effective method of two-dimensional transient analysis of potential and charge carrier distribution in a buried-channel charge-coupled device (BCCD) operating in storage and transfer modes has been developed with the aid of the finite Fourier transform (FET) technique.The effect of different clocking schemes on charge carrier transfer inefficiency and charge handling capacity are examined and discussed using the method developed. It is also shown that, for a BCCD operating in the storage mode, two-dimensional analysis indicates that the charge handling capacity determined by one-dimensional analysis can result in overestimation, which is misleading.     

A survey of high-density dynamic RAM cell concepts

The performance capabilities of a variety of dynamic RAM cell concepts proposed in recent years are compared to the industry standard one-transistor cell. The new concepts are divided into three categories. The lateral charge sensing cells such as the Charge-Coupled cell, Hi-C cell, Merged-Charge cell, and Stacked-Capacitor cell. Vertical cells such as VMOS, the Punchthrough Isolated, and the Buried-Bit-Line cell which make use of the third dimension to achieve higher density. The Stratified-Charge cell and Taper-Isolated cell use current sensing of a dynamic change in the threshold voltage of a buried-channel transistor. The various cells were fabricated and compared on the basis of signal size, leakage rates, packing density, and fabrication and operational complexity. An overall figure of merit for a dRAM cell is suggested which combines all three considerations. Based on the cell concepts reported to date and this figure of merit, the Stacked-Capacitor, VMOS, and Punchthrough-Isolated cells ate the most promising charge storage cells. The Taper-Isolated cell, however, is shown to have significant overall advantage compared to the charge storage cells.     

Theoretical analysis of charge transfer in thin-film charge-coupled devices

The charge-transfer process in thin-film charge-coupled devices made from, e.g. hydrogenated amorphous silicon (a-Si:H) is analysed mathematically. This analysis considers the spatial coordinate in the transfer direction explicitly, while, by making use of the thin film feature, it is formulated as a quasi 1-D problem. In agreement with previous work, it is found that the thickness of the active layer influences the deleterious effect of localized states. However, it is shown that for a realistic distribution of localized states in undoped a-Si:H, the transfer inefficiency can approach the ultimate trap-free case when the active layer thickness is reduced to below 0.1 μm. Such a device can be operated at a frequency of slightly less than 100 kHz.     

Charge handling capacity in charge coupled devices

In analog signal processing applications, the charge handling capacity of a charge coupled device (CCD) is an important parameter that determines the dynamic range. In this paper, approximate expressions for the signal handling capacity for surface-channel and buried-channel CCD's are derived and compared. The upper limit for the buried-channel charge capacity is imposed by the onset of surface electron accumulation.     

A latch-up-free CMOS RAM cell with well-source structure

A well-source structure that provides a design goal for enhancing latchup immunity in VLSI full CMOS RAM without additional fabrication steps and performance degradations is described. The key features are to supply a cell power charge from n-well and to arrange cell power lines in such a way as to prevent the parasitic p-n-p transistor from turning on. The availability of the well-source structure was examined by using test devices and 64-kb full-CMOS RAM chips fabricated with 2-/spl mu/m n-well technology. No latchup was induced in a cell array portion with the well-source structure. Sixfold increase in the latchup immunity was observed for the RAM with the well-source structure versus the RAM with the conventional cell design.