通信电子电路中二极管的频率变换功能

晶体二极管是一种简单实用的通信电子器件。通过分析其单向导电性与压控电容特性,认为在通信电子电路中使用晶体二极管主要有三种典型的频率变换功能,即在振幅检波电路中的整流作用,在混频电路中的开关作用以及在调频电路中的变容作用。     

基于主方程单电子晶体管模拟新方法

在对单电子晶体管主方程模型及主方程的解法详细的分析的基础上,把单电子晶体管主方程模型和SP ICE的ABM功能结合,提出了基于主方程的单电子晶体管SP ICE模型。该模型由一个非线性电压控制电流源、非线性电压控制电压源、电容构成。并利用该模型对单电子晶体管V-I特性进行SP ICE模拟,同直接解主方程解法相比,仿真结果表明该模型具有合理的精确度。     

Reply to Comments on “Cut-off Characteristics of a Cylindrical Magnetron”

A new circuit for generation of triangle/square waveform is described. The circuit uses a linear pulse amplifier, a clipper and a differentiating network, consisting of a capacitance and a FET behaving as a voltage-controlled resistor. The circuit covers a wide frequency range and the variation of frequency with the control voltage is fairly linear.     

压控晶体振荡器的设计

简要介绍了压控晶体振荡器的工作原理,说明了晶体谐振器与变容二极管在压控晶振中起的关键作用,以及如何根据实际情况选择合适的晶体谐振器和变容二极管以实现相应的压控频偏和压控线性。介绍了几种可以实现负斜率压控特性和改善压控对称性的压控电路。     

Optical Receiver With Widely Tunable Sensitivity in BiCMOS Technology

A monolithically integrated optical receiver with voltage-controlled sensitivity in 0.6-m BiCMOS technology is presented. The transimpedance variations are achieved by varying the control voltage of the voltage-controlled resistor changing its equivalent resistance. The optical receiver design is based on a P-intrinsic-N photodiode and on a mixed current-mode and voltage-mode approach, by using a current conveyor and a voltage amplifier. Thanks to the current-mode signal processing, the bandwidth of the optical receiver is independent of the photodiode capacitance. A linearity error smaller than 2.92%, a sensitivity dynamic range of 83.2 (38.4 dB), an offset voltage smaller than 0.56 mV, a power consumption less than 4.7 mW, and a bandwidth up to 205.5 MHz are achieved.     

A New Monolithic Voltage-Controlled Oscillator

A new monolithic voltage-controlled oscillator exploiting a previously reported monolithic variable capacitance cell is presented. With a 2.3 volt swing in control voltage, the oscillator generates a sinusoidal output signal at frequencies ranging from 55 MHz to 135 MHz. The total harmonic distortion is less than 1%, while frequency slew rate is greater than 16 MHz/ns.     

MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8nm)

An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance     

225MHz-400MHz压控调谐滤波器的实现

在跳频收发系统中，在射频前端加入调谐滤波器可以提高系统的抗阻塞干扰能力。文章详细介绍了一种225MHz-400MHz压控调谐滤波器的实现方法，该方法主要是通过电压改变变容二极管的电容，从而改变带通滤波器的中心频率，从而实现压控滤波。因此通过分段线性电压来控制带通中心频点就可以对跳频信号进行跟踪滤波。     

Millimetre-wave VCO with enhanced f/sub trans/

A 60 GHz voltage-controlled oscillator (VCO) with a double cross-coupled negative-resistance cell is presented. The proposed double cross-coupled pair shows higher f_trans and lower input capacitance than a typical capacitive-degeneration cross-coupled pair at millimetre-wave band. The 60 GHz double cross-coupled VCO has phase noise of -84 dBc/Hz at 100 kHz offset from 59.2 GHz and good FOM of -188 dBc/Hz.     

A voltage-controlled tunable distributed RC filter

A new type of voltage-controlled tunable distributed RC filter is described by the type metal-insulator-semiconductor-metal. Tuning is attained by field-effect control of the capacitance by a bias voltage, independently of the distributed resistance. Results are given for evaporated thin-film NiCr-Y/SUB 2/O/SUB 3/-CdS-Al filters, together with illustrative applications to tunable RF networks.     

On the pinched hysteresis behavior in a state-controlled resistor

We show that the pinched hysteresis behavior observed in a voltage-controlled resistor with state-feedback self-control can be attributed to the current flowing in the parasitic capacitance holding the voltage across this resistor. A mathematical model describing this circuit structure is derived and validated numerically. To provide experimental evidence of this proposal, a circuit representing a voltage-controlled resistor is placed in parallel with a capacitor and then the current in this capacitor, which is proportional to the derivative of the applied voltage, is sensed, converted into a voltage and used to control the resistance value. This leads to the appearance of a pinched hysteresis loop as theoretically predicted. This work provides further insight into the origin of this behavior in fabricated solid-state devices that can be shown to follow the proposed circuit structure.     

Design and implementation of a CMOS VCXO for FM stereo decoders

A circuit technique to simulate large variable capacitance of both positive and negative polarities over a given frequency range is discussed. The simulated capacitance can be varied by voltage control from -60 to +100 pF. The capacitor-simulating circuit is connected in parallel with a resonator to tune its parallel resonance. An oscillator with grounded resonator is also developed. Together with the variable capacitor, a voltage-controlled crystal oscillator (VCXO) is realized. The oscillation frequency of the oscillator can be tuned continuously from 452 to 461 kHz by voltage control. Detailed analyses to completely characterize the oscillator with a simple expression are presented. The prototype of the VCXO has been fabricated in a 4-μm standard CMOS process     

VCO电路测试新型BST电容器的可变电容特性

基于新型BST电容器的变容机理,采用集成芯片MC12148设计VCO(压控震荡器)测试电路,通过测量不同控制电压对应的频率,计算出材料的电容与介电常数,研究了新型BST的压控特性,推导出该BST材料的电压与电容关系式。结果显示:新型BST材料加正反偏压电容都发生变化;最大耐压值为40 V;其电容调谐率与压控灵敏度都很小,分别为10.691%和5.717 kHz/V;材料应用在频率合成器的微调上,可提高合成频率的灵敏度与精度。     

A sinusoidal voltage-controlled oscillator for integrated circuits

This article describes an inductorless near-harmonic voltage-controlled oscillator circuit that utilizes a compensated Wien-bridge topology with a voltage-controlled Miller integrator as the tuning element. Suitable for monolithic integrated realization, the VCO offers a two-to-one control range for frequencies up to 10 MHz, with less than a 1-dB amplitude variation and less than a ten percent total harmonic distortion over the entire control range.     

电感电容压控振荡器调谐曲线的时域分析

本文提出了一种基于周期计算技术的压控振荡器频率-电压调谐曲线的分析方法.在传统的谐波平衡近似方法中,通过大信号非线性分析方法可以计算出一个周期内可变电容的有效电容值.然而通过有效电容推导的调谐曲线并不准确,况且如果高阶谐波分量不可以忽略的话,谐波平衡近似分析方法将会变得很复杂.本文提出的周期计算方法所得到的振荡调谐曲线比传统谐波平衡近似分析方法更加精确.在0.35μm 2P4M CMOS工艺上实现的电感电容压控振荡器的实验测试证明了该理论分析的正确性.     

Low-Power BiCMOS Optical Receiver With Voltage-Controlled Transimpedance

An optical receiver with voltage-controlled transimpedance using a current conveyor and a voltage amplifier monolithically integrated with a PIN photodiode in 0.6 mum BiCMOS technology is presented. The transimpedance is directly proportional to a voltage-controlled resistance, and can be continuously varied by changing its control voltage. Thanks to the mixed current-mode and voltage-mode signal processing, the bandwidth of the optical receiver is virtually independent of the photodiode capacitance. A linearity error smaller than 3.1%, a sensitivity dynamic range of 78.8 (37.9 dB) with the largest sensitivity of S = 890 mV/muW at 660 nm, an offset voltage smaller than 0.53 mV, a largest maximum power consumption of only 3.2 mW, a small-signal frequency bandwidth up to 189 MHz, a large-signal rise time/fall time down to 3.7 ns/3.3 ns, and an output noise level down to -77.8 dBm (for a frequency of 50 MHz and a resolution bandwidth of 30 kHz) are achieved     

一种考虑MOS效应及频变特性的类传输线型锥形TSV通孔电学模型

为准确描述锥形TSV通孔寄生电阻、电容、电感高频下MOS效应及其频变特性,本文首先推导出了锥形TSV通孔压控MOS电容的解析模型。其次基于修正后的双传输线寄生参数提取公式对锥形TSV通孔内寄生参数进行了提取。最终建立了一种考虑MOS效应及频变特性的类传输线型锥形TSV通孔电学模型。通过仿真工具验证模型精度,结果显示：在100GHz频带内模型与仿真结果吻合度较高,可以准确描述高频下锥形TSV通孔内寄生参数的半导体物理特性及频变特性,可用来预测锥形TSV通孔的电学特性,对优化三维集成电路电学性能有一定指导意义。     

二阶压控电压源低通滤波器设计

本文详细介绍二阶压控电压源低通滤波器的设计方法,给出了其通用表达式。设计方法是根据所需转折频率,在1:2至1:10较宽的范围内灵活取两电容值,再计算出与灵活选取的电容准确匹配的电阻阻值。相对于查表法、图示法取值更具灵活性和实用性,由于不需要精确匹配成本较高的电容,此方法还具有成本较低的优势。用Multisim-10仿真软件对所设计的二阶压控电压源低通滤波器进行模拟仿真,结果表明与理论计算符合得很好。     

The GaAs traveling-wave amplifier as a new kind of microwave transistor

A versatile solid-state microwave amplifier has evolved from a combination of transistor mechanisms and the transferred-electron effect. The prototype device, called a "traveling-wave transistor," employs a 2-µm layer of n-type GaAs grown epitaxially on a semi-insulating substrate. A transistor-like input launches a traveling space-charge wave that grows exponentially as it moves along the surface to a relatively distant output. There it is converted back into an electromagnetic wave. The long distance between input and output minimizes the feedback capacitance that often limits gain and bandwidth in high-frequency devices. Twelve experimental units show broad-band net gain in X band, with 10-30-dB built-in isolation. One unit exhibits instantaneous net gain from 6.7 to 15.3 GHz; another yields 28 dB at 9.2 GHz. All devices are good for linear microwave signal processing: voltage-controlled phase modulation at constant net gain, or voltage-controlled gain modulation at constant phase. Different bias conditions make possible threshold-sensitive saturated-amplitude amplification of pulses or sinusoids for logic or digital functions.     

A slew-rate controlled output driver using PLL as compensation circuit

A slew-rate controlled output driver adopting the delay compensation method has been implemented using 0.18-/spl mu/m CMOS process for storage device interface. A phase-locked loop (PLL) is used to generate compensation current and constant delay time. The compensation current reduces the slew-rate variation over process, voltage, and temperature variation of the output driver. The constant delay time, which is generated by the replica of the voltage-controlled oscillator in the PLL, reduces the slew-rate variation over load capacitance variation. Such an output driver has 25% less variation at slew rate than that of the conventional output driver. The proposed output driver is able to meet UDMA100 interface that specifies load capacitance ranging from 15 to 40 pF and slew rate from 0.4 to 1.0 V/ns.