用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术,制备出应变Si/弛豫Si0.9Ge01/渐变组分弛豫SiGe/Si衬底.通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺,有效地降低了表面粗糙度和位错密度.与Ge组分突变相比,采用线性渐变组分后,应变硅材料表面粗糙度从3.07nm减小到0.75nm,位错密度约为5×104 cm-2,表面应变硅层应变度约为0.45%.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术,制备出应变Si/弛豫Si0.9Ge01/渐变组分弛豫SiGe/Si衬底.通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺,有效地降低了表面粗糙度和位错密度.与Ge组分突变相比,采用线性渐变组分后,应变硅材料表面粗糙度从3.07nm减小到0.75nm,位错密度约为5×104 cm-2,表面应变硅层应变度约为0.45%.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术，制备出应变Si/弛豫Si0.9Ge0.1/渐变组分弛豫SiGe/Si衬底. 通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺，有效地降低了表面粗糙度和位错密度.与Ge组分突变相比，采用线性渐变组分后，应变硅材料表面粗糙度从3.07nm减小到0.75nm，位错密度约为5E4cm-2，表面应变硅层应变度约为0.45%.     

氧化对SOI基SiGe薄膜残余应变弛豫的影响

研究了氧化对外延在SOI衬底上的SiGe薄膜的残余应变弛豫过程的影响.通过对SiGe薄膜采用不同工艺的氧化,从而了解不同氧化条件对SOI基SiGe薄膜的应变弛豫过程的影响.氧化将会促使SiGe薄膜中的Ge原子扩散到SOI材料的顶层硅中.而SiGe薄膜的残余应变弛豫过程将会与Ge原子的扩散过程同时进行,通过对SiGe薄膜和SOI顶层硅中位错分布的分析发现:在氧化过程中,SiGe薄膜和SOI衬底之间存在一个应力传递的过程.     

氧化对SOI基SiGe薄膜残余应变弛豫的影响

研究了氧化对外延在SOI衬底上的SiGe薄膜的残余应变弛豫过程的影响.通过对SiGe薄膜采用不同工艺的氧化,从而了解不同氧化条件对SOI基SiGe薄膜的应变弛豫过程的影响.氧化将会促使SiGe薄膜中的Ge原子扩散到SOI材料的顶层硅中.而SiGe薄膜的残余应变弛豫过程将会与Ge原子的扩散过程同时进行,通过对SiGe薄膜和SOI顶层硅中位错分布的分析发现:在氧化过程中,SiGe薄膜和SOI衬底之间存在一个应力传递的过程.     

干法氧化制备SiGe弛豫缓冲层及其表征

SiGe弛豫缓冲层是高性能Si基光电子与微电子器件集成的理想平台.通过1000℃干法氧化组分均匀的应变Si0.88Ge0.12层,在Si衬底上制备了表面Ge组分大于0.3,弛豫度大于95%,位错密度小于1.2×105cm-2的Ge组分渐变SiGe弛豫缓冲层.通过对不同氧化时间的样品的表征,分析了氧化过程中SiGe应变弛豫的主要机制.     

干法氧化制备SiGe弛豫缓冲层及其表征

SiGe弛豫缓冲层是高性能Si基光电子与微电子器件集成的理想平台.通过1000℃干法氧化组分均匀的应变Si0.88Ge0.12层,在Si衬底上制备了表面Ge组分大于0.3,弛豫度大于95%,位错密度小于1.2×105cm-2的Ge组分渐变SiGe弛豫缓冲层.通过对不同氧化时间的样品的表征,分析了氧化过程中SiGe应变弛豫的主要机制.     

低温硅结合离子注入技术制备应变Si材料

为制作应变硅MOS器件,给出了一种制备具有高表面质量和超薄SiGe虚拟衬底应变Si材料的方法。通过在Si缓冲层与赝晶Si0.8Ge0.2之间设置低温硅（LT-Si）层,由于失配位错限制在LT-Si层中且抑制线位错穿透到Si0.8Ge0.2层,使表面粗糙度均方根值（RMS）为1.02nm,缺陷密度系106cm-2。又经过P+注入和快速热退火,使Si0.8Ge0.2层的应变弛豫度从85.09%增加到96.41%,且弛豫更加均匀。同时,RMS（1.1nm）改变较小,缺陷密度基本没变。由实验结果可见,采用LT-Si层与离子注入相结合的方法,可以制备出满足高性能器件要求的具有高弛豫度、超薄SiGe虚拟衬底的高质量应变Si材料。     

〈100〉沟道方向对高迁移率双轴应变硅p-MOSFET的作用

双轴应变技术被证实是一种能同时提高电子和空穴迁移率的颇有前景的方法;〈100〉沟道方向能有效地提升空穴迁移率. 研究了在双轴应变和〈100〉沟道方向的共同作用下的空穴迁移率. 双轴应变通过外延生长弛豫SiGe缓冲层来引入,其中,弛豫SiGe缓冲层作为外延底板,对淀积在其上的硅帽层形成拉伸应力. 沟道方向的改变通过在版图上45°旋转器件来实现,这种旋转使得沟道方向在(001)表面硅片上从〈110〉晶向变成了〈100〉晶向. 对比同是〈110〉沟道的应变硅pMOS和体硅pMOS,迁移率增益达到了130%;此外,在相同的应变硅pMOS中,沟道方向从〈110〉到〈100〉的改变使空穴迁移率最大值提升了30%. 讨论和分析了这种双轴应变和沟道方向改变的共同作用下迁移率增强的机理.     

<100>沟道方向对高迁移率双轴应变硅p-MOSFET的作用

双轴应变技术被证实是一种能同时提高电子和空穴迁移率的颇有前景的方法;<100>沟道方向能有效地提升空穴迁移率.研究了在双轴应变和<100>沟道方向的共同作用下的空穴迁移率.双轴应变通过外延生长弛豫SiGe缓冲层来引入,其中,弛豫SiGe缓冲层作为外延底板,对淀积在其上的硅帽层形成拉伸应力.沟道方向的改变通过在版图上45°旋转器件来实现.这种旋转使得沟道方向在(001)表面硅片上从<110>晶向变成了<100>晶向.对比同是<110>沟道的应变硅pMOS和体硅pMOS,迁移率增益达到了130%;此外,在相同的应变硅pMOS中,沟道方向从<110>到(100)的改变使空穴迁移率最大值提升了30%.讨论和分析了这种双轴应变和沟道方向改变的共同作用下迁移率增强的机理.     

Transition from the two- to three-dimensional growth of Ge films upon deposition onto relaxed SiGe/Si(001) buffer layers

The critical thickness of the two-dimensional growth of Ge on relaxed SiGe/Si(001) buffer layers different in Ge content is studied in relation to the parameters of the layers. It is shown that the critical thickness of the two-dimensional growth of Ge on SiGe buffer layers depends on the lattice mismatch between the film and the substrate and, in addition, is heavily influenced by Ge segregation during SiGe-layer growth and by variations in the growth-surface roughness upon the deposition of strained (stretched) Si layers. It is found that the critical thickness of the two-dimensional growth of Ge directly onto SiGe buffer layers with a Ge content of x = 11–36% is smaller than that in the case of deposition onto a Si (001) substrate. The experimentally detected increase in the critical thickness of the two-dimensional growth of Ge with increasing thickness of the strained (stretched) Si layer predeposited onto the buffer layer is attributed to a decrease in the growth-surface roughness and in the amount of Ge located on the surface as a result of segregation.     

Raman谱研究不同缓冲层结构对Si_(1-x)Ge_x应力弛豫的影响

应用 Raman散射谱研究超高真空化学气相淀积 ( UHV/CVD)生长的不同结构缓冲层对恒定组分上表层 Si1- x Gex 层应力弛豫的影响 .Raman散射的峰位不仅与 Ge组分有关 ,而且与其中的应力状态有关 .在完全应变和完全弛豫的情况下 ,Si1- x Gex 层中的 Si- Si振动模式相对于衬底的偏移都与 Ge组分成线性关系 .根据实测的 Raman峰位 ,估算了应力弛豫 .结果表明 :对组分渐变缓冲层结构而言 ,超晶格缓冲层中界面间应力更大 ,把位错弯曲成一个封闭的环 ,既减少了表面位错密度 ,很大程度上又释放了应力     

Pure germanium epitaxial growth on thin strained silicon-germanium graded layers on bulk silicon substrate for high-mobility channel metal-oxide-semiconductor field-effect transistors

We demonstrate epitaxially grown high-quality pure germanium (Ge) on bulk silicon (Si) substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD) without involving growth of thick relaxed SiGe buffer layers. The Ge layer is grown on thin compressively strained SiGe layers with rapidly varying Ge mole fraction on Si substrates resulting in several SiGe interfaces between the Si substrate and the pure Ge layer at the surface. The presence of such interfaces between the Si substrate and the Ge layer results in blocking threading dislocation defects, leading to a defect-free pure Ge epitaxial layer on the top. Results from various material characterization techniques on these grown films are shown. In addition, capacitance-voltage (CV) measurements of metal-oxide-semiconductor (MOS) capacitors fabricated on this structure are also presented, showing that the grown structure is ideal for high-mobility metal-oxide-semiconductor field-effect transistor applications.     

Strained Si/SiGe MOS technology: Improving gate dielectric integrity

Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance gains in short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to the lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed.     

Radiation damage in proton-irradiated strained Si n-MOSFETs

Strained Si layers (sSi) on strain-relaxed SiGe buffer layers are frequently used in order to boost up the carrier mobility. This study investigates the degradation of such sSi n-MOSFETs by 20-MeV proton irradiation. The drain current decreases and a negative shift of the threshold voltage is observed after proton irradiation. The impact of the fabrication process of sSi transistors on the degradation is also discussed.     

超高真空化学气相生长用于应变硅的高质量SiGe缓冲层

采用UHV/CVD技术,以多层SiGe/Si结构作为缓冲层来生长应变弛豫SiGe虚衬底,并在此基础上生长出了具有张应力的Si层.利用高分辨X射线、二次离子质谱仪和原子力显微镜分别对薄膜的晶体质量、厚度以及平整度进行了分析.结果表明,通过这种方法制备的SiGe虚衬底,不仅可以有效提高外延层中Ge含量,以达到器件设计需要,而且保证很好的晶体质量和平整的表面.Schimmel液腐蚀后观察到的位错密度只有1×106cm-2.     

Thermally Processed High-Mobility MOS Thin-Film Transistors on Transferable Single-Crystal Elastically Strain-Sharing Si/SiGe/Si Nanomembranes

Demonstration of high-performance MOS thin-film transistors (TFTs) on elastically strain-sharing single-crystal Si/SiGe/Si nanomembranes (SiNMs) that are transferred to foreign substrates is reported. The transferable SiNMs are realized by first growing pseudomorphic SiGe and Si layers on silicon-on-insulator (SOI) substrates, and then, selectively removing the buried oxide (BOX) layer from the SOI. Before the release, only the SiGe layer is compressively strained. Upon release, part of the compressive strain in the SiGe layer is transferred to the thin Si layers, and the Si layers, thus, become tensile strained. Both the initial compressive strain state in the SiGe layer and the final strain sharing state between the SiGe and the Si layers are verified with X-ray diffraction measurements. The TFTs are fabricated employing the conventional high-temperature MOS process on the strain-shared SiNMs that are transferred to an oxidized Si substrate. The transferred strained-sharing SiNMs show outstanding thermal stability and can withstand the high-temperature TFT process on the new host substrate. The strained-channel TFTs fabricated on the new host substrate show high current drive capability and an average electron effective mobility of 270 cm²/V ldr s. The results suggest that transferable and thermally stable single-crystal elastically strain- sharing SiNMs can serve as excellent active material for high-speed device application with a simple and scalable transfer method. The demonstration of MOS TFTs on the transferable nanomembranes may create the opportunity for future high-speed Si CMOS heterogeneous integration on any substrate.     

应变Si1-xGex沟道PMOSFET空穴局域化研究

为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。     

Si/SiGe PMOSFET USING P^＋ IMPLANTATION TECHNOLOGY

Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor （PMOSFET） using P^＋ （phosphor ion） implantation technology is successfully fabricated. P^＋ implantation into SiGe virtual substrate induces a narrow defect region slightly below the SiGe/Si interface, which gives rise to strongly enhanced strain relaxation of SiGe virtual substrate. X-Ray Diffraction （XRD） tests show that the degree of relaxation of SiGe layer is 96% while 85% before implantation. After annealed, the sample appeared free of Threading Dislocation densities （TDs） within the SiGe layer to the limit of Transmission Electron Microscopy （TEM） analysis. Atomic Force Microscope （AFM） test of strained Si channel surface shows that Root Mean Square （RMS） is 1.1nm. The Direct Current （DC） characters measured by HP 4155B indicate that the maximum saturated transconductance is twice bigger than that of bulk Si PMOSFET.