Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4 GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4 GHz and achieves a phase noise of −130 dBc/Hz 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0 to 0.3 V. It achieves a peak to peak voltage of 0.59 V with an ultra low power consumption of 3.8 mW from a 0.6 V supply voltage. The output power level of the QVCO is −10 dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.     

A low phase noise and low spur PLL with auto frequency control circuit for L1-band GPS receiver

A low phase noise and low spur phase-locked loop (PLL) for L1-band global positioning system receiver is proposed in this paper. For obtaining low phase noise for PLL, All-PMOS LC-VCO with varactor-smoothing technique and noise-filtering technique is adopted. To reduce the reference spur, a low current-mismatch charge pump is carefully designed. A quasi-closed-loop auto frequency control circuit is used to accelerate the lock process of PLL. The PLL is fabricated in 180 nm CMOS Mixed-Signal process while it operates under 1.8 V supply voltage. The measured output frequency of PLL is 1.571 GHz and output power is −1.418 dBm. The in-band phase noise is −98.1 dBc/Hz @ 100 kHz, while the out-band phase noise is −130.3 dBc/Hz @ 1 MHz. The reference spur is −75.8 dBc at 16.368 MHz offset. When quasi closed-loop AFC is working, the measured lock time is about 10.2 μs.     

High-resolution wide-band LC-VCO for reliable operation in phase-locked loops

This paper presents a novel sizing scheme to implement the array of switches in the capacitor bank of LC-VCOs for oscillation frequency coarse control. The proposed scheme allows increasing the number of elements in the capacitor bank beyond the values typically achieved by binary scaling, endowing the resulting LC-VCO with a wider tuning range and high frequency resolution, which is beneficial for the implementation of reliable phase-locked loops. Two different gigahertz LC-VCOs have been designed to validate the proposed scheme. The prototypes, fabricated in a cost-effective 0.18 μm CMOS process, cover a 700 MHz frequency range from 1.35 GHz to 2.05 GHz and from 2.05 GHz to 2.75 GHz, respectively, with a phase noise figure of − 122 dBc/Hz and − 119.5 dBc/Hz at 1 MHz from the mid-range carriers, and a power consumption of 18 mW. These figures result in a respective FOM_T of − 186.4 dBc/Hz and − 183.8 dBc/Hz. The performance of the fabricated LC-VCOs is achieved in each case with a dense coarse tuning range of 128 levels, which allows, respectively, a fine tuning gain smaller than 40 MHz V^− 1.     

Improving linearity in MOS varactor based VCOs by means of the output quiescent bias point

This paper presents a CMOS based LC tank VCO topology improving the tuning range linearity. The VCO tuning range is linearized with PMOS varactors which remain in the inversion region for an extended range of the control voltage. This is achieved with the design of the quiescent operating point in the VCO's output nodes with a value close to the voltage rails, letting the varactors to behave quasi linearly in the achievable VCO tuning range. The experimental results of a VCO in a CMOS 0.35 µm process show a linear tuning range improvement of 75% of the control voltage in the (1.43–1.55) GHz range, with a minimum VCO gain variation compared to similar architectures. The results show a phase noise improvement from −94 dBc/Hz to −124 dBc/Hz @600 kHz offset from the carrier with an overall reduced amplitude noise for the VCO.     

Floating active inductor based Class-C VCO with 8 digitally tuned sub-bands

A fully integrated floating active inductor based voltage-controlled oscillator (VCO) is presented. The active inductor employs voltage differencing transconductance amplifier (VDTA) as a building block. The designed VCO achieves frequency tuning by varying the bias current through the VDTA and utilizes a Class-C topology for improving the phase noise performance. The inductor-less VCO is designed and implemented in a 45-nm CMOS process and its performance is estimated using Virtuoso ADE of Cadence. Operating at a supply voltage of ±1 V, the proposed VCO consumes 0.44–1.1 mW corresponding to the oscillation frequency of 1.1–1.8 GHz thereby exhibiting a tuning range of 48.27%. The phase noise of the VCO lies in the range of −94.12 to −98.37 dBc/Hz at 1 MHz offset resulting in a FOM of −172.14 to −176.69 dBc/Hz.     

Wide-tuning-range,low-phase-noise quadrature ring oscillator exploiting a novel noise canceling technique

This paper presents a novel noise-canceling technique, which is used to improve the phase noise of a two-stage quadrature ring oscillator. The thermal noise canceling circuitry is used to cancel the channel thermal noise of the output transistors in each stage of the oscillator. Simulations using TSMC 0.13 μm CMOS technology show a wide frequency tuning range of 315 MHz to 6.64 GHz and ?97.5 dBc/Hz at 1 MHz offset from 4.7 GHz for changing supply from 0.5 V to 1.6 V. The power consumption is obtained to be 14.8 mW. The proposed oscillator can be used in applications such as ultra-wideband systems, and multiband and multimode receivers.     

Optimized 2.4 GHz voltage controlled oscillator with a high-Q MWCNT network-based pulse-shaped inductor

This paper focuses on the use of a high-Q Multi-Wall Carbon Nano-Tube (MWCNT)-based pulse-shaped inductor in the implementation of an LC differential voltage-controlled oscillator (LCVCO). The topology integrates a micro-scaled capacitor and a MWCNT network-based inductor together with the CMOS circuits. The CMOS circuits were designed to enhance the quality factor and to control the oscillation amplitude. The high quality factor of the inductor improves the overall quality factor and phase noise of the oscillator. The measurement results show that the LCVCO operates at 2.3982 GHz and achieves a phase noise of ?133.3 dBc/Hz at 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.07 GHz to 2.77 GHz (29.16%) with an ultra low power consumption of 1.7 mW from a 0.6 V supply voltage. The output power level of the VCO is ?10 dBm, with an improved quality factor of 49.     

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm².     

A 5-GHz LC VCO with digital AAC and AFBS for 2.4 GHz ZigBee transceiver applications

A 5 GHz LC VCO (voltage-controlled oscillator) with automatic amplitude control (AAC) and automatic frequency-band selection (AFBS) for 2.4 GHz ZigBee transceivers is presented. Instead of continuous feedback loop, an alternative amplitude calibration scheme is proposed in this paper to alleviate the deficiencies inherent in the conventional approach. It helps to keep the VCO at optimum amplitude to avoid saturation of the cross-coupled transistors and therefore stabilizes the phase noise performance over process, voltage and temperature variations. For the ZigBee application with 16 frequency channels, a coarse tuning loop is added in this work to implement the frequency-band selection using the AFBS mechanism. The VCO core and the digital AAC, AFBS modules have been fully integrated in a 2.4 GHz ZigBee transceiver which was fabricated in a 0.18 μm RF-CMOS technology. The current consumption is 4.7 mA at 4.85 GHz with 1.8 V power supply and a chip area of about 0.285 mm² is occupied. The VCO is capable of operating from 4.67 GHz to 5.18 GHz and the measured phase-noise level is –120 dBc/Hz at 1 MHz offset from a 4.85 GHz carrier. The tuning sensitivity K_VCO of the VCO is about 78 MHz/V with 0.9 V control voltage.     

A high-yield vacuum-evaporation-based R2R-compatible fabrication route for organic electronic circuits

Advances are described in a vacuum-evaporation-based approach for the roll-to-roll (R2R) production of organic thin film transistors (TFTs) and circuits. Results from 90-transistor arrays formed directly onto a plasma-polymerised diacrylate gate dielectric are compared with those formed on polystyrene-buffered diacrylate. The latter approach resulted in stable, reproducible transistors with yields in excess of 90%. The resulting TFTs had low turn-on voltage, on–off ratios ∼10⁶ and mobility ∼1 cm²/V s in the linear regime, as expected for dinaphtho[2,3-b:2′,3′-f] thieno[3,2-b]thiophene the air stable small molecule used as the active semiconductor. We show that when device design is constrained by the generally poor registration ability of R2R processes, parasitic source–drain currents can lead to a >50% increase in the mobility extracted from the resulting TFTs, the increases being especially marked in low channel width devices. Batches of 27 saturated-load inverters were fabricated with 100% yield and their behaviour successfully reproduced using TFT parameters extracted with Silvaco’s UOTFT Model. 5- and 7-stage ring oscillator (RO) outputs ranged from ∼120 Hz to >2 kHz with rail voltages, V_DD, increasing from −15 V to −90 V. From simulations an order of magnitude increase in frequency could be expected by reducing parasitic gate capacitances. During 8 h of continuous operation at V_DD = −60 V, the frequency of a 7-stage RO remained almost constant at ∼1.4 kHz albeit that the output signal amplitude decreased from ∼22 V to ∼10 V. Over the next 30 days of intermittent operation further degradation in performance occurred although an unused RO showed no deterioration over the same period.     

A broadband and compact asymmetrical backward coupled-line coupler with high coupling level

A new wideband asymmetric microstrip coupled-line coupler with 3 dB coupling value and quadrature phase difference is presented. Compared with the conventional edge-coupled couplers, this structure, consisting of two different transmission lines (interdigital and conventional microstrip transmission lines) as coupled lines, achieves wider operating bandwidth and larger coupling level. The coupled-line length of the proposed structure is approximately λ_g/4. To characterize the structure, an equivalent circuit model has been established. A 3 dB designed and fabricated coupler with 0.2 mm spacing between coupled lines exhibits an amplitude balance of 2 dB from 2.2 GHz to 4.2 GHz. Good agreements between the full-wave simulation and equivalent circuit model results has been achieved and verified the effectiveness of the proposed circuit model. Also, measurement results have been presented.     

A 10 GHz low phase-noise CMOS voltage-controlled oscillator using dual-transformer technology

A novel low phase-noise differential Colpitts VCO by using transformer feedback technology is presented in this paper. This work demonstrates a simple differential topology with dual-transformer approach to reduce phase-noise at low DC power consumption. A symmetrical circuit layout can be realized easily by transformers and a commonly cross-coupled structure is not adopted herein because cross couple feedback path is also a serious parasitic effect more at 10 GHz operation. Therefore, dual-transformers provide a compact feedback path and DC feed path simultaneously. Consuming a DC power of 8 mW in the VCO core, the circuit exhibits a phase-noise of ?115 dBc/Hz at offset frequency of 1-MHz and the figure of merit value is ?184.1 dBc.     

A tunable optoelectronic oscillator based on a tunable microwave attenuator

A novel realization of a wideband tunable optoelectronic oscillator (OEO) based on dual-port electrode Mach–Zehnder modulator (DMZM), a tunable microwave attenuator (TMA), and a chirped fiber Bragg grating (CFBG) is proposed and demonstrated. By simply adjusting the power ratio between the two arms of DMZM, the chirp of the DMZM will be tuned, and the center frequency of the microwave photonic filter will be tuned. When the OEO loop in the proposed system is closed, the output frequency of OEO is determined by the microwave photonic filter, and a high spectral purity microwave signal with a tunable frequency from 5.8 to 11 GHz is generated. The single sideband (SSB) phase noise of the generated signal could reach −107.4 dBc/Hz at an offset frequency of 10 kHz.     

A polyphase filter based on CMOS inverters

A new idea for generation of quadrature signals on chip is presented. The topology is based on a passive RC polyphase filter, where the resistive parts are made active by using inverters. The active filter combines quadrature generation, isolation, and gain without losing quadrature performance compared to a regular RC polyphase filter. The filter technique is demonstrated in a 10 GHz front-end application where a broadband VCO, having a tuning range of 1.44 GHz, drives an active polyphase filter to generate quadrature LO signals. According to simulations the quadrature phase error shows a typical tuned behavior and stays below 0.8° for the complete tuning range. Since the signal amplitude is high throughout the filter the noise is low, below 160 dBc/Hz at 10 MHz offset. The high amplitude also reduces the need for high gain tuned buffers, thereby enabling significant reductions in chip area.     

CMOS balanced regenerative frequency dividers for wide-band quadrature LO generation

CMOS regenerative frequency dividers, based on a fully balanced Gilbert cell, are analyzed in this paper for quadrature local oscillator (LO) signal generation. Driven in opposite phase by double frequency signals, they provide quadrature waveforms while simultaneously driving large mixers LO input capacitances, thereby avoiding power hungry buffers typically required. Experimental results, carried out on 0.18 μm CMOS prototypes, show 68% bandwidth around 2 GHz center frequency, with a quadrature accuracy better than 1°, making them suitable for multi-standard wireless receivers. To keep the output amplitude constant while simultaneously minimizing the average power consumption, a digital calibration loop regulates each divider biasing current.     

Oscillation-controlled CMOS ring oscillator for wireless sensor systems

This paper presents a ring oscillator with the function of the oscillation controlled for wireless sensor systems (WSSs). The proposed oscillator consists of a NAND gate, 4 inverters, and 1-, 3-, 9-times buffer stage. Operation of it is controlled by the NAND gate. The oscillator can reduce the power loss because the oscillator is oscillated during only high level input. The proposed oscillator was designed and fabricated by 2.5 μm CMOS technology, through which it is possible to realize a WSS on a single chip because a sensor and an oscillator can be fabricated concurrently.The frequency tuning range of the oscillator was found to be approximately 90–152 MHz and the output power of the oscillator was ?8.42 dBm. The measured phase noise is ?99.35 and ?102.59 dBc/Hz at 1 and 5 MHz offsets, respectively, from the carrier of 152 MHz. Power consumption of the oscillator is determined by the duty cycle of the input signal pulse, and the range of power consumption was measured as 1.5–45 mW at the duty cycle of 1.0.     

Low-harmonic distortion in single-ended and push-pull class E power amplifier by using slotted microstrip lines

In this work, a very low-harmonic distortion with high power-added efficiency (PAE) power amplifier (PA) with slotted microstrip lines is reported. The circuit is a push-pull class E amplifier, terminated with defected structures to improve the spectrum purity and efficiency. The relationship of the second and third harmonic to the fundamental is 70 and 54 dBc, respectively. The amplifier is developed with HBT medium power transistors. The circuit works at 1.8 GHz obtaining a PAE close to 60%, delivering an output power of 24 dBm with a power gain of 13.3 dB.     

Performance evaluation of (D)APSK modulated coherent optical OFDM system

Performance of amplitude and phase shift keying (APSK) modulated coherent optical orthogonal frequency division multiplexing (CO-OFDM) with and without differential encoding is investigated. Numerical simulations based on 40 Gbit/s single-channel and 5 ^* 40 Gbit/s wavelength division multiplexing transmission are performed, and the impacts of amplified spontaneous emission noise, laser linewidth, chromatic dispersion, and fiber nonlinearity on the system performance are analyzed. The results show that compared with conventional 16 quadrature amplitude modulation (QAM) modulated optical OFDM signal, although 16(D)APSK modulated optical OFDM signal has a lower tolerance towards amplified spontaneous emission (ASE) noise, it has a higher tolerance towards fiber nonlinearity such as self-phase modulation (SPM) and cross-phase modulation (XPM): the optimal launch power and the corresponding Q² factor of 16(D)APSK modulated OFDM signal are respectively 2 dB and 0.5 dB higher than 16QAM modulated optical OFDM signal after 640 km transmission, both in single-channel and WDM CO-OFDM systems. Although the accumulated CD decreases the peak-to-average power ratio (PAPR) during transmission, 16(D)APSK modulated OFDM signal will still remain an advantage compared with 16QAM modulated OFDM signal up to 1000 km single-channel transmission, meanwhile relaxing the needs for training symbols and pilot subcarriers and consequently increase the spectral efficiency.     

Chromatic dispersion estimation methods using polynomial fitting in PDM-QPSK or other multilevel-format coherent optical systems

We propose a polynomial fitting algorithm based method for non-data-aided chromatic dispersion (CD) estimation in single carrier (SC) coherent optical systems with arbitrary modulation formats, and compare it with our previously proposed CD estimation method which is also based on the polynomial fitting algorithm but requires special modulation formats thus is a data-aided CD estimation method for systems with PDM-QPSK or other multilevel modulation formats. For the data-aided CD estimation method, an extra chirp-free OOK signal is transmitted. The curve of the average phase at the frequency ± f as a function of the frequency f is measured at the coherent receiver. The accumulated CD is then estimated with a polynomial fitting algorithm. In the simulation of a 50 Gbaud 50%-RZ OOK system through 12.5 × 80 km standard single mode fiber (SSMF), the estimation errors are within ± 50 ps/nm in 20 tests when the launch power is from −5 dBm to −1 dBm. Non-data-aided CD estimation for arbitrary modulation formats is achieved by measuring the differential phase between frequency f ± f_s/2 (f_s is the symbol rate) in digital coherent receivers. The estimation errors are within ± 200 ps/nm, in a 50 Gbaud PDM-QPSK system through 10 × 80 km SSMF with the launch power from −3 dBm to −1 dBm. The estimation accuracy can be potentially improved by averaging multiple results. The data-aided CD estimation method has an inherently bigger estimation range than that of the newly proposed non-data-aided method, while the newly proposed non-data-aided method can tolerate a much larger frequency offset between the transmitter and the local oscillator. These methods are promising for future optical fiber networks with dynamic optical routing and coherent detection.     

Injection locking phase rotator for Outphasing transmitter

This paper presents a novel technique of implementing the amplitude information into out-phase mapping, which is a necessary block of the high-efficiency Outphasing transmitter architecture. The proposed technique is based on using injection locking ring oscillator and switching-based control circuit to implement phase rotator. The technique is compatible with digital implementation using DSP. Since, Outphasing transmitters use switching power amplifiers, this implementation is suitable for an all-digital and adjustable transmitter implementation. The modulator system is designed using UMC130 nm CMOS technology; and is simulated at 1.8 GHz operation frequency, as it is commonly used in multiple mobile applications requiring high power levels. Simulation shows an out-phasing error of 0.41° rms, across the whole input amplitude sweep of 45 dB. The power consumption of the single phase rotator is 1.5 mW from 1.2 V supply.