Trajectory prediction control for digital control DC–DC converters with fast transient response

A novel trajectory prediction control algorithm for digital control DC–DC converters has been presented in this paper. The proposed trajectory prediction control algorithm can provide an accurate prediction of the duty ratio of the next several switching cycles, so as to overcome the inherent time delay of the digital control loop, and to improve the transient response of digital control DC–DC converters, including load response, line response and reference tracking response. A digital control buck DC–DC converter was implemented to verify the effectiveness of the proposed prediction control algorithm. The recovery time is about 8 μs and 4 μs respectively, when the load current changes from a full load to a 17% load and the input voltage changing between 5 V to 6 V. The fastest reference tracking speed is about 26.7 μs/V.     

Successive-divider-line ADC dedicated to low-power medical devices

A low-power and small silicon area digitally controlled Switched Mode Power Supply (SMPS) is intended for the minimization of both power and size of an on-chip DC power supply building block which is mainly dedicated for implantable medical sensing and microstimulation devices. Such SMPS is based on a successive divider-line analog-to-digital Converter (SDLADC), which is the focus of this paper. Special attention is paid for reducing the power consumption and silicon area of this SDLADC, which consists of a resistor network based on diode connected transistor used to replace the delay-line of the windowed ADC. To compensate process and temperature variations, a digital calibration technique is used to meet the specified static and dynamic output voltage regulations and avoid variations of the regulated SMPS output voltage. The proposed ADC is implemented in AMS 0.35 μm CMOS process. Simulation results show a current consumption of 1.5 μA/MHz and conversion time of 10 ns much lower than recent conventional topology values. The proposed circuit exhibits a quantization steps smaller than 1.6% of V_ref and it can be a solution for high switching frequency, which results on faster regulation of SMPS output voltage.     

A design methodology for integrated inductor-based DC–DC converters

A design methodology for monolithic integration of inductor based DC–DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 μm CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80 nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016 mm² with under 1 μW power consumption for providing 0.7 °C effective resolution at 1 sample/s processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.     

Pseudo-V2 control with adaptive compensation for fast-transient current-mode buck converter

A type of pseudo-V² control, with on-chip adaptive compensation to achieve fast transient (FT) response for current mode DC–DC buck converter, has been proposed and simulated using 0.18 μm CMOS technology in this paper. Based on a new on-chip capacitor multiplier, adaptive compensation is achieved by making the compensation capacitance to track the load current. The proposed pseudo-V² control utilizes the output ripple to determine the duty cycle during load transient. Thus the overshoot/undershoot voltage and the transient recovery time are effectively reduced. Simulation results demonstrate the transient ripple is smaller than 50 mV and the transient recovery time is shorter than 10 μs for a 450 mA load current step. The maximum power conversion efficiency is 94.6% at 1 MHz switching frequency when input and output voltages are 5 V and 1.8 V, respectively.     

An 8 bit, 100 kS/s,switch-capacitor DAC SAR ADC for RFID applications

An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is introduced to provide stabilized current. This invariable current from RDCM, charging or discharging the only capacitor in circuit is controlled by pulse width modulated signal to realize switch capacitor DAC. The switch control scheme is built using basic AND gates to generate the control signals for RDCM. Only one capacitor and reduced transistor count in digital part reduces the silicon area occupied by the ADC to only 0.0098 mm². The converter, designed in GPDK 90 nm CMOS, exhibits maximum sampling frequency of 100 kHz & consumes 6.75 µW at 1 V supply. Calculated signal to noise and distortion ratio (SNDR) at 1 V supply and 100 kS/s is 48.68 dB which relates to ENOB of 7.79 bits. The peak values of differential and integral nonlinearity are found to be +0.70/−0.89 LSB and +1.40/−0.10 LSB respectively. Evaluated figure of merit (FOM) is 3.87×10²⁰, which show that the proposed ADC acquires minimal silicon area and has sufficiently low power consumption compared to its counterparts in RFID applications.     

Improving GBW product on CMOS operational transconductance amplifiers by interleaved feedforward paths

This paper presents two Operational Transconductance Amplifier (OTA) compensation schemes for multistage topologies. The solutions are based on interleaved feedforward paths that cancel a non-dominant pole similarly to the zero nulling resistor technique with the advantage of avoiding resistors. Both schemes are designed in 90 nm CMOS process, the first one obtains 71 dB of DC gain, a gain bandwidth product (GBW) of 720 MHz with 360 μW of power consumption. The second proposed scheme obtains a similar DC gain and doubles the former proposed OTA GBW at the expense of 2.2 mW of power consumption for high speed applications. The compensation schemes are theoretically analyzed and the design guidelines are presented. The results of post layout simulations and corner analysis validate the new solutions.     

Feed-forward Output Swing Prediction AGC design with Parallel-Detect Singular-Store Peak Detector

This paper presents an Automatic Gain Control (AGC) circuit design with 200–530 μW average power consumption given a 1 V supply. The Variable Gain Amplifier (VGA) therein comes with 0.9 V input range and output stages with a swing of 0.9 V and a minimum bandwidth of 100 MHz. Feed-forward Output Swing Prediction is used to adjust the gain of the VGA corresponding to the signal envelope detected by a Parallel-Detect Singular-Store Peak Detector. At a maximum refresh-rate of 4 MHz, the AGC is capable of adjusting the gain of the VGA within less than 250 ns when the input signal envelope is reduced by 20 dB, and 100 ns when raised by 20 dB. The circuit design is carried out using a 0.18 μm standard CMOS process with a core area of 0.0024 mm².     

Self-heating and destruction of high-voltage 4H-SiC rectifier diodes under a single short current surge pulse

Self-heating of high-voltage (6 kV class) 4H-SiC rectifier p⁺–n–n⁺ diodes under the action of a single 20 μs forward current surge pulse has been studied experimentally up to current densities j ≈ 100 kA/cm². The diode parameters are stable after a single surge pulse with current density j ≈ 60 kА/cm², although the estimated temperature of the diode at the end of this pulse is ～1650 K. After several pulses of this amplitude or after subjecting the diode to pulses with higher current density, the diode degrades. The degradation is manifested in an irreversible decrease of the differential resistance of the diode under a high forward bias. Even a single 20 μs pulse with peak current density j ≈ 100 kA/cm² leads to total destruction of the device.     

DC and microwave characteristics of Lg 50 nm T-gate InAlN/AlN/GaN HEMT for future high power RF applications

The DC and microwave characteristics of L_g = 50 nm T-gate InAlN/AlN/GaN High Electron Mobility Transistor (HEMT) on SiC substrate with heavily doped n+ GaN source and drain regions have demonstrated using Synopsys TCAD tool. The proposed device features an AlN spacer layer, AlGaN back-barrier and SiN surface passivation. The proposed HEMT exhibits a maximum drain current density of 1.8 A/mm, peak transconductance (g_m) of 650 mS/mm and ft/fmax of 118/210 GHz. At room temperature, the measured carrier mobility, sheet charge carrier density (n_s) and breakdown voltage are 1195 cm²/Vs, 1.6 × 10¹³ cm⁻² and 18 V respectively. The superlatives of the proposed HEMTs are bewitching competitor for future monolithic microwave integrated circuits (MMIC) applications particularly in W-band (75–110 GHz) high power RF applications.     

Low threshold melt-processed two-photon organic surface emitting upconversion lasers

Herein, a low threshold, wavelength-tunable, compact, two-photon pumped upconversion laser is presented. The surface emitting lasers are composed of melt-processed 1,4-bis[2-[4-[N,N-di(p-totyl)amino]phenyl]vinyl]benzene (DADSB) as active media and two designed distributed bragg reflectors. The melting fabrication process is very simple, and the lasing threshold is as low as 150 μJ cm^?2 pulse^?1, when pumped by a Ti:sapphire amplifier operating at 800 nm with a 150 fs pulse width. To the best of our knowledge, it is one of the lowest values for two-photon lasers. Lasing from multimode to single-mode oscillation is demonstrated. Tunable single mode oscillation was obtained at wavelength from 514 nm to 523 nm with a spectral width of less than 0.2 nm.     

Thermal-aware design and fault analysis of a DC/DC parallel resonant converter

In this paper a 3-D electrothermal (ET) analysis of a DC–DC parallel resonant converter (PRC) for constant current (CC) application is presented. A full 3-D ET simulation approach is proposed at application level to provide a support for the design stage and to analyse possible fault conditions inside the active devices. Simulations and measurements have been performed on a 100 W–2 A prototype of a PRC-CC circuit with 80 kHz nominal switching frequency.In particular, in the reported case study, the analysis has been focused on the full-bridge section of the circuit in order to prove the effect of the soft switching operation, introduced by the resonant technique, and consider the effect of possible fault conditions. To this purpose an unexpected short-circuit condition on a power MOSFET composing the H-bridge is considered, to evaluate the ET circuit behaviour and the time-to-failure of the power section. Considerations are carried out in terms of minimum requirements of protection circuits which must be fulfilled in order to avoid catastrophic system failure.A second power converter, rated for 1.5 kW, has been then designed, based on the same circuital topology, and an ET simulation has been performed in order to carry out considerations on the effect of mismatches among the input bridge devices.     

A new type of low power read circuit in EEPROM for UHF RFID

A novel low power read circuit without reference in 1 k-bits electrically erasable and programmable (EEPROM) for UHF RFID is designed and implemented in SMIC 0.18 μm EEPROM process. The read power consumption is optimized using a pre-charge sense amplifier. To improve the performance of the read circuit, a self-detect circuit, a read control logic and a feedback scheme are adopted, combined with a special time sequence. For a power supply voltage of 1 V, an average power consumption of 1.6 μA for the read operation of the EEPROM can be achieved when the read clock frequency is 640 kHz. What is more, with a 110 °C temperature change, the read power consumption variation is as low as 12%. The die size of the EEPROM is 0.15 mm², where the read circuit occupies 0.0125 mm².     

Simulation based study of thermal effects on periodic nanostructures fabricated by laser interference

Laser interference based direct writing is a potential solution for wide range of fabrication of nanostructure. This paper deals with two dimensional heat conduction analysis and the simulation of the same on silicon and germanium surfaces. Simulation of direct writing of patterns with 193 nm, 27 nsec, single pulse laser source with power varied from 800 mJ/cm² to 1100 mJ/cm² are presented. The rise in the temperature on the surfaces as well as beneath the surface is analyzed on the basis of the results. We also report about the dependency of the thermal diffusion length on the homogeneity of the formed structures.     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25 μm CMOS technology

This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25 μm/5 V CMOS technology. Breakdown voltages of 20 V for n-channel device with a specific on resistance of 1.06 mΩ cm² and −20 V for p-channel device with a specific on resistance of 2.83 mΩ cm² have been achieved without any modification of existing standard CMOS process.     

High power 4H–SiC pin diodes (10 kV class) with record high carrier lifetime

The hole lifetime τ_p in the n-base and isothermal (pulse) current–voltage characteristics have been measured in 4H–SiC diodes with a 10 kV blocking voltage (100 μm base width). The τ_p value found from open circuit voltage decay (OCVD) measurements is 3.7 μs at room temperature. To the best of the authors’ knowledge, the above value of τ_p is the highest reported for 4H–SiC. The forward voltage drops V_F are 3.44 V at current density j = 100 A/cm² and 5.45 V at j = 1000 A/cm². A very deep modulation of the blocking base by injected non-equilibrium carriers has been demonstrated. Calculations in term of a simple semi-analytical model describe well the experimental results obtained.     

Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2

We analyzed the noise characteristics of 0.18 μm and 0.35 μm nMOSFETs with a gate area of 1.1 μm² in the frequency range of 1 Hz to 100 kHz. Both two- and four-finger devices were investigated and analyzed. The experimental results show that the noise of 0.35 μm gate-length nMOSFET possesses lower 1/f component than the 0.18 μm one, whereas the four-finger devices reveal less 1/f noise than those of with two-finger ones. Furthermore, we used time domain measurement of drain current and also the statistical analysis of wafer level on the random telegraph signals (RTS) tests, and the results showed that RTS noise is higher in devices with a 0.35 μm gate-length, and devices with a smaller gate finger width produce more RTS noise than devices with a larger gate finger width.     

Increased doping depth of Al in wet-chemical laser doping of 4H-SiC by expanding laser pulse

Al is doped into 4H-SiC by irradiating pulsed KrF excimer laser to 4H-SiC immersed in AlCl₃ aqueous solution. Impact on doping depth of the use of expanded laser-pulse width is investigated. Expanded laser pulse is produced by splitting and recombining the laser beam with mirrors. The laser pulse width was expanded from its original width of 55–100 ns, while the peak power of the expanded pulse is as half as that of the original pulse under the same laser fluence. Multiple shots of the expanded laser pulses increased the doping depth at the Al concentration of 1×10¹⁶ /cm³ to 100 nm from 30 nm of the single shot of the original short, high-peak power laser. The increased doping depth could be due to enhanced diffusion by extra vacancies generated by the repeated laser irradiations. Due to the smaller laser peak power, the expanded pulse laser can suppress damage generation under multiple laser shots and, as a result, leakage current of the pn junction diode is kept low.