Impact of technology scaling and process variations on RF CMOS devices

Inspired by the huge improvement in the RF properties of CMOS devices, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Moreover, the RF frequency performance of CMOS is investigated under the influence of process variations for different CMOS generations. Using the BSIM4 model, it is found that future CMOS technologies have high prospects in the RF industry and will continue challenging other technologies in the RF domain to be the dominant technology for RF transceivers and system-on-chip implementations.     

Design of self-bias tail transistor technique for low phase noise CMOS VCO with harmonic suppression using capacitance ground

This paper presents a low phase noise wideband CMOS VCO based on the self-bias tail transistor technique and harmonic suppression using a capacitance ground. This VCO utilizes switching capacitor arrays in which four channels are able to be selected for multi-band application. Moreover, the design of CMOS VCO makes good use of the self-bias tail transistor and capacitance ground filter technique to reduce the phase noise. The MOS varactors are used as fine tuning for wideband operating application. The fully integrated VCO provides excellent performance with high FOM −193 dBc/Hz. The bandwidth of the frequency is 1.1 GHz and the tuning range is 13.8%. The power dissipation of the core circuit is 8.28 mW under a 1.8 V supply and phase noise is measured as low as −123.6 dBc/Hz at 1 MHz offset under 8.5 GHz oscillation frequencies. This VCO was made by the TSMC 0.18 μm 1P6M CMOS standard process and the chip area is 0.75×0.69 (mm²).     

Purification of inductors and improvement of phase noise in monolithic differential LC-VCOs

A novel idea for the improvement of phase noise in differential LC-VCOs with no degradation of power consumption is proposed. Being based on purification of inductors to enhance the quality factor (Q), the application of the idea in design of CMOS based Giga Hertz (GHz) range low power and low phase noise monolithic differential LC-VCOs is illustrated and analyzed. Post-layout simulations using CMOS 0.18 μm TSMC RF design kit are used for evaluation.     

Full oscillation cycle phase noise analysis of differential CMOS LC oscillators

This paper analyzes the phase noise of the widely used differential LC oscillator topology and presents brief equations describing phase noise over the entire oscillation period. The findings show that if a capacitance is present at the source node of the differential pair, two phenomena occur that increase the phase noise: the switch time increases, lengthening the interval spent in a noisy balanced state and increasing the transistor noise excess factor; and at higher frequencies the unbalanced state starts to contribute phase noise. The analysis is based upon the superposition of piecewise linear equations using the EKV transistor model, which includes a concise formulation of the noise excess factor.     

一款具有低相噪，宽调频范围和高线性度的压控晶体振荡器芯片

本文实现了一款带有LVCMOS和LVPECL输出的压控晶体振荡器芯片(VCXO-IC),具有低相噪,宽调节范围和高线性度等特点。通过采用一种新颖的差分倍频Colpitts振荡器来得到低噪声的2倍频输出;宽调节范围和高线性度通过采用MOS变容管阵列来实现。测试结果表明,当采用AT切40MHz晶体时,该芯片在1kHz处的相位噪声达到-135dBc/Hz,频率调节范围达到 /- 130ppm,且线性度小于5%。该芯片采用Chartered 0.35μm CMOS 2P3M工艺,芯片总面积为2.4 mm2。     

基于90nmCMOS工艺的低功耗宽带压控振荡器设计

A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET(IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range(FTR) of 18.4%and a phase noise of –101.38 d Bc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185d Bc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.     

Design and frequency/phase-noise analysis of a 10-GHz CMOS ring oscillator with coarse and fine frequency tuning

A 10-GHz CMOS ring oscillator that employs a multi-pass technique for boosting its frequency is proposed in this paper. The proposed circuit allows the tuning gain to be lowered by deploying the coarse/fine frequency tuning whilst maintaining wide frequency coverage. The small signal model of the proposed delay stage and the circuit operation are discussed in this paper. The time-variant analysis presented permits accurate prediction of the frequency tuning characteristic and the results have been verified by simulation. The phase noise analysis is also discussed in detail to provide better insight to the noise that is contributed by each transistor. The calculated results agreed well with that of the simulations. Hai Qi Liu was born in Jiangsu, China, in 1979. He received the B.S. and M.Sc. degrees, both in electrical engineering from the Tianjin University, Tianjin, China, in 2000, and Tongji University, Shanghai, China, in 2003, respectively. He is currently working toward the Ph.D. degree at the Nanyang Technological University, Singapore. His research focuses mainly on the design of fully integrated oscillators and Phase-Locked Loops for optical communication applications. His research interests also include RF frequency synthesizers and RF front-end designs for wireless applications. Wang Ling Goh obtained both her B.Eng and Ph.D. degrees from the department of Electrical and Electronic Engineering at the Queen’s University of Belfast (QUB) in United Kingdom. When working on her Ph.D., she was also engaged as a research associate at the Northern Ireland Semiconductor Research Centre (NISRC) at QUB. Dr Goh joined the School of Electrical and Electronic Engineering at the Nanyang Technological University (NTU) in Singapore as a lecturer in January 1996. She is now an Associate Professor in the Division of Circuits and Systems, School of Electrical & Electronic Engineering. Dr Goh has to-date co-authored 1 book, filed 13 patents (granted), and published about 60 research papers in international conferences and journals. Her research interests are in areas of silicon device processing technologies as well as digital and mixed-signal IC designs. Liter Siek received the B.A.Sc. degree from University of Ottawa, Ontario, Canada; the M.Eng.Sc. from University of New South Wales, Sydney, Australia; and the Ph.D. from Nanyang Technological University, Singapore. From 1981 to 1983 he was employed in several companies in the area of automation and control. From 1983 to 1985, he was with SGS, currently known as ST Microelectronics situated in Castelletto, Milan, Italy, where he worked in the central R&D Laboratories for Linear IC. From 1985 to 1987, he was with the same company situated in Singapore’s Asia Pacific Design Center. Since October 1988, he has been with Nanyang Technological University. His research interests are in the design of bipolar, CMOS and BiCMOS analog/mixed signal ICs. In addition, he has authored and co-authored 53 international journal/conference technical papers.     

New implementation of injection locked technique and its application to low phase noise quadrature oscillators

A new implementation of the injection locked technique is proposed. The incident signal is directly injected into the common-source connection node of the sub-harmonic oscillator instead of the gate of the tail current source, and a narrowband noise filtering network is inserted into the same node to suppress the tail current source noise. A novel quadrature oscillator with the proposed injection locked technique is presented. The simulations show that the phase noise of the quadrature oscillator is about 7 dB better than that of the stand-alone sub-harmonic oscillator. The quadrature oscillator has been implemented in 0.25 um CMOS process and the measured results show that the proposed quadrature oscillator could achieve a phase noise of −130 dBc/Hz at 1 MHz offset from 1.13 GHz carrier while only drawing an 8.0 mA current from the 2.5 V power supply.     

Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells

Leakage estimation is an important step in nano-scale technology digital design flows. While reliable data exist on leakage trends with bulk CMOS technology scaling in stand-alone devices and circuits, there is a lack of public domain results on the effect of scaling on leakage power consumption for a complete standard cell set. We present an analysis on a standard cell library applying a logic-level estimation model, supported by SPICE BSIM4 comparison. The logic-level model speedup over SPICE is >10³ with average accuracy below 1% error. We therefore explore the effects of scaling on the whole standard cell set with respect to different leakage mechanisms (sub-threshold, body, gate) and to input pattern dependence. While body leakage appears to be dominant, sub-threshold leakage is expected to increase more than other components with scaling. Detailed data of the whole analysis are reported for use in further research on leakage aware digital design.     

一种双控制回路低相位噪声CMOS压控振荡器设计

在集成锁相环中，压控振荡器的输出频率范围要能随所有工艺和工作条件的变化而覆盖所需的频率范围。增大压控振荡器的增益而实现宽调协范围会增加压控振荡器和锁相环的相位噪声。在这篇文章中，通过两路控制来得到压控振荡器中心频率可调，实现了非常小的压控振荡器增益。     

基于双环X波段低相噪频率合成器的设计与实现

基于相位噪声特性,对数字锁相式频率合成器进行了研究和分析。在对比传统单环锁相技术的基础上,介绍了一种双环技术的X波段低相噪锁相式频率合成器。在满足小频率步进、低杂散的情况下,设计所得到的X波段频率合成器其绝对相位噪声≤-100 dBc/Hz@1 kHz。     

Analysis and optimization of the impact of channel resistance on CMOS LNA noise performance

The intrinsic channel resistance, which is caused by the finite charging time of the carriers in the inversion layer, has remarkable impact on RF CMOS circuits, especially low noise amplifier (LNA), the first block of receiver. The impact of channel resistance on the noise performance of LNA is thoroughly studied and analyzed in this paper, and then new formulae are proposed systematically. Moreover, revised noise figure optimization technique is presented. All of this work will be very instructive for the design of high performance LNA.     

系统噪声和动态范围对激光束参数测量影响的分析

目前在激光束空域参数及传输因子的测量中，一般采用基于面阵ＣＣＤ的数字图像采集系统，本文应用计算机模拟仿真的手段，针对基模高斯光束和高阶厄米－高斯光束，分析了系统中的是电噪声和动态范围对激光束一阶四阶矩等空域参数以及Ｍ＾２因子测量精度的影响，提出了有效积分区域的概念，给出了实际工作中合理的积分范围，并通过大量的数据说明噪声和动态范围对光束测量精度影响不显著，为合理要求光电探测器和电路和系统的噪声性能     

基于估计方法的CMOS图像传感器列固定模式噪声校正方法

CMOS图像传感器的列固定模式噪声对图像质量的影响非常严重。在分析CMOS图像传感器固定模式噪声产生机理、噪声特性以及其在输出图像中的表现的基础上,提出了一种针对CMOS图像传感器中列固定模式噪声的校正方法。该方法利用CMOS图像采集系统对积分球发出的均匀平行光束进行多次采样并建模来对列固定模式噪声进行估计,然后将估计结果应用于CMOS图像硬件采集系统进行列固定模式噪声的校正,固定模式噪声的校正在FPGA中使用查找表方法实现。实验结果表明该方法可以有效消除列固定模式噪声,改善图像质量。     

标准CMOS工艺在高速模拟电路和数模混合电路中的应用展望

从速度、集成度、功耗和成本等几个方面深入的分析了利用标准CMOS工艺来设计开发高速模拟器件和混合处理芯片的现状及发展潜力。     

Size effect on the electrical conduction and noise of RuO2-based thick film resistors

Temperature dependence of sheet resistance for a generic RuO₂-based resistor with a composition of 20wt.% RuO₂-80wt.% glass (63wt.% PbO-25wt.% B₂O₃-12wt.% SiO₂) is evaluated. A combined tunnel/parallel conduction model is employed to describe the resistance behavior with respect to the temperature variation. The geometry of the resistive film, such as the aspect ratio and thickness, cast a significant effect on the electrical characteristic of the thick film assembly. It is observed that shorter resistive films exhibit smaller resistivity as compared to that of the longer film. Thinner resistive films have smaller resistivity as compared to the thicker ones. In addition,1/f noise is the dominating contribution in the thick film resistor. The presence of1/f noise can be qualitatively explained with the aid of the tunneling mechanism.     

Design of a three-stage ring-type voltage-controlled oscillator with a wide tuning range by controlling the current level in an embedded delay cell

This paper presents a new design for a three-stage voltage-controlled differential ring oscillator embedded with a delay cell for a wide tuning range from 59 MHz to 2.96 GHz by adjusting the current level in the delay cell. The ring oscillator consists of a voltage-to-current converter, coder circuit, three-stage ring with delay cells, and current monitoring circuit to extend the tuning range of the proposed voltage-controlled oscillator. Each functional block has been designed for a minimum power consumption using the TSMC 0.18 μm CMOS technology. We simulate the performances of the proposed voltage-controlled oscillator in terms of phase noise, power consumption, tuning range, and gain. Our simulation results show that the proposed oscillator has the linear frequency–voltage characteristics over a wide tuning range. At each tuning range (mode), the calculated phase noise of the proposed ring oscillator at each tuning range (mode) was −87, −85, −81, and −79 dBc/Hz at a 1 MHz offset from the center frequency. The DC power of the proposed voltage-controlled oscillator consumed 0.86–3 mW under a 1.8 V supply voltage.     

The total dose effects on the 1/f noise of deep submicron CMOS transistors

Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI （shallow trench isolation） SiO2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion.     

Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs: perspective of low temperature current testing

The increase in the off-state current for sub-quarter micron CMOS technologies is making conventional I_DDQ testing ineffective. Since natural process variation together with low-V_TH devices can significantly increase the absolute leakage value and the variation, choosing a single threshold for I_DDQ testing is impractical. One of the potential solutions is the cooling of the chip during current testing. In this paper we analyze the impact of CMOS technology scaling on the thermal behavior of different leakage current mechanisms in n-MOSFETs and estimate the effectiveness of low temperature I_DDQ testing. We found that the conventional single threshold low temperature I_DDQ testing is not effective for sub-quarter micron CMOS technologies and propose the low temperature ΔI_DDQ test method. The difference between pass and fail current limits was estimated more than 200× for 0.13-μm CMOS technology.     

非相干散射雷达的高信噪比空间物体距离测量方法

非相干散射雷达是目前地基电离层探测的强大手段, 同时在空间物体探测方面也具有重要应用前景.当空间物体回波信噪比很高时, 可以利用单个脉冲进行目标检测, 而无需相干积累.非相干散射雷达常采用相位编码脉冲, 在单个相位编码脉冲内存在多次相位翻转, 此相位翻转在接收机滤波后显示一定坡度, 通过搜索此坡度曲线上具有最大斜率的坡度点可高精度确定发射-接收回波脉冲内各对应相位翻转的时间差以及对应的距离, 对这些距离值进行加权最小二乘拟合, 即可给出该回波脉冲对应的空间物体距离及误差估计值.利用欧洲非相干散射科学联合会(European Incoherent Scatter Scientific Association, EISCAT)实测数据分析发现, 距离误差可达数十米量级, 远优于以往的基于发射-接收回波脉冲前沿时间差方法.