二维离散小波变换高效低存储VLSI架构设计*

通过改进二维离散小波变换(2D DWT)的提升算法,提出一种高效的硬件架构,可省去行列模块间的转置缓存,减少片内存储器需求,并可利用同一2D DWT架构实现JPEG 2000中的5/3和9/7 变换。对于N×N的图像（N为图像宽度）,进行5/3 变换仅需2N片内缓存,进行9/7变换仅需4N片内缓存,关键路径为一个乘法器的延时。与已有的2D DWT架构相比,本架构省去了行列模块间的转置缓存,并利用折叠技术和流水线技术降低了硬件开销,缩短了关键路径,有效提升了系统性能。     

Efficient compression algorithm for hyperspectral images based on correlation coefficients adaptive 3D zerotree coding

The authors propose an efficient compression algorithm for hyperspectral images, which is based on the correlation coefficients adaptive asymmetric tree three-dimensional (3D) set partitioning in hierarchical trees (AT-3DSPIHT) coding of the asymmetric 3D wavelet transform (A3D-DWT) coefficients. According to the characteristics of the correlation coefficients between adjacent spectral bands, a binary tree spectral band grouping algorithm is carried out to divide the adjacent spectral bands into different mode groups. Along with this, an appropriate A3D-DWT with the corresponding decomposition levels and a proper AT-3D zerotree are determined adaptively. Several airborne visible/infrared imaging spectrometer images are used to evaluate the proposed algorithm. Compared with the state-of-the-art 3D-DWT based algorithms, the proposed adaptive AT-3DSPIHT achieves the best compression performance at lower bit rates. Moreover, at the low correlated adjacent bands, the proposed algorithm also outperforms the 2DSPIHT algorithm.     

FPGA implementation of XOR-MUX full adder based DWT for signal processing applications

In the recent past there is a rapid development in the field of digital technology especially in signal processing and image processing based applications Excellent performance high speed, compactable in size low power and less delay are the essential needs of the devices used for applications such as signal processing, audio processing and software define radio and so on. Particularly, digital gadgets are prone to have more critical logic size and power consumption and take large area in VLSI Implementation due to arithmetic operations of adders and multiplier designs. Thus priority architecture of Digital Wavelet Transform (DWT) is affected as it comprises a number of Filter banks in level basics, thus all Filter banks have number of adders and multipliers due to coefficient decompositions of low and high pass filters. On this n-size repeated filter logic takes more logic size and power consumption. Here, the proposed work presents a novel approach of DWT by replacing conventional adders and multipliers with XOR-MUX adders and Truncations multipliers thereby reducing the 2n logic size to n-size logic. Finally, the proposed DWT architecture designed in VHDL and also implemented in FPGA XC6SLX9-2TQG144 proved the performance in terms of delay, area and power.     

低功耗并行的二维离散小波变换的VLSI结构

提出了一种基于提升算法的低功耗并行的二维离散小波变换的VLSI结构。提出结构的同时进行行和列方向的处理,不需要额外的缓存来存储用于列变换的中间变换系数。通过分时复用关键的运算功能模块,该结构同时可以对两行数据进行处理,硬件的利用率达到100%。边界对称扩展通过嵌入式电路实现,大大降低了需要的片上存储器的数量以及对片外存储器的访问,有效地降低了系统的功耗。     

支持分辨率渐进码流的无损图像编码方法

针对无损图像压缩编码,提出了一种新颖的图像分解去相关方法。当前的无损图像编码方法主要有CALIC和JPEG-LS,两者都在空域直接作预测,导致编码码流不具有分辨率可伸缩性。结合小波提升模式与边缘自适应预测研究实现了一种比二维小波变换性能更好的分解方法。首先,对图像的每一列样值进行一维小波分解;然后,对高频子带进行边缘自适应预测,减少残留的信息。针对低频子带图像进行同样的两步操作,就完成了对图像的一次二维分解。对低频图像进行多次迭代操作后即形成了对图像的一个多分辨率分解。实验结果表明,与JPEG2000的无损模式相比,由于边缘自适应预测的引入,提出的分解模式获得了明显的编码增益。     

三维建筑物重建中基于图像的非完全拓扑分析

在计算机视觉和计算机图形学中,单视图三维重建是一个很难的问题。为实现基于单幅图像的快速建筑物识别过程,提出了一种可行的、有效的三维重建方法—非完全拓扑分析。首先,对可见部分的轮廓进行分析并提取建筑形象,得到完整的拓扑结构。其次,将分割后的拓扑结构与原始数据库信息进行快速匹配。实验表明,本方法与SSDA图像匹配算法相比,大大提高了计算速度。     

高性能二维9/7离散小波变换VLSI结构

为了降低二维小波变换中的存储消耗并同时提高电路处理速度,提出了一种二维并行的VLSI结构。通过充分挖掘二维变换中行变换和列变换之间的关系,优化了行变换核和列变换核的并行数据扫描输入方式,将9/7小波变换的中间存储降低至4N。同时,采用基于翻转格式的流水线技术,将电路的关键路径缩短至一级乘法器延时,有效地提高了电路处理速度,并通过伸缩电路合并的优化方法将乘法器个数降低至10个,从而有效地减少了硬件资源消耗。     

Efficient parallel architecture for multi-level forward discrete wavelet transform processors

A resource efficient and high-performance architecture for a two-dimensional multi-level discrete wavelet transform processor is presented in this paper. The JPEG2000 standard integer lossless 5-3 filter has been implemented. It achieves optimal hardware utilisation with minimal combinational logic block slices and high frequency of operation. To reduce the hardware complexity and to achieve high performance the proposed architecture implements lifting scheme with a single multiplier-free processing element to perform both predict and update operations. Symmetric extension is used at image boundaries without requiring any extra clock cycle. The generic architecture is very flexible and can perform up to five levels of forward transform on any arbitrary image size. Synthesis of the 5-level architecture on Xilinx Virtex 5 FPGA shows that the processor can achieve a maximum frequency of operation of 221.44 MHz. The reduced hardware complexity and high frequency of operation render the design suitable for incorporation in image processing applications requiring fast operations. The 5-level design has been successfully implemented on a Xilinx Spartan 3E FPGA, utilising only 1104 slices for a 512-by-512 pixel test image, the lowest hardware requirements for a 5-level discrete wavelet transform processor reported to date.     

Fast 3D wavelet transform on multicore and many-core computing platforms

The three-dimensional wavelet transform (3D-DWT) has focused the attention of the research community, most of all in areas such as video watermarking, compression of volumetric medical data, multispectral image coding, 3D model coding and video coding. In this work, we present several strategies to speed up the 3D-DWT computation through multicore processing. An in depth analysis of the available compiler optimizations is also presented. Depending on both the multicore platform and the GOP size, the developed parallel algorithm obtains efficiencies above 95 % using up to four cores (or processes), and above 83 % using up to 12 cores. Furthermore, the extra memory requirements is under 0.12 % for low resolution video frames, and under 0.017 % for high resolution video frames. In this work, we also present a CUDA-based algorithm to compute the 3D-DWT using the shared memory for the extra memory demands, obtaining speed-ups up to 12.68 on the many-core GTX280 platform. In areas such as video processing or ultra high definition image processing, the memory requirements can significantly degrade the developed algorithms, however, our algorithm increases the memory requirements in a negligible percentage, being able to perform a nearly in-place computation of the 3D-DWT whereas in other state-of-the-art 3D-DWT algorithms it is quite common to use a different memory space to store the computed wavelet coefficients doubling in this manner the memory requirements.     

基于Lifting的小波变换通用硬件实现方法研究

文章提出了一套完整的基于Lifting算法小波通用硬件实现的流程。该方法系统分析了目前基于Lifting算法小波实现过程中的有限精度分析,基本一维、两维小波变换结构设计以及常用优化算法,提炼出了一套小波设计的通用方法。该文将以6/10小波变换为例介绍该方法的具体实现过程,为设计者提供了一整套设计一个高性能小波可遵循的流程,它可以应用于小波变换的硬件设计以及相关的基于小波变换的信号处理系统设计。     

提升小波变换的三种算法性能比较

离散小波变换(DWT)在语音,图像等信号处理中有着广泛的应用,在JPEG2000标准中就推荐采用5/3和9/7小波来分别进行无损和有损图像压缩,取代基于DCT变换的图像压缩,并且还推荐采用提升方法来实现。提出三种基于提升方法的二维离散小波变换的并行算法,并在超常超标量数字指令(VLIW)的数字信号处理器(DSP)上进行了性能方面的比较。这里,我们以在图像压缩中常用的不同分辨率的图像作为实验对象。实验结果表明,此三种算法对图像数据进行小波变换的处理时间有了明显缩短,并且实现在参数空间的不同点上都得到更好的效果。     

Machine Learning-Based Pruning Technique for Low Power Approximate Computing

Approximate Computing is a low power achieving technique that offers an additional degree of freedom to design digital circuits. Pruning is one of the types of approximate circuit design technique which removes logic gates or wires in the circuit to reduce power consumption with minimal insertion of error. In this work, a novel machine learning (ML) -based pruning technique is introduced to design digital circuits. The machine-learning algorithm of the random forest decision tree is used to prune nodes selectively based on their input pattern. In addition, an error compensation value is added to the original output to reduce an error rate. Experimental results proved the efficiency of the proposed technique in terms of area, power and error rate. Compared to conventional pruning, proposed ML pruning achieves 32% and 26% of the area and delay reductions in 8*8 multiplier implementation. Low power image processing algorithms are essential in various applications like image compression and enhancement algorithms. For real-time evaluation, proposed ML optimized pruning is applied in discrete cosine transform (DCT). It is a basic element of image and video processing applications. Experimental results on benchmark images show that proposed pruning achieves a very good peak signal-to-noise ratio (PSNR) value with a considerable amount of energy savings compared to other methods.     

基于翻转结构的离散小波变换片上系统设计验证

论文研究了二维提升结构9／7小波变换模块电路实现;通过分析小波变换过程中数据流格式及输入输出规律,指出可基于片上系统软硬件协同地完成小波变换;据此设计了基于翻转结构的一维小波变换专用处理电路用于水平方向一维小波变换;通过嵌入式软核读取中间结果,用于垂直方向一维小波变换。对标准图像的测试结果表明：平均仅需4ms-5ms时间即可完成512×512大小图像的9／7小波变换,具有较高的工程实用价值。     

基于提升框架的实时视频降噪方法

针对基于离散小波变换的视频降噪方法难于实时处理的问题,提出了一种基于提升框架的可实时处理的视频降噪方法。首先,对每帧图像利用提升框架进行多级小波分解,得到尺度系数和小波系数;然后,对不同层次的小波系数采用软阈值收缩方法进行滤波;小波逆变换后,利用时间域滤波方法进一步提高降噪效果。实验结果表明,该方法具有较好的实时性和去噪效果。     

基于PDF417和提升小波的数字图像水印算法

根据PDF417与提升小波变换的特点,提出一种基于PDF417和提升小波变换的数字图像水印算法。首先将水印信息进行PDF417编码,并在密钥控制下进行混沌序列置乱后得到二值水印图像;最后使用小波提升技术对原始图像进行小波三级变换,在小波变换域低频子带中嵌入二值水印图像。实验结果证明：该算法能很好地保持图像质量,对常见的图像处理具有很强的鲁棒性,同时不仅能保持传统小波多分辨率图像水印的优势,而且处理速度更快,对图像尺寸没有特殊要求。     

Novel robust image watermarking based on subsampling and DWT

This paper presents a robust digital image watermarking scheme based on subsampling and DWT. Subsampling is firstly used to construct a subimage sequence as a video segment. Then, a random watermark sequence satisfied with Gaussian distribution is block-wised embedded into the DWT domain of these subimages repeatedly using the video watermarking technique. And watermark is detected through computing correlation between watermark and watermarked frames. The experiment results demonstrate that the proposed scheme achieves good robustness against JPEG compression, common image processing operation and geometric distortions. Furthermore, the proposed watermarking scheme is also robust against linear collusion and other video watermarking attacks.     

An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing

In order to guarantee both performance and programmability demands in 3D graphics applications, vector and multithreaded SIMD architectures have been employed in recent graphics processing units. This paper introduces a novel instruction-systolic array architecture, which transfers an instruction stream in a pipelined fashion to efficiently share the expensive functional resources of a graphics processor. Specifically, cache misses and dynamic branches can cause additional latencies and complicated management in these parallel architectures. To address this problem, we combine a systolic execution scheme with on-demand warp activation that handles cache miss latency and branch divergence efficiently without significantly increasing hardware resources, either in terms of logic or register space. Simulation indicates that the proposed architecture offers 25% better performance than a traditional SIMD architecture with the same resources, and requires significantly fewer resources to match the performance of a typical modern vector multi-threaded GPU architecture.     

图像小波分解的FPGA实现

小波分析作为信号处理领域中的一种重要方法,在信号处理、模式分析和图像处理等方面得到了广泛的应用。然而小波变换巨大的运算量却使得它在实时处理领域中的应用受到了限制。本文根据离散小波变换的Mallat算法,提出了一种EPGA实现高速小波分解的方法,设计出的小波变换模块结构清晰而且规则,易于级联,可实现多级变换。同时,,运算精度和处理速度均满足实时图像处理的要求。     

基于方向提升小波变换的多描述视频编码

提出一种基于方向提升小波变换的多描述可分级视频编码方法,该方法能增强视频编码的容错性和网络自适应性。对视频序列中的每一帧图像按梅花下采样产生2个子序列,对每个子序列分别进行三维小波可分级视频编码形成2个描述。为解决传统二维小波变换方法对梅花下采样图像编码效率低的问题,引入方向提升小波变换对图像进行空域分解,提出5模式方向提升小波变换以进一步提高编码效率。实验结果证明了该方法的有效性。     

Neural network method: delay and system of delay differential equations

In the present article, delay and system of delay differential equations are treated using feed-forward artificial neural networks. We have solved multiple problems using neural network architectures with different depths. The neural networks are trained using the extreme learning machine algorithm for the satisfaction of delay differential equations and associated initial/boundary conditions. Further, numerical rates of convergence of the proposed algorithm are reported based on variation of error in the obtained solution for different number of training points. Emphasis is on analysing whether deeper network architectures trained with extreme learning machine algorithm can perform better than shallow network architectures for approximating the solutions of delay differential equations.