采用噪声抵消技术的无电感宽带低噪声放大器

设计了一款多用途、宽带、无电感的低噪声放大器。放大器的第1级为单端输入差分输出结构,采用了噪声抵消技术来降低噪声;第2级引入有源感性负载,并通过电阻负反馈来扩展带宽。采用TSMC 130 nm工艺对电路进行仿真,后仿结果表明,在0.4~6.2 GHz带宽范围内,S21为19 dB,噪声系数为1.9~2.5 dB,功耗为9.6 mW,电路核心面积为0.08 mm²。     

一种具有新型增益控制技术的CMOS宽带可变增益LNA

高速超宽带无线通信的多标准融合是未来射频器件的发展趋势,该文提出一种基于CMOS工艺、具有新型增益控制技术的宽带低噪声放大器(LNA),采用并联电阻反馈实现宽带输入匹配,并引入噪声消除技术来减小噪声以提高低噪声性能;输出带有新型6位数字可编程增益控制电路以实现可变增益。采用中芯国际0.13m RF CMOS工艺流片,芯片面积为0.76 mm2。测试结果表明LNA工作频段为1.1-1.8 GHz,最大增益为21.8 dB、最小增益8.2 dB,共7种增益模式。最小噪声系数为2.7 dB,典型的IIP3为-7 dBm。     

CMOS 射频低噪声放大器的设计

讨论了CMOS射频低噪声放大器的相关设计问题,对影响其增益、噪声系数、线性度等性能指标的因素进行了分析,并综述了几种提高其综合性能指标的方法。在此基础上,采用SMIC0．25μm CMOS工艺库,给出了3．8GHz CMOSLNA的设计方案。HSPICE仿真结果表明：电路的功率增益为13．48dB,输入、输出匹配良好,噪声系数为2．9dB,功耗为46．41mw。     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS

In this work, design and measurement results of UHF RF frontend circuits to be used in low-IF and subsampling receiver architectures are presented. We report on three low noise amplifiers (LNA) (i) single-ended (ii) differential (iii) high-gain differential and a double-balanced mixer all implemented in 0.35-μ m SOI (Silicon on Insulator) CMOS technology of Honeywell. These circuits are considered as candidate low-power building blocks to be used in the two fully-integrated receiver chips targeted for deep space communications. Characteristics of square spiral inductors with high quality (Q) factors (as high as 10.8) in SOI CMOS are reported. Single-ended and fully-differential LNA's provide gains of 17.5 dB and 18.74 dB at 435 MHz, respectively. Noise figure of the single-ended LNA is 2.91 dB while the differential LNA's noise figure is 3.25 dB. These results were obtained for the power dissipations of 12.5 mW and 16.5 mW from a 2.5-V supply for the single-ended and differential LNA's, respectively. High-gain low-power differential LNA provides a small-signal gain of 45.6 dB with a noise figure of 2.4 dB at 435 MHz. Total power dissipation of the high gain LNA is 28 mW from a 3.3-V supply. The double-balanced mixer provides a conversion gain of 5.5 dB with a noise figure of 13 dB at 2 MHz IF. The power dissipation of the mixer is 11.5 mW from a 2.5-V supply. The measured responses and the power dissipations of the building blocks meet the requirements of the communications system. The die areas occupied by the single-ended LNA, differential LNA, high-gain LNA and the mixer are 0.6 mm × 1.4 mm, 1 mm × 1.4 mm, 1.4 mm × 1.2 mm and 0.6 mm × 0.9 mm, respectively. Ertan Zencir received the B.Sc. and M.S. degrees in electrical and electronics engineering from Middle East Technical University, Ankara, Turkey, and Ph.D. degree in electrical engineering from Syracuse University, Syracuse, NY in 1995, 1997, and 2003, respectively. He joined the Electrical Engineering and Computer Science Department of University of Wisconsin-Milwaukee as an Assistant Professor in August 2004. 2003). His current research focuses on RFIC and transceiver design for wireless communications. Douglas Te-Hsin Huang was born in Chia-yi Taiwan. He received the B.S. degree in electrical engineering from National Taiwan Ocean University, Kee-lung, Taiwan in 1993, and the M.S. and Ph.D. degrees in electrical engineering from Syracuse University, Syracuse, New York, in 2001 and 2003, respectively. In 2004, he joined Skyworks Solutions Inc., where he is currently an RFIC Design Engineer. His research deals mainly with low-power, infrastructure, analog RFIC, and microwave integrated circuit designs. Besides microwave and semiconductor engineering, Dr. Huang has broad interest in art, music, and philosophy. Ahmet Tekin received his B.S. degree in Electrical Engineering from Bogazici University, Istanbul, Turkey in 2002 and MS degree in Electrical engineering form North Carolina A&T State University, Greensboro, NC. He is currently working towards his PhD degree at University of California, Santa Cruz, CA. He was a Research Assistant at RF Microelectronic Laboratory, North Carolina A&T State University, from 2002 to 2004. He worked on the design of low power UHF transceiver circuits for space applications. He is currently a Research Assistant at Bio-mimetic Microelectronic Systems Laboratory, University of California at Santa Cruz, working on implantable very low power UHF frequency transceiver for a body sensor network. Numan S. Dogan received the B.Sc. degree from Karadeniz Technical University, Trabzon, Turkey, in 1975, the M.Sc. degree from Polytechnic University, New York, in 1979, and the PhD degree from the University of Michigan, Ann Arbor, in 1986, all in electrical engineering. Since 1998, he has been with the Electrical and Computer Engineering Department, North Carolina A&T State University, Greensboro, North Carolina, where he is an Associate Professor. He was a Visiting Faculty Researcher at Air Force Research Laboratory (AFRL), Eglin Air Force Base, Florida, in 1998, and General Electric Corporate Research and Development Laboratory, Schenectady, New York, in 1999. His earlier research interests included microwave and millimeter-wave solid-state devices and circuits, high-temperature electronics, and silicon micromachining. His recent research interests include RF CMOS Integrated Circuits and low-power Medical Implant Communication Systems (MICS) transceivers. Currently he serves as the Chair of the IEEE Central North Carolina Section. In April 2004, he organized “a walking robot competition” for High School Students. He enjoys hiking to Alpine Lakes in the Pacific Northwest and fishing. Ercument Arvas (M'85–SM'89) received the B.S. and M.S. degrees from METU, Ankara, Turkey, in 1976 and 1979, respectively, and the Ph.D. degree from Syracuse University, Syracuse, New York, in 1983, all in Electrical Engineering. Between 1984 and fall of 1987, he was with the Electrical Engineering Department of Rochester Institute of Technology, Rochester, New York. He joined the Electrical Engineering and Computer Science Department of Syracuse University in 1987, where he is currently a Professor. His research interests include numerical electromagnetics, antennas, and microwave circuits and devices.     

一种零中频通用射频前端的设计及实现

摘要：本文采用零中频结构针对800～2400MHz工作频段设计了一种通用射频前端,该射频前端在一款高性能解调器的基础上,加入宽带低噪声放大器、程控射频AGC电路、电调谐预选滤波器等电路,从而实现灵敏度优于-100dBm/5MHz,动态范围大于100dB的设计指标要求。     

一种基于噪声抵消技术的宽带低噪声放大器

设计了一种应用于全球数字广播 (Digital Radio Mondiale,DRM)和数字音频广播 (Digital Audio Broadcasting,DAB) 的宽带低噪声放大器.采用噪声抵消结构,抵消输入匹配器件在输出端所产生的热噪声和闪烁噪声,使输入阻抗匹配和噪声优化去耦.电路采用华润上华CSMC 0.6 μm CMOS工艺实现.测试结果表明,3 dB带宽为100 kHz～213 MHz,最大增益为16.2 dB, S11和S22小于-7.5 dB, 最小噪声系数为3.3 dB, 输入参考的1 dB增益压缩点为-3.8 dBm,在5 V电源电压下,功耗为51 mW,芯片面积为0.18 mm2.     

低功耗CMOS低噪声放大器的设计

针对低功耗电路设计的需求,提出了一种低功耗约束下CMOS低噪声放大器的设计方法,并与传统的设计方法进行了对比。模拟结果表明,按照该方法基于0.18μm CMOS工艺设计的工作于1.58 GHz的低噪声放大器,在仅消耗1.9 mA电流的条件下,噪声指数小于1 dB。     

Low-Noise Design for Wideband Front-End Circuits and Systems of Optical and Microwave Receivers

Analog front-end circuits and systems is becoming increasingly important as technology continues to wideband. In this paper, based on the two-port equivalent noise models, a modularized method is developed to fast and accurate noise analysis and design of preamplifier, which is the most critical building block in the front-end circuits. A fundamental noise model is En - In model. Using the En - In model data, all noise performance indexes can be predicted easily. Moreover, the correlation coeffi- cient between En and In is assumed to be a complex here, not a real in the conventional, for the accurate estimation of optimum source impedance. In addition, the matching networks and noise canceling technique for wideband appli- cation are overviewed and summarized here. Finally, the illustrative experiments verify that the proposed technique has a significant potential use for high sensitivity receivers.     

Two CMOS LNAs Sharing the Same On-Chip Inductors and Bias Network

An area-efficient design for two 2.4 GHz CMOS LNAs is presented, by sharing the on-chip inductors and bias network. Compared with LNA1, LNA2 features a new technique to improve the linearity of CMOS LNA, achieving a much higher IIP3 with the tradeoff of voltage gain and noise figure.     

应用于无线传感器网络低噪声放大器的设计

本文给出一种应用于无线传感器网络射频前端低噪声放大器的设计,采用SMIC0．18μmCMOS工艺模型。在CadenceSpectre仿真环境下的仿真结果表明：该低噪声放大器满足射频前端的系统要求,在2．45GHz的中心频率下增益可调,高增益时,噪声系数为2．9dB,输入P1dB压缩点为-19．8dBm,增益为20．5dB;中增益时,噪声系数为3．6dB,输入P1dB压缩点为-15．8dBm,增益为12．5dB;低增益时,噪声系数为6．0dB,输入P1dB压缩点为-16．4dB,增益为2．2dB。电路的输入输出匹配良好,在电源电压1．8V条件下,工作电流约为6mA。     

北斗导航接收机LNA的设计与仿真

为了实现北斗卫星导航接收机射频前端的研制,根据接收机射频模块系统指标要求,包括增益、噪声系数、灵敏度等关键指标要求,提出一种基于ATF54143的LNA设计方案,采用两级结构,源极传输线负反馈稳定技术,实现输入最佳噪声匹配,输出共轭匹配设计,并用ADS软件进行仿真,得到增益32dB,噪声系数0.45dB,输入驻波比1.5。     

C波段CMOS射频前端电路设计与实现

设计了一款工作在C波段(4.2 GHz)的CMOS射频前端电路,电路包括低噪声放大器和Gilbert型有源双平衡混频器.其中低噪声放大器采用共源和共栅放大器方式,实现了单端输入到差分输出的变换;而混频器的输出端采用电感负载形式.电路采用SMIC 0.18μmRF工艺实现,测试结果表明,混频器的输出频率约为700 MHz,电路的功率增益为24 dB,单边带噪声指数为8 dB,在1.8 V工作电压下,电路总功耗为36 mW.     

1GHz 0.5μm CMOS低噪声放大器的设计

从低噪声放大器(L NA)的设计原理出发,提出并设计了一种工作于1GHz的实用L NA.电路采用共源-共栅的单端结构,用HSPICE软件对电路进行分析和优化.模拟过程中选用的器件采用TSMC0 .5 μm CMOS工艺实现.模拟结果表明所设计的L NA功耗小于15 m W,增益大于10 d B,噪声系数为1.87d B,IIP3大于10 d Bm,输入反射小于- 5 0 d B.可用于1GHz频段无线接收机的前端     

433MHz ASK接收机射频前端电路设计

设计了一款应用在433MHz ASK接收机中的射频前端电路。在考虑了封装以及ESD保护电路的寄生效应的同时,从噪声、匹配、增益和线性度等方面详细讨论了低噪声放大器和下混频器的电路设计。采用0.18μm CMOS工艺,在1.8V的电源电压下射频前端电路消耗电流10.09 mA。主要的测试结果如下:低噪声放大器的噪声系数、增益、输入P1dB压缩点分别为1.35 dB、17.43 dB、-8.90dBm;下混频器的噪声系数、电压增益、输入P1dB压缩点分别为7.57dB、10.35dB、-4.83dBm。     

A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 m CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm².     

0.13微米CMOS双通道超宽带低噪声放大器设计

本文设计了一款超宽带低噪声放大器,并对设计流程进行分析仿真.该低噪放采用双通道结构,有效的输入阻抗匹配、平稳的增益和低噪声等性能可以同时实现.应用ADS工具TSMC 0.13μm CMOS工艺库的仿真结果表明,其最大功率增益为14.2dB,在8GHz频点的IIP3为-4dBm,输入、输出反射系数分别小于-10.2dB和-10.89dB,噪声指数单调下降到1.46dB,并且总功耗和带内最大增益摆幅较低.     

CMOS single-ended-to-differential low-noise amplifier

In this work, a low-power single-ended-to-differential low-noise amplifier (LNA) is reported. The circuit has been designed and optimized to be included in an IEEE 802.15.4 standard receiver. In order to minimize power consumption, active loads and currents mirrors have been replaced by optimized inductors and transformers. Moreover, an exhaustive study of the mixed-mode parameters has been carried out, enabling the definition of single-ended figures of merits in terms of mixed-mode S-parameters. The LNA has been implemented using a 0.35 μm RFCMOS technology. Performances are a noise figure of 4.3 dB, a power gain of 21 dB, and a phase balance of 180±1°. Regarding non-linear behaviour, the obtained 1 dB-compression point obtained is −9.5 dB m while intermodulation intercept point is −3 dB m, dissipating 6 mA from 1.5 V supply voltage.     

带自动增益控制的射频前端在CMMB U/V频段接收器中的应用

-本篇文章提出一种带自动增益控制(AGC)和数字控制射频可变增益放大器(RFVGA)的射频前端结构。这种前端结构是应用在中国移动多媒体广播(CMMB)直接下变频接收器中的。RFVGA提供了50dB的增益范围,每一步增益变化为1.6dB。所采用的AGC策略可以改善在CMMB系统中很关键的邻道信号抑制。射频前端由低噪声放大器(LNA), RFVGA,混频器(mixer), 以及AGC 组成。在LNA工作在低增益模式,RFVGA工作在中等增益模式时,射频前端的输入三阶交调点(IIP3)可以达到4.9dBm;当LNA与RFVGA都工作在最高增益模式时,射频前端的双边带噪声系数(NFdsb)低于4dB。本文所展示的射频前端采用0.35μm BiCMOS 工艺制作,电源电压3V,消耗电流25.6mA。     

一种2.4 GHz CMOS射频前端电路

基于0.18 μm CMOS工艺,设计了一种面向低速率低功耗应用的2.4 GHz射频前端电路,包含2个单刀双掷开关、1个功率放大器和1个低噪声放大器。采用栅衬浮动电压偏置技术对传统单刀双掷开关进行了改进,以提高其线性度;功率放大器采用两级放大结构,对全集成的低噪声放大器进行了噪声优化;集成了输入输出匹配网络,采用了到地电感,以提高输入输出端的ESD性能。在接收模式时,电路的静态电流为10.7 mA,增益为11.7 dB,IIP3为2.1 dBm,噪声系数为3.4 dB。在发射模式时,电路的静态电流为17.4 mA,功率增益为17.7 dB,输出P1dB为20 dBm,饱和功率为21.4 dBm,最大PAE为23.8%,在输出功率为20 dBm时的频谱满足802.15.4协议要求。