Spectral-Encoded UWB Communication Systems: Real-Time Implementation and Interference Suppression

This paper considers a particular implementation of an ultra-wideband communication system that uses spectral encoding as both the multiple-access scheme and the interference-suppression technique. The main advantage of this technique is that the transmitted signal spectrum can be conveniently shaped to suppress narrowband interference and to not cause noticeable interference to overlaid systems. An extensive analysis of a possible implementation of this system by using surface acoustic-wave models is presented, and general expressions for the system performance are obtained. Numerical results show that a significant improvement in the system performance is obtained when the proposed interference-suppression method is used.     

Jitter tolerance calibration for high-speed serial interfaces

A jitter tolerance calibration test bench suitable for high speed serial interfaces (HSSI) using verilog-AMS is proposed in this paper. The jitter tolerance simulation environment can be easily parameterized in order to be compliant to any HSSI standard specification. As an example, the proposed solution is applied for the jitter tolerance simulation and characterization of the most updated M-PHY ver.3 HSSI standard for mobile applications. A comprehensive method for the calculation of the jitter noise frequency ingredients and the calibration of jitter noise sources is also proposed resulting a jitter tolerance mask compliant with the M-PHY ver.3 specifications. Using the proposed implementation the transistor level and behavioral modules co-simulation time could be significantly minimized.     

Synthesis of hazard-free control circuits from asynchronous finite state machines specifications

We discuss a special class of state machine specifications called Asynchronous Finite State Machines (AFSM) which allows the specification and synthesis of hazard-free control circuits under the unbounded delay model. AFSM are useful for the specification of sequential behavior involving choices. In contrast, models such Signal Transition Graphs (STGs) are more amenable to the specification of deterministic concurrent behavior.AFSM specifications are transformed into STGs and then to State Graphs (SGs). At the SG level of representation, hazards can be identified as a type of violations of the Complete State Coding (CSC) property. Algorithms for obtaining SGs from AFSMs, and conditions for hazard-free implementation of SG derived from AFSM are discussed. A hazard-free synthesis technique from SG is described. A CAD prototype called CLASS (Cirrus Logic Asynchronous Synthesis System) has been built and used to successfully synthesize and verify the state machine benchmark from HP Laboroatories [1] and various other real applications.     

A General Approach to Sampled-Data Modeling for Power Electronic Circuits

A general sampled-data representation of the dynamics of arbitrary power electronic circuits is proposed to unify existing approaches. It leads, via compact and powerful notation, to disciplined modeling and straightforward derivation of small-signal models that describe perturbations about a nominal cyclic steady state. Its usefulness is further illustrated by considering the representation and analysis of a class of symmetries in circuit operation. The results of the application of this methodology to modeling the small-signal dynamics of a series resonant converter are described. The results correlate well with simulation results obtained on the Massachusetts Institute of Technology's Parity Simulator. What is of greater significance is the fact that the small-signal model is obtained in a completely routine way, starting from a general formulation and working down to the actual circuit; this contrasts with the circuit-specific analyses that are more typical of the power electronics literature. The automatability of this procedure is also discussed, and it is pointed out that the key ingredients for automatic generation of dynamic models from a circuit specification are now available.     

Frequency Response Verification of Analog Circuits Using Global Optimization Techniques

This paper develops a new formal technique to verify the frequency response of analog circuits using global optimization techniques. Since simulation-based approaches are unable to cover the design space, there is a need for formal approaches to verify large circuits. Drawing parallels from the digital domain, the verification problem in the analog domain is modeled as a non-linear optimization problem and solved using global optimization techniques by ensuring that the implementation response is bounded within an envelope around the specification. We also address the problem of verifying frequency response under the influence of parameter variations. Direct as well as indirect techniques are illustrated using accurate frequency response models. Experimental results are presented to show the effectiveness of the proposed methodology.     

Design of minimum-phase digital filters as the sum of two allpass functions using the cepstrum technique

A new and practical approach using the cepstrum technique is proposed in the design of minimum-phase digital filters as the sum of two allpass functions. The desired magnitude response is specified in the frequency domain. Its corresponding minimum-phase response is then obtained from the desired magnitude response. The desired phases for the two allpass filters are obtained from the magnitude and phase responses. For both filters to be stable, the corresponding denominator polynomials are minimum phase. The filter coefficients are obtained from the desired phases using the cepstrum technique. Design examples show that the method works well for both classical filter specification and general magnitude specification in the frequency domain.     

Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming

In this paper, a novel optimization technique is proposed to optimize filter coefficients of linear phase finite-impulse response (FIR) filter to share common subexpressions within and among coefficients. Existing approaches of common subexpression elimination optimize digital filters in two stages: first, an FIR filter is designed in a discrete space such as finite wordlength space or signed power-of-two (SPT) space to meet a given specification; in the second stage, an optimization algorithm is applied on the discrete coefficients to find and eliminate the common subexpressions. Such a two-stage optimization technique suffers from the problem that the search space in the second stage is limited by the finite wordlength or SPT coefficients obtained in the first stage optimization. The new proposed algorithm overcomes this problem by optimizing the filter coefficients directly in subexpression space for a given specification. Numerical examples of benchmark filters show that the required number of adders obtained using the proposed algorithm is much less than those obtained using two-stage optimization approaches.     

Lightpath Establishment Without Wavelength Conversion Based on Aggressive Rank Accounting in Multi-Domain WDM Networks

In multi-domain WDM networks, in order to establish inter-domain lightpaths across multiple domains without wavelength conversion, a lightpath establishment method based on rank accounting has previously been proposed. With the method, the inter-domain lightpaths are established with small blocking probability based on ranking databases for wavelengths; however, the performance of the method deteriorates when the ranking databases are not frequently updated. In this paper, we propose a lightpath establishment method based on aggressive rank accounting so that ranking databases are updated frequently. In the proposed method, border-node information is used in addition to wavelength usage information, and ranking databases for multiple nodes are updated simultaneously every time a lightpath establishment is processed. From the border-node information, accuracies of the wavelength usage information for each node are computed, and then the ranking database for each node is updated with the wavelength usage information and the computed accuracies. With the updated ranking database, each source node establishes an inter-domain lightpath without wavelength conversion to its destination node across multiple domains. We also present two implementations of the proposed method toward its practical use based on RSVP-TE signaling. We evaluate by simulation the performance of the proposed method, and we show that the proposed method provides smaller blocking probability than the conservative, conventional method when inter-domain lightpaths are not frequently established. We also show that the proposed method still provides smaller blocking probability even if routes of the inter-domain lightpaths change. Finally, we show that the performance of the proposed method is insensitive to the two implementations.     

A simplified CAD of millimeter-wave diplexer with E-plane T-junction and all-metal insert filters

An equivalent circuit theory design of a class of rectangular waveguide E-plane T-junction diplexer with E-plane all-metal insert filters is presented. Element values of equivalent circuit models of E-plane T-junction proposed in [1] are computed and approximated. The parameters of the filters designed by [2] are also given. By use of the network combining technique, the scattering matrix of the diplexer is obtained and optimized according to the diplexer specification with a novel objective function. The experimental results show a fairly good agreement with the computed results.     

Formal verification of timed systems: a survey and perspective

An overview of the current state of the art of formal verification of real-time systems is presented. We discuss commonly accepted models, specification languages, verification frameworks, state-space representation schemes, state-space construction procedures, reduction techniques, pioneering tools, and finally some new related issues. We also make a few comments according to our experience with verification tool design and implementation.     

Initialization issues in asynchronous circuit synthesis

A design specification is said to be functionally uninitializable if an initializable implementation cannot be obtained. Due to the absence of any initialization sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for uninitializable circuits. We present a novel procedure for synthesizing initializable asynchronous circuits from functionally uninitializable Signal Transition Graphs (STG). After characterizing the necessary conditions for functional uninitializability, we propose a technique that transforms the original STG into an equivalent, functionally initializable STG. We show that the presence of concurrency provides the designer with an extra degree of flexibility when implementing the circuit. It is shown that initializability can be achieved by sacrificing minimal concurrency and without violating the syntactic properties of the STG required for a hazard-free implementation. The synthesis of a trigger module illustrates this procedure.A preliminary version was presented at the International Conference on Computer Design, October 1994.     

Reliability Modeling Using SHARPE

Combinatorial models such as fault trees and reliability block diagrams are efficient for model specification and often efficient in their evaluation. But it is difficult, if not impossible, to allow for dependencies (such as repair dependency and near-coincident-fault type dependency), transient and intermittent faults, standby systems with warm spares, and so on. Markov models can capture such important system behavior, but the size of a Markov model can grow exponentially with the number of components in this system. This paper presents an approach for avoiding the large state space problem. The approach uses a hierarchical modeling technique for analyzing complex reliability models. It allows the flexibility of Markov models where necessary and retains the efficiency of combinatorial solution where possible. Based on this approach a computer program called SHARPE (Symbolic Hierarchical Automated Reliability and Performance Evaluator) has been written. The hierarchical modeling technique provides a very flexible mechanism for using decomposition and aggregation to model large systems; it allows for both combinatorial and Markov or semi-Markov submodels, and can analyze each model to produce a distribution function. The choice of the number of levels of models and the model types at each level is left up to the modeler. Component distribution functions can be any exponential polynomial whose range is between zero and one. Examples show how combinations of models can be used to evaluate the reliability and availability of large systems using SHARPE.     

Towards automated implementation of adaptive systems from abstract SystemC specifications

Adaptivity is a key feature in embedded systems which requires explicit support in Electronic System-Level (ESL) design methodologies. Similarly, a higher level of abstraction during system specification is crucial for enabling ESL design activities such as Design Space Exploration. This has motivated the development of methodologies, such as A-HetSC, for enabling SystemC abstract specification of the adaptive parts of a system. However, in order to enable practical ESL design flows, it is essential to enable suitable implementation paths from the abstract adaptive specification. Otherwise, the cost of manual refinement of the abstract adaptive specification or simply the inability to systematically achieve an implementation will compromise the advantages obtained by the abstract model. This paper presents a system-level implementation methodology for tackling the implementation of the adaptive parts of an abstract SystemC specification. These adaptive parts are described as abstract adaptive processes, the basic constructs for specifying adaptivity in the A-HetSC methodology. The methodology proposes two main implementation paths. One path automatically targets an embedded SW implementation, for an immediate, flexible and cheap implementation of the adaptive processes. For the HW implementation path, a systematic SystemC-based refinement for targeting a refined model is proposed. Such a refined model is already supported by high-level synthesis tools, which automate the rest of the HW implementation path. It enables a cost efficient implementation of adaptive functionality in contexts where a software implementation does not fulfil time performance demands. The refinement of an adaptive inverse transform module, as part of an adaptive video decoder (AVD), is used as a demonstrative example.     

A Petri Net Control Unit for High-Speed Modular Signal Processors

This paper proposes a hierarchical representation of digital signal processing algorithms suitable for real-time implementations. Petri net models are used to demonstrate every possible operating parallelism in their graphical expression, the marked Petri graph. Moreover, a hierarchical algorithm execution control based on delayed Petri graphs is presented. A strictly modular system architecture suitable for VLSI implementation and data-driven processing is reviewed in its main components. The algorithm representation is then applied to the design of the control part of the system modules. Details at the logic level of the controllers for an array of digital signal processors are presented as an application of the proposed methodology.     

Generating efficient protocol code from an abstract specification

A protocol compiler takes as input an abstract specification of a protocol and generates an implementation of that protocol. Protocol compilers usually produce inefficient code both in terms of code speed and code size. We show that the combination of two techniques makes it possible to build protocol compilers that generate efficient code. These techniques are: (i) the use of a compiler that generates from the specification a unique tree-shaped automation (rather than multiple independent automata) and (ii) the use of optimization techniques applied at the automation level, i.e., on the branches of the trees. We have developed a protocol compiler that uses both these techniques. The compiler takes as the input a protocol specification written in the synchronous language Esterel. The specification is compiled into a unique automation by the Esterel front end compiler. The automation is then optimized and converted into C code by our protocol optimizer called HIPPCO. HIPPCO improves the code performance and reduces the code size by simultaneously optimizing the performance of the common path and optimizing the size of the uncommon path. We evaluate the gain expected with our approach on a real-life example, namely a working subset of the TCP protocol generated from an Esterel specification. We compare the protocol code generated with our approach to that derived from the standard BSD TCP implementation. The results are very encouraging. HIPPCO-generated code executes up to 25% fewer instructions than the BSD code for input packet processing while only increasing the code size by 25%     

Efficient statistical approach to estimate power consideringuncertain properties of primary inputs

Power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits is heavily dependent on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. Due to the complex nature of the problem, it is practically impossible to use traditional power estimation techniques to determine such bounds. In this paper, we present a novel approach to accurately estimate the maximum and minimum bounds for average power using a technique which calculates the sensitivities of average power dissipation to uncertainties in specification of primary inputs. The sensitivities are calculated using a novel statistical technique and can be obtained as a by-product of average power estimation using Monte Carlo-based approaches. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately