Γ (Gamma): A SaaS-enabled fast and accurate analog design System

With ever increasing demand for lower power consumption, lower cost, and higher performance, designing analog circuits to meet design specifications has become an increasing challenging task, Analog circuit designers must, on one hand, have intimate knowledge about the underlining silicon process technology׳s capability to achieve the desired specifications. They must, on the other hand, understand the impact of tweaking circuits to satisfy a given specification on all circuit performance parameters. Analog designers have traditionally learned to tackle design problems with numerous circuit simulations using accurate circuit simulators such as SPICE, and have increasingly relied on trial-and-error approaches to reach a converging point. However, the increased complexity with each generation of silicon technology and high dimensionality of searching for solutions, even for some simple analog circuits, have made the trial-and-error approach extremely inefficient, causing long design cycles and often missed deadlines. Novel rapid and accurate circuit evaluation methods that are tightly integrated with circuit search and optimization methods are needed to aid design productivity.Furthermore, the current design environment with fully distributed licensing and supporting structures is cumbersome at best to allow efficient and up-to-date support for design engineers. With increasing support and licensing costs, fewer and fewer design centers can afford it. Cloud-based software as a service (SaaS) model provides new opportunities for CAD applications. It enables immediate software delivery and update to customers at very low cost. SaaS tools benefit from fast feedback and sharing channels between users and developers and run on hardware resources tailored and provided for them by the software vendor. On the downside, web-based tools are expected to perform in a very short turn-around schedule and be always responsive.This paper presents a list of innovations that come together to a new class of analog design tools: 1). Lookup table-based approach (LUT) to model complex transistor behavior provides both the necessary accuracy and speed essential for repeated circuit evaluations. 2). The proposed system architecture tight integrate the novel LUT approach with novel system level functions to allow further significantly better accuracy/speed tradeoff and faster design convergence with designer׳s intent. 3). Incorporating use inputs at key junctures of the design process allows the tool to better capture designer׳s intent and improve design convergence. 4). The combination of high accuracy and faster evaluation time make it possible to incorporate SaaS features, such as short solution space navigation steps and crowdsourcing, into the tool. This allows sharing of server-side resources between many users. Instead of fully automating a signoff circuit optimization process, the proposed tool provides effective aid to analog circuit designers with a dash-board control of many important circuit parameters with several orders faster in computation time than SPICE simulations.     

Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing

Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With the component density of these devices, small analog circuits, as well as larger analog systems, can be synthesized and tested in a shorter time and at a lower cost, compared with the full design cycle. However, automated development platforms and computer-aided design tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance optimization must be recognized as an indispensable step of the analog physical synthesis flow. Our goal in this brief is to present a physical synthesis framework with an optimization core and an integrated simulation environment for verification of the synthesis results. Although SPICE has been used as the simulation tool for our experiments, there is no dependency on a particular circuit simulator. Our synthesis tool currently accepts SPICE netlists as input and gives priority to user-specified metrics when optimizing the synthesized circuit performance. Experimental results demonstrate the effectiveness of our approach.     

Measuring the uniqueness and variety of analog circuit design features

Analog circuit design activity is currently a less formalized process, in which the main source for innovation is the designer's ability to produce new designs by combining basic devices, sub-circuits, and ideas from similar solutions. There are few systematic methods that can fuse and transform the useful features of the existing designs into new solutions. Moreover, most automated circuit synthesis tools are still limited to routine tasks, like transistor sizing and layout design. Developing new design techniques that can combine the existing design features requires metrics that describe the uniqueness and variety of the features. This paper evaluates for analog circuits two such general-purpose metrics proposed in [1] and [2]. Three case studies are discussed on using the metrics to characterize the design features of current mirrors, transconductors, and operational amplifiers. The two metrics and the presented study is useful in producing an overall characterization of analog circuit features. This can help in enhancing the circuit design process, training of young designers, and developing new automated synthesis tools that can explore more solution space regions that are likely to include novel design features.     

Stability problems in universal current-mode filters

Analog circuit designers have usually focused on the design of circuits employing a minimum number of components, occupying less area and dissipating less power. However, some important issues such as signal limitations and especially stability problems of the analog circuits have not received considerable attention in the literature. Hence, the work described in this paper deals with the stability problems of two new current-mode analog filters employing multiple output current controlled conveyors (MOCCCIIs). Toward that end, a single pole model is replaced for each non-ideal current gain of the MOCCCIIs. Both of the novel universal current-mode active-C filters can simultaneously realize low-pass, band-pass and high-pass/notch filter responses. SPICE and MATLAB simulation results are given to verify the theoretical analysis.     

ARIADNE: A constraint-based approach to computer-aided synthesis and modeling of Analog integrated circuits

The ARIADNE approach to computer-aided synthesis and modeling of analog circuits is presented. It is a mathematical approach based on the use of equations. Equations are regarded as constraints on a circuit's design space and analog circuit design is modeled as a constraint satisfaction problem. To generate and efficiently satisfy constraints, advanced computational techniques such as constraint propagation, interval propagation, symbolic simulation, and qualitative simulation are applied. These techniques cover design problems such as topology construction, modeling, nominal analysis, tolerance analysis, sizing and optimization of analog circuits. The advantage of this approach is the clear separation of design knowledge from design procedures. Design knowledge is modeled in declarative equation-based models (DEBMs). Design procedures are implemented into general applicable CAD tools. The ARIADNE approach closely matches the reasoning style applied by experienced designers. The integration of synthesis and modeling into one frame and the clear separation of design knowledge from design procedures eases the process of extending the synthesis system with new circuit topologies, turning it into an open design system. This system can be used by both inexperienced and experienced designers in either interactive or automated mode.     

Analog VLSI Design Constraints of Programmable Cellular Neural Networks

Analog parallel signal processing systems, like cellular neural networks (CNN's), intrinsically have a high potential for perception-like signal processing tasks. The robust design of analog VLSI requires a good understanding of the capabilities as well as the limitations of analog signal processing. Implementation-oriented theoretical methods are described to compute the effect of all types circuit non-idealities with random or systematic causes on the static and dynamical behavior of CNN's and to derive specifications for the cell circuit building blocks. The fundamental impact of transistor mismatch on the trade-off between the speed, accuracy and power performance of CNN chips is demonstrated. A design methodology taking into account the effect of transistor mismatch is proposed and experimental results of a CNN chip implementation designed with this method are discussed.     

Enhanced analog “yields” cost-effective systems-on-chip

As device feature sizes of analog MOS circuits are reduced to the deep-submicron ranges, the effect of process variability on circuit performance and reliability is magnified. Yield is becoming more and more critical and statistical methods are required to simulate the effect of process variability to enable circuit designers to “design-in” quality through circuit robustness. More work is needed particularly in the areas of modeling and statistical CAD of submicron, low-voltage mixed-signal ICs. The characterization work needed to tune models to specific VLSI technology, implementation into the SPICE and APLAC simulators, and use in design and optimization of analog and digital VLSI circuits     

Physical modeling of lateral scaling in bipolar transistors

The dependence of important transistor characteristics, such as transit frequency, on emitter width and length is modeled on a physical basis. Closed-form explicit analytical equations are derived for modeling the emitter size dependence of the low-current minority charge and transit time, the critical current indicating the onset of high injection in the collector, and the stored minority charge in the collector at high injection. These equations are suited for application in various compact transistor models such as the SPICE Gummel-Poon model (SGPM) as well as the advanced models HICUM and MEXTRAM. As demonstrated by two- and three-dimensional device simulation and measurements, combination of the derived equations with HICUM results in accurate prediction of the characteristics of transistors with variable emitter length and width. As a consequence, the new model makes the conventional transistor library unnecessary and offers bipolar circuit designers the flexibility to use the transistor size that fits the application best     

Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.     

Simulation of optically injection-locked microwave oscillatorsusing a novel SPICE model

Optical injection-locking of GaAs field-effect transistor microwave oscillators has been examined experimentally as well as by using two different optical interaction models. An additional simulation program with IC emphasis (SPICE) circuit for observing small locking ranges is also described. This first-order interaction model which utilizes a standard version of SPICE produces predictions of injection-locking range in excellent agreement with measured results. These tools allow the oscillator designer to optimize the injection-locking performance by analyzing various circuit topologies and DC bias levels     

Analog integrated filter compilation

A review of the progress in automated design of analog integrated filters is presented. Such tools are ahead of other analog circuit automation in terms of the acceptance by designers and practical applicability. A survey of the present-day commercial and academic systems is made and the range of facilities available is compared. The problems faced in the design of this type of software are typical of the problems of analog design systems in general; lack of openness for introduction of new design knowledge, difficulties of dealing simultaneously with expert and novice users, poor integration in design environments, and user-interface problems. The structure of a typical system is studied and the computer methods used within are discussed with regard to such issues as speed, flexibility, and ease-of-use. Some future directions for analog filter compilers are proposed.     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

Review: Machine learning techniques in analog/RF integrated circuit design,synthesis, layout,and test

Rapid developments in semiconductor technology have substantially increased the computational capability of computers. As a result of this and recent developments in theory, machine learning (ML) techniques have become attractive in many new applications. This trend has also inspired researchers working on integrated circuit (IC) design and optimization. ML-based design approaches have gained importance to challenge/aid conventional design methods since they can be employed at different design levels, from modeling to test, to learn any nonlinear input-output relationship of any analog and radio frequency (RF) device or circuit; thus, providing fast and accurate responses to the task that they have learned. Furthermore, employment of ML techniques in analog/RF electronic design automation (EDA) tools boosts the performance of such tools. In this paper, we summarize the recent research and present a comprehensive review on ML techniques for analog/RF circuit modeling, design, synthesis, layout, and test.     

Calibrating simulation tools for nanometer designs

Next-generation silicon processes will challenge system-on-a-chip (SOC) designers to increase the accuracy of the data they feed to their high level tools. Minimum circuit features of 250 nm (0.25 μm) or below are demanding. The tools that simulate them will need transistor models and interconnect parameters that reflect nothing less than the actual physical properties of the process in which ICs are to be manufactured. These silicon-calibrated models can then pass their accuracy on to capable transistor-level simulation tools. Silicon calibration calls for for tighter relationships and more effective communication than is now found among silicon foundries electronic design automation (EDA) companies, and IC design groups. The EDA tools must be regularly updated, to equip design engineers to cope with the challenges of nanometer design. Although simulation tools may never predict silicon behavior with 100 percent accuracy, EDA tool vendors and IC fabrication facilities share a responsibility to calibrate their tool suites as closely as possible with actual silicon     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

基于混合遗传算法的模拟电路自动设计研究

模拟电路在电子系统设计中具有重要意义.模拟电路设计包括电路拓扑结构设计和元件值设计,这两个方面对计算机辅助模拟电路设计都很重要.但是,传统的遗传算法在不断进化电路元件值时效率低.因此,本文提出一种具有超突变和精英策略的混合遗传算法HME-GA.该方法不仅可以用来设计电路的拓扑结构,而且可用于设计电路的元件值.实验结果表明,HEM-GA算法优于简单遗传算法GA,可作为计算机辅助模拟电路设计的有效方法,在模拟电路自动化设计中具有非常重要的意义和巨大的应用潜力.     

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout.