A floating point conversion algorithm for mixed precision computations

The floating point number is the most commonly used real number representation for digital computations due to its high precision characteristics. It is used on computers and on single chip applications such as DSP chips. Double precision (64-bit) representations allow for a wider range of real numbers to be denoted. However, single precision (32-bit) operations are more efficient. Recently, there has been an increasing interest in mixed precision computations which take advantage of single precision efficiency on 64-bit numbers. This calls for the ability to interchange between the two formats. In this paper, an algorithm that converts floating point numbers from 64- to 32-bit representations is presented. The algorithm was implemented as a Verilog code and tested on field programmable gate array (FPGA) using the Quartus II DE2 board and Agilent 16821A portable logic analyzer. Results indicate that the algorithm can perform the conversion reliably and accurately within a constant execution time of 25 ns with a 20 MHz clock frequency regardless of the number being converted.     

单精度浮点数累加和误差研究

计算机中进行浮点数加法运算时,需要进行对阶和右规格化操作,该操作会进行舍入处理,这种处理过程会产生误差,浮点数累加运算会造成误差的累积,导致计算结果精度不够甚至计算结果错误。通过实验手段研究单精度浮点数累加过程中不同结合顺序对浮点数累加和误差的影响,探索结合顺序导致计算误差的规律,为多核计算、GPU计算、多处理器计算等计算范型和计算结构提供选择结合方法的依据,便于发挥其并行计算的优势。     

Delay and area efficient approximate multiplier using reverse carry propagate full adder

The performance and power of error resilient applications will rise with a decrease in designing complexness due to approximate computing. This paper includes the new method for the approximation of multipliers. Variable likelihood terms are produced by the alteration of partial products of the multiplier. Based on the probability statistics, the accumulation of altered partial products leads to the variation of logic complexity. Here the estimate is implemented in 2 variables of 16-bit multiplier and in the final stage with reverse carry propagate adder(RCPA). The reverse carry propagate adder have carry signal propagation from the most significant bit(MSB) to the least significant bit(LSB), which results in greater relevance to the input carry than the output carry. The technique of carry circulation in reverse order with delay variations increases the stability. Utilizing the RCPA in approximate multiplier provide 21% and 7% improvements in area and delay. On comparing, this structure is resilient to delay variations than the ideal approximate adder.     

An efficient micromixer actuated by induced-charge electroosmosis using asymmetrical floating electrodes

Efficient microfluid mixing is an important process for various microfluidic-based biological and chemical reactions. Herein we propose an efficient micromixer actuated by induced-charge electroosmosis (ICEO). The microchannel of this device is easy to fabricate for its simple straight channel structure. Importantly, unlike previous design featuring complicated three-dimensional conducting posts, we utilize the simpler asymmetrical planar floating-electrodes to induce asymmetrical microvortices. For evaluating the mixing performance of this micromixer, we conducted a series of simulations and experiments. The mixing performance was quantified using the mixing index, specifically, the mixing efficiency can reach 94.7% at a flow rate of 1500 µm/s under a sinusoidal wave with a peak voltage of 14 V and a frequency of 400 Hz. Finally, we compared this micromixer with different micromixing devices using a comparative mixing index, demonstrating that this micromixer remains competitive among these existing designs. Therefore, the method proposed herein can offer a simple solution for efficient fluids mixing in microfluidic systems.     

Distributions of floating point numbers

The logarithmic distribution is commonly used to model mantissae of floating point numbers. It is known that floating point products of logarithmically distributed mantissae are logarithmically distributed, while floating point sums are not. In this paper a distribution for floating point sums is derived, and for a special case of logarithmically distributed mantissae the deviation of this distribution from the logarithmic distribution is determined.     

Area and delay efficient GDI based accuracy configurable adder design

Adders are one of the basic fundamental critical arithmetic circuits in a system and their performances affect the overall performance of the system. Traditional n-bit adders provide precise results, whereas the lower bound of their critical path delay of n bit adder is Ὠ(log n). To achieve a minimum critical path delay lower than Ὠ(log n), many inaccurate adders have been proposed. These inaccurate adders decrease the overall critical path delay and improve the speed of computation by sacrificing the accuracy or predicting the computation results. In this work, a fast reconfigurable approximate ripple carry adder has been proposed using GDI (Gate Diffusion Logic) passing cell. Here, GDI cell acts as a reconfigurable cell to be either connected with the previous carry value or approximated value in an adder chain. This adder has greater advantage and it can be configured as an accurate or inaccurate adder by selecting working mode in GDI cell. The implementation results show that, in the approximate working mode, the proposed 64-bit adder provides up to 23%, 34% and 95% reductions in area, power and delay, respectively compared to those of the existing adder.     

TWFBD的浮点数编码遗传算法

近年来,有关浮点数编码遗传算法的消噪变异研究有了一定的进展,取得了一些成果。浮点数编码消噪变异的理论和方法研究一直是该领域研究的重点,需要有更新更有理论和应用价值的研究成果出现。有界域的紧小波框架用于浮点数编码消噪变异尚处于无人问津的研究领域。着重分析了有界域的紧小波框架的性质,用有界域的紧小波框架在算法中进行消噪变异操作,提出了基于有界域紧小波框架的遗传算法,并进行了实验。研究和实验结果表明,将有界域的紧小波框架用于浮点数编码消噪变异,具有可靠的理论基础,与其他方法相比,其效果也十分明显。     

Loop invariants in floating point algorithms

It will be shown that by using directed roundings resp. enclosure sets for the exact values, the loop conditions and loop invariants of numerical algorithms can be generalized for computing in a discrete screen. On this way, in spite of rounding errors, it is possible to verify the received results. Thereby only inherent properties of the algorithms are used, which moreover guarantee that the loops terminate.     

An improved maximally redundant signed digit adder

Signed digit (SD) number systems support digit-parallel carry-free addition, where the sum digits absorb the possible signed carries in {−1, 0, 1}. Radix-2^h maximally redundant SD (MRSD) number systems are particularly attractive. The reason is that, with the minimal (h + 1) bits per SD, maximum range is achieved. There are speculative MRSD adders that trade increased area and power for higher speed, via simultaneous computation of three sum digits, while anticipating one of the possible signed carries. However, the nonspeculative approach that uses carry-save two’s complement encoding for intermediate sum digits, has proved to be more efficient.In this paper, we examine three previous nonspeculative MRSD adders and offer an improved design with significant savings in latency, area consumption and power dissipation. The enhanced performance is mainly due to the elimination of sign extension of the signed carries. The latter leads to a sum matrix of positively and negatively weighted bits that normally complicate the use of standard adder cells. However, with inverted encoding of negatively weighted bits, we manage to efficiently use such cells. The claimed performance measures are supported by 0.13 μm CMOS technology synthesis.     

Novel efficient full adder and full subtractor designs in quantum cellular automata

In this study, two new full adder/full subtractor designs based on quantum-dot cellular automata technology have been proposed. By means of the presented equation for SUM and SUBTRACT operations, the new high-speed, low power, and cost efficient designs have been achieved. Even if the three-level design has a lower cell count, occupies less area, and operates at a higher speed, the one-layer design is far more feasible. Analysis of the temperature and energy consumption of the proposed design indicates that the proposed approaches are superior to those of previous works.

     

Decimal shifting for an exact floating point representation

A floating point representation which permits exact conversion of decimal numbers is discussed. This requires the exponent to represent a power of ten, and thus decimal shifts of the binary mantissa are needed. A specialized design is analyzed for the problem of division by ten, which is needed for decimal shifting.     

Optimal floating point multiplication processor for signal processing

The design of a floating point matrix- vector multiplication processor array for VLSI, which has an optimal area-time complexity product, is presented. This processor array is capable of performing the function (where n = 1,…, N) and can be applied in many digital signal processing applications, by simply changing the matrix coefficients stored in that array. Each N-bit mantissa, M-bit exponent (N, M) processor element of the array comprises a mantissa multiplier/adder circuit and hardware to handle the floating point control. The multiplier/adder circuit is implemented by a new optimal algorithm, which is regular, recursive and fast. Secondly, the algorithm offers a highly local and regular interconnection network, which is a fundamental requirement in VLSI circuit design methodology.     

Some models of error in floating point multiplication

New results are given on error in floating point multiplication. Certain choices of the base minimize the mean multiplicative error. These choices depend on which measure of error is selected. Some measures are included which were not in earlier studies. Some of the results have application to computer design.     

浮点运算的FPGA实现

介绍了采用FPGA实现浮点基本运算的方法,并在ALTERACyclone系列芯片试验验证该算法在高速时钟条件下的性能。     

形式化验证在处理器浮点运算单元中的应用

随着芯片复杂度的急剧增加,模拟仿真验证不能保证测试向量的完备性,尤其是一些边界情况。形式验证方法因其完整的状态空间遍历性和良好的完备性,被业界应用于设计规模不大的模块和子单元中。针对处理器浮点运算单元,采用Cadence公司JasperGold工具对一些关键模块进行了形式化验证,对流水控制中的纠错码(Error Correcting Code,ECC)、软件结构寄存器(Software Architected Register,SAR)和计算单元中的公共模块分别采用了基于FPV(Formal Property Veri fication)的性质检验和基于SEC(Sequential Equivalence Checking)的等价性检验。结果表明,形式化验证在保证设计正确性的基础上极大地缩短了验证周期。     

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

Floating point digital signal processing technology has become the primary method for real time signal processing in most digital systems presently. However, the challenges in the implementation of floating point arithmetic on FPGA are that, the hardware modules are larger, have longer latency and high power consumption. In this work, a novel efficient reversible floating point fused arithmetic unit architecture is proposed confirming to IEEE 754 standard. By utilizing reversible logic circuits and implementation with adiabatic logic, power efficiency is achieved. The hardware complexity is reduced by employing fused elements and latency is improved by decomposing the operands in the realization of floating point multiplier and square root. To validate the design, the proposed unit was used for realization of FFT and FIR filter which are important applications of a DSP processor. As detection is one of the core baseband processing operations in digital communication receivers and the detection speed determines the data rates that can be achieved, the proposed unit has been used to implement the detection function. Simulation results and comparative studies with existing works demonstrate that the proposed unit efficiently utilizes the number of gates, has reduced quantum cost and produced less garbage outputs with low latency, thereby making the design a computational and power efficient one.     

Efficient half-precision floating point multiplier targeting color space conversion

Multimedia Tools and Applications - Color Space Conversion (CSC) in image processing applications, demands computationally simple floating point multipliers consuming less area and power. This...     

2-Adic MRA的浮点数编码遗传算法

通过2-Adic多分辨率分析,构造正交小波基;证明所构造正交小波用于浮点数编码消噪的正确性;提出用正交小波在浮点数编码遗传算法中进行消噪变异操作,以消除浮点数编码在遗传环境中所产生的噪音对算法性能的影响;构建基于2-Adic多分辨率分析的遗传算法,并进行了实验。仿真实验表明,提出的算法可明显提高浮点数编码遗传算法的收敛速度和精度,具有较高的可靠性。