高速图像采集系统的研究及FPGA实现

针对图像采集速度慢和图像品质低等问题,设计并实现了一种基于NiosⅡ双核的高速图像采集系统。该系统利用现场可编程门阵列(FPGA)对图像传感器进行控制,并通过乒乓操作原理对图像进行采集。然后采用面积换速度的原则进行图像处理,在图像处理过程中采用 BP网络图像压缩的算法保存并传输给上位机。对采集数据进行仿真表明:与传统图像采集方法相比较,该系统的图像采集速度和图像采集质量都得到了极大的提高。     

Architecture for fractal image compression

The algorithms for fractal image compression impose a heavy demand on the processor's arithmetic unit and the memory interface, failing to utilize the full capabilities of a general-purpose processor. The repetitive nature of the algorithm indicates that parallelization would reduce the time complexity of the otherwise expensive encoding scheme. In this paper, the design of an ASIC for FIC is proposed. This exploits the fact that the algorithm requires only integer arithmetic with repetitive use of the same set of data. Controlled parallelism is introduced by way of multiple functional units. These result in an encoding time 75 times faster than the high-level software implementation and 22 times faster than the assembly level implementation on a DSP processor.     

Efficient FPGA implementation of DWT and modified SPIHT for lossless image compression

In this paper, we present an implementation of the image compression technique set partitioning in hierarchical trees (SPIHT) in programmable hardware. The lifting based Discrete Wavelet Transform (DWT) architecture has been selected for exploiting the correlation among the image pixels. In addition, we provide a study on what storage elements are required for the wavelet coefficients. A modified SPIHT (Set Partitioning in Hierarchical Trees) algorithm is presented for encoding the wavelet coefficients. The modifications include a simplification of coefficient scanning process, use of a 1-D addressing method instead of the original 2-D arrangement for wavelet coefficients and a fixed memory allocation for the data lists instead of the dynamic allocation required in the original SPIHT. The proposed algorithm has been illustrated on both the 2-D Lena image and a 3-D MRI data set and is found to achieve appreciable compression with a high peak-signal-to-noise ratio (PSNR).     

A novel hardware-oriented Kohonen SOM image compression algorithm and its FPGA implementation

Kohonen self-organizing map (K-SOM) has proved to be suitable for lossy compression of digital images. The major drawback of the software implementation of this technique is its very computational intensive task. Fortunately, the structure is fairly easy to convert into hardware processing units executing in parallel. The resulting hardware system, however, consumes much of a microchip’s internal resources, i.e. slice registers and look-up table units. This results in utilising more than a single microchip to realize the structure in pure hardware implementation. Previously proposed K-SOM realizations were mainly targetted on implementing on an application specific integrated circuit (ASIC) with low restriction on resource utilization. In this paper, we propose an alternative architecture of K-SOM suitable for moderate density FPGAs with acceptable image quality and frame rate. In addition, its hardware architecture and synthesis results are presented. The proposed K-SOM algorithm compromises between the image quality, the frame rate throughput, the FPGA’s resource utilization and, additionally, the topological relationship among neural cells within the network. The architecture has been proved to be successfully synthesized on a single moderate resource FPGA with acceptable image quality and frame rate.     

Greylevel Difference Classification Algorithm in Fractal Image Compression

This paper propses the notion of a greylevel difference classification algorithm in fractal image compression .Then an example of the greylevel difference classification alge-rithm is given as an improvement of the quadrant grevlevel and variance classification in the quadtree-based encoding algorithm.The algorithm incorporates the frequency feature in spatial analysis using th notion of average quadrant greylevel difference,leading to an enhancement in terms of encoding time ,PSNR value and compression ratio.     

Schema genetic algorithm for fractal image compression

In this paper, fractal image compression using schema genetic algorithm (SGA) is proposed. Utilizing the self-similarity property of a natural image, the partitioned iterated function system (PIFS) will be found to encode an image through genetic algorithm (GA) method. In SGA, the genetic operators are adapted according to the schema theorem in the evolutionary process performed on the range blocks. Such a method can speed up the encoder and also preserve the image quality. Simulations show that the encoding time of our method is over 100 times faster than that of the full search method, while the retrieved image quality is still acceptable. The proposed method is also compared to another GA method proposed by Vences and Rudomin. Simulations also show that our method is superior to their method in both the speedup ratio and retrieved quality. Finally, a comparison of the proposed SGA to the traditional GA is presented to demonstrate that when the schema theorem is embedded, the performance of GA has significant improvement.     

ECT图像重建算法的FPGA实现

支持向量机(SVM)在解决小样本,非线性及高维模式识别问题等方面有许多优势,但在处理大规模数据集时训练速度缓慢.针对以上问题提出了SVM学习算法硬件化的设计,它可以在保证向量机学习速度的同时,提高支持向量机的硬件资源利用效率.ECT图像重建实验结果表明,在不影响分类精度的情况下,硬件实现有效减少了运行时间,在一些实时性要求较高的场合该方法的优点将尤为明显.     

An FPGA implementation of a neural optimization of block truncation coding for image/video compression

This paper presents a Field Programmable Gate Array (FPGA) implementation for image/video compression using an improved block truncation coding (BTC) image compression technique. The improvement is achieved by employing a Hopfield neural network (HNN) to calculate a cost function upon which a block is classified as either a high- or a low-detail block. Accordingly, different blocks are coded with different bit rates and thus resulting in better compression ratios. The paper formulates the utilization of HNN within the BTC algorithm in such a way that a viable FPGA implementation is produced. The implementation exploits the inherent parallelism of the BTC/HNN algorithm to provide efficient algorithm-to-architecture mapping. The Xilinx VirtexE BTC implementation has shown to provide a processing speed of about 1.113 × 10⁶ of pixels per second with a compression ratio which varies between 1.25 and 2 bits/pixel, according to the image nature.     

An improved fractal image compression using wolf pack algorithm

Abstract

The fractal image compression is a recent tool for encoding natural images. It builds on the local self-similarities and the generation of copies of blocks based on mathematical transformations. The technique seems interesting in both theory and application but have a drawback renders in real-time usage due to the high resource requirement when encoding big data. By another way, heuristics algorithms represent a set of approaches used to solve hard optimisation tasks with rational resources consumption. They are characterised with their fast convergence and reducing of research complexity. The purpose of this paper is to provide, and for the first time, more detailed study about the Wolf Pack Algorithm for the fractal image compression. The whole Image is considered as a space search where this space is divided on blocks, the scooting wolves explore the space to find other smaller block which have a similarity with based on its parameters. Scooting wolfs perused the whole space a selected the blocks with the best fitness. The process will be stopped after a fixed number of iterations or if no improvement in lead wolf solution. Results show that compared with the exhaustive search method, the proposed method greatly reduced the encoding time and obtained a rather best compression ratio. The performed experiments showed its effectiveness in the resolution of such problem. Moreover, a brief comparison with the different methods establishes this advantage.     

Dynamic Fractal Transform with Applications to Image Data Compression

A recent trend in computer graphics and image processing is to use Iterated Function System(IFS)to generate and describe both man-made graphics and natural images.Jacquin was the first to propose a fully automation gray scale image compression algorithm which is referred to as a typical static fractal transform based algorithm in this paper.By using this algorithm,an image can be condensely described as a fractal transform operator which is the combination of a set of reactal mappings.When the fractal transform operator is iteratedly applied to any initial image,a unique attractro(reconstructed image)can be achieved.In this paper,a dynamic fractal transform is presented which is a modification of the static transform.Instea of being fixed,the dynamic transform operator varies in each decoder iteration,thus differs from static transform operators.The new transform has advantages in improving coding efficiency and shows better convergence for the deocder.     

一种新型非线性分形图像压缩编码算法

提出一种简单的非线性分形算法，简化了Popeseu等提出的算法，用于解决压缩字典较小的问题．实验结果表明，这一算法简单可行，具有良好的压缩结果和高质量的重建图像。     

基于FPGA的JPEG压缩编码设计与实现

利用FPGA可以并行处理数据的优点,设计出了一种JPEG压缩编码电路。并在尽量保证图像质量的前提下,对JPEG的传统编码过程进行优化与调整,简化了编码电路,提高了编码效率,并生成独立IP核,方便调用。实验结果表明,设计的编码电路完全达到了预期目的。     

LFM脉冲压缩的FPGA时域实现

为解决频域法实现线性调频(LFM)脉冲压缩时硬件开销较大的问题,采用时域法实现。针对间距为20m的两目标LFM信号,设计了一款64阶分布式FIR时域匹配滤波器;采用全流水线并行处理结构实现,并利用FPGA的ROM宏模块构建查找表代替乘法运算,既提高了运算速度又减小了硬件开销。基于FPGA器件EP2C35F672C8完成了LFM信号时域脉冲压缩的逻辑设计与集成。仿真结果显示,系统占用2268个逻辑单元、1573个寄存器、27K字节存储器资源。     

基于FPGA高速图像数据的存储及显示设计

设计了一种基于FPGA控制Nand Flash阵列实现高速流水线式存储的方案。设计利用FPGA作为主控制器,通过Camera Link输入通信接口将图像数据经过一/二级缓存写入Flash存储阵列中,并采用DMA传输技术将存储后的图像数据上传至计算机硬盘中作进一步处理;同时,利用SDRAM显存实时刷新数据,FPGA构造相应的VGA信号,最终实现100 MB/s图像数据的实时显示。     

满足资源约束的图像复原算法的FPGA实现

提出了一种基于Van Cittert迭代方法对被乘性噪声污染的观测图像快速复原处理的FPGA电路实现方法。通过研究点扩展函数的对称性,将图像邻域内的像素进行分组滤波运算,明显减少了电路对乘法器数量的要求,有效地利用了FPGA的资源,适当地安排流水线和并行处理单元显著地提高了芯片的运行速度。实验结果表明,对于相同的图像复原处理任务,提出的电路结构需要的逻辑单元数量更少,时间消耗更短。     

快速分形真彩图像压缩方法的实现

针对分形图像编码时间过长的缺点,提出了一种快速分形图像编码方法,称为LSS（Local Sub Search）,实验结果表明,对于真彩图像,较之传统的分形编码方法,该方法在相近的压缩比和解码图像质量的情况下,编码时间大为缩短。该方法已在VC++6.0集成开发环境下得以实现。     

数理统计特征的快速图像分形压缩算法研究

图像自相似是图像分形研究中一个重要的研究方向,尤其是对自相似图像子块的特征提取量化问题尤为引人关注。在分形图像编码发展的过程中,图像自相似特征的提取和量化得到了广泛的研究和应用。通过对图像数理统计特征的研究,提出了一种对图像子块进行分类的方法,使拥有相似特征的图像子块能够划分到更小的区域范围内,改进了分形图像压缩算法。经过分析和实验证明,该方法在不影响重建图像质量的前提下,提高了分形编码的速度,较大程度地减少了计算量。     

适用于低压缩比环境的高效率图像压缩算法

静态图像压缩算法国际标准JPEG目前已广为应用,但其作为通用静态图像压缩算法,实现方法较为复杂,在某些场合并不适用。在深入分析JPEG压缩原理的基础上,通过改进JPEG算法的量化与编码模块,提出了一种基于离散余弦变换（DCT）的简单压缩算法。该算法在低压缩比（压缩比小于15）环境下具有很好的压缩效果,而实现方法却比JPEG简单许多。