一种CMOS混合信号电路衬底噪声耦合模型

利用二维器件模拟器MEDICI提取出重掺杂外延型衬底的电阻宏简化模型,所需的6个参数均可通过器件模拟得到,能够精确表征混合信号集成电路中的衬底噪声特性。基于0.25μm CMOS工艺所建立的电阻宏模型,设计了简单的混合信号电路进行应用验证,证明了该模型能够有效表征混合信号集成电路的衬底噪声。     

IGBT gate driver IC with full-bridge output stage using a modified standard CMOS process

This paper discusses the benefits of a full-bridge output stage on integrated IGBT gate drive circuits. This full-bridge topology allows obtaining positive and negative gate voltages using a single floating power supply. Short circuit protections have also been integrated, implementing an original soft shutdown process after an IGBT short circuit fault. The monolithic integration is based on an innovative high-voltage CMOS technology for power integrated circuits, using a standard low cost CMOS technology, requiring only one extra processing step. Lateral power N- and P-MOS transistors have been optimized using 2D simulators attending both specific on-resistance and breakdown voltage in order to optimize the full-bridge output stage. The IGBT driver has been experimentally tested, producing ±15 V gate-to-emitter voltage, and supplying the current peaks required by the 600 V IGBT switching processes. The driver characteristic response times are adapted to work at high switching frequency (>25 kHz) with high value of capacitive loads (3.7 nF).     

A toroidal inductor integrated in a standard CMOS process

This paper presents a toroidal inductor integrated in a standard 0.13 μm CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches are followed and the results are compared; this comparison provides useful guidelines for the design of the device. A very simple Π model for low frequencies is derived from 1-port and 2-port measurements, and a good matching with general theory is observed. The coil exhibits an inductance between 0.9 nH and 1.1 nH up to 20 GHz (physical limit for the measurement equipment) and a quality factor approaching 10 at 15 GHz. No self-resonance is observed within the measurement range.     

0.18-um CMOS 3.1-10．6GHz超宽带低噪声放大器设计

介绍了一种基于0．18-um CMOS工艺、适用于超宽带无线通信系统接收前端的低噪声放大器。在3．1～10．6GHz的频带范围内对它仿真获得如下结果：最高增益12dB；增益波动小于2dB；输入端口反射系数S11小于-10dB；输出端口反射系数S22小于-15dB；噪声系数NF小于4．6dB。采用1．5V电源供电，功耗为10．5mW。与近期公开发表的超宽带低噪声放大器仿真结果相比较，本电路结构具有工作带宽大、功耗低、输入匹配电路简单的优点。     

粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

一种新型900MHz CMOS低噪声放大器的设计

对两种低噪声放大器(LNA)的构架进行了比较,详细推导了共源LNA的噪声系数与输入晶体管栅宽的关系及优化方法,设计了一种采用0.6 μ m标准CMOS工艺,工作于900MHz的新型差分低噪声放大器.在900MHz时,噪声系数为1.5 dB的情况下可提供22.5 dB的功率增益,-3dB带宽为1 50MHz,S11达到-38dB,消耗的电流为5mA.     

一种SOI CMOS电脉冲时间间隔测定电路的研制

文章设计了一种SOI CMOS电脉冲时间间隔测定器集成电路。阐述了其工作原理，进行了电路的版图设计，测试了芯片的性能。测试结果表明，该电路测量精度高、工作速度快，且抗辐照性能好，达到了设计要求。     

CMOS集成电路低功耗设计方法

近年来，功耗问题已成为VLSI设计，尤其是在电池供电的应用中必须考虑的重要问题之一。文章通过对CMOS集成电路功耗起因的分析，对CMOS集成电路低功耗设计方法和设计工具进行了深入的讨论。     

CMOS射频集成电路：成果与展望

CMOS射频集成电路的研究和制作将大大拓展集成电路的应用空间,文章介绍了采用CMOS工艺集成射频电路研究中所取得的成果,评述了其中存在的问题,最后指出了该领域中未来的几个研究方向。     

High-voltage LDMOS transistors fully compatible with a deep-submicron 0.35 μm CMOS process

This work presents the design of LDMOS transistors fully compatible with a standard CMOS process, only requiring mask layout manipulation. A conventional 0.35 μm CMOS process was elected to demonstrate the viability of the approach. The prototyped LDMOS transistor exhibits a breakdown voltage of 24 V, which represents an improvement of 31% when compared with the high-voltage extended-drain NMOS available in the process library, while other static parameters remain in the same range. Furthermore, this solution enables the CMOS integration of a high-voltage pass-transistor, as a consequence of the formation of an isolated lightly doped p-type region inside the n-well.     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

低失真CMOS连续时间Butterworth滤波器电路的设计

介绍了一种CMOS工艺下实现的连续时间滤滤器。该滤波器运用了R-MOSFET-C技术来改善线性度,达到低失真。利用滤波器系统本身的环路增益,并将环内的非线元件替换,由元件本身的非线性所产生的失真大大减小。     

An analysis of high-frequency noise in RF active CMOS mixers

An analysis of high-frequency noise in RF active CMOS mixers including single-balanced and double-balanced architectures is presented. The analysis investigates the contribution of non-white gate-induced noise to the output noise power as well as the spot noise figure (NF) of the RF CMOS mixer. It accounts for the non-zero correlation between the gate-induced noise and the channel’s thermal noise. The noise contribution of the RF transconductor and the switching pair to the output noise power is studied. Experimental results verify the accuracy of the analytical model. Payam Heydari (S’98–M’00) received the B.S. and M.S. degrees in electrical engineering from the Sharif University of Technology, in 1992, 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California, in 2001. During the summer of 1997, he was with Bell-Labs, Lucent Technologies, where he worked on noise analysis in deep submicrometer very large-scale integrated (VLSI) circuits. During the summer of 1998, he was with IBM T. J. Watson Research Center, Yorktown Heights, NY, where he worked on gradient-based optimization and sensitivity analysis of custom-integrated circuits. Since August 2001, he has been an Assistant Professor of Electrical Engineering at the University of California, Irvine, where his research interest is the design of high-speed analog, RF, and mixed-signal integrated circuits. Dr. Heydari has received the 2005 National Science Foundation (NSF) CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 Henry Samueli School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Mention Award from the Department of EE-Systems at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty at the EECS Department of the University of California, Irvine. His name was included in the 2006 Who’s Who in America. Dr. Heydari Professor Heydari has been the Associate Editor of IEEE TRANS. ON CIRCUITS AND SYSTEMS, I, since 2006. He currently serves on the Technical Program Committees of International Symposium on Low-Power Electronics and Design (ISLPED), International Symposium on Quality Electronic Design (ISQED), and the Local Arrangement Chair of the ISLPED conference. He was the Student Design Contest Judge for the DAC/ISSCC Design Contest Award in 2003, the Technical Program Committee member of the IEEE Design and Test in Europe (DATE) from 2003 to 2004, and International Symposium on Physical Design (ISPD) in 2003.     

低功耗宽带CMOS低噪声放大器

本文实现了一款低功耗的宽带低噪声放大器(LNA)。该低噪放由输入级、中间级和输出级组成。由于每一级都采用了电流复用技术,显著地降低了功耗。输入级通过电阻、电容负反馈和并联电感,实现了良好的输入匹配。引入电感抵消了电容产生的虚部阻抗并且抵消了电容产生的极点。与电阻负反馈放大器相比,本文提出的结构提高了增益。中间级通过并联电感引入零点,采用低Q值拓展带宽。输出级是源级跟随器,提供了良好的输出匹配。经0.18 μm TSMC CMOS工艺仿真验证,在3 V的电源电压下,功耗仅为4.89 mW。另外在1~4.5 GHz频带范围内,电压增益(S21)为14.8±0.4 dB,噪声系数(NF)介于3.1~4.2 dB之间,输入、输出反射系数(S11、S22)均小于-10 dB。在4GHz时,输入三阶交调点(IIP3)达到-11dBm。     

CMOS电压基准的设计原理

电压基准是集成电路一个重要的构成单元。结合多年设计经验，介绍了五类CMOS电压基准的设计原理、理论推导、参考电路、特点和主要性能指标，给出了主要参数的计算公式。最后，对各种CMOS电压基准的性能进行了比较。     

一种用于数字电视调谐器的宽带CMOS无电感噪声抵消低噪声放大器

A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2-15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point(IP1dB) is - 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5×0.35 mm2.     

Design and testing of a self-powered 3D integrated SOI CMOS system

A self-powering 3D integrated circuit built using an SOI CMOS process is presented. The 3D integrated circuit has three tiers connected by vertical vias through the intertier oxides. The circuit elements are a photodiode array, a charge-integrating capacitor, and a local oscillator with an output buffer, each on a separate tier. The final system size is 250 μm × 250 μm × 696 μm. Our results demonstrate the circuit as a feasible proof-of-concept 3D “system”. The photodiode array stores charge on the capacitor and powers the oscillator as designed.     

深亚微米CMOS低噪声放大器的设计

通过一个符合性能指标的，用于射频接收系统的CMOS低噪声放大性能的设计，讨论了深亚微米MOSFET的噪声情况，并在满足增旋和功耗的前提下，对低噪声放大噪声性能进行分析和优化，该LNA工作在2.5GHz电源电压，直流功耗为25mW，能够提供19dB的增益（S21），而噪声系数仅为2.5dB，同时输入匹配良好，S11为-45dB，整个电路只采用了一个片外电感使电路保持谐振，此设计结果证明CMOS工艺在射频集成电路设计领域具有可观的潜力。     

CMOS图像传感器像素中MOSFET晶体管的栅感应噪声原理及分析

提出一种CMOS图像传感器像素中MOSFET晶体管的栅感应噪声原理.分析表明MOSFET工作于强反型区的栅感应噪声比工作于亚阈值区明显,但当施加在栅极电压达到3V时,随着ω/ωT比值的增加,MOSFET工作于亚阈值区的栅感应噪声比工作于强反型区明显.同时详细分析了有源像素(APS)中的RESET晶体管的栅感应噪声的影响并提出抑制栅感应噪声的电路.     

图像传感器像素中MOSFET晶体管的栅感应噪声原理及分析

提出一种CMOS图像传感器像素中MOSFET晶体管的栅感应噪声原理.分析表明MOSFET工作于强反型区的栅感应噪声比工作于亚阈值区明显,但当施加在栅极电压达到3V时,随着ω/ωT 比值的增加,MOSFET工作于亚阈值区的栅感应噪声比工作于强反型区明显.同时详细分析了有源像素(APS)中的RESET晶体管的栅感应噪声的影响并提出抑制栅感应噪声的电路