Modeling and design of a monolithically integrated power converter on SiC

To fully explore the high temperature and high power density potential of the 4H-SiC material, not only power devices need to be fabricated on SiC, but also the circuitries for signal generation/processing, gate driver and control. In this paper, static and dynamic characteristics of SiC lateral JFET (LJFET) devices are numerically simulated and compact circuit models developed. Based on these models, analog and digital integrated circuits functional blocks such as OPAMP, gate driver and logic gates are then designed and simulated. Finally, a fully integrated power converter including pulse-width-modulation circuit, over-temperature protection circuit and a power boost converter is designed and simulated. The converter has an input of 200 V and an output voltage of 400 V, 2.5 A, operating at 1 kW and 5 MHz.     

All-digital controlled boost DC–DC converter with all-digital DLL-based calibration

Traditional digital controls mostly use digital–analog converters to convert input and output voltages into digital coding to achieve control. This paper proposes the use of two digital ramps with two different frequencies to replace a digital–analog converter. This approach can produce seven bit resolution for the DPMW signal. In addition, we use an all-digital DLL phase correction concept to further enhance the resolution of the DPWM signal by an additional three bits, resulting in 10-bit DPWM signal resolution. The proposed circuit uses 0.35 μm CMOS processes, with a core area of 0.987 mm², a system switching frequency of 500 KHz, an input voltage range of 3.3–4.2 V, and an output voltage range of 5 V. Output voltage measurement accuracy reaches 99%, while the system reaches efficiency of 91% with output loads of up to 500 mA.     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

10 K NbN ADC for IR sensor applications

The authors report the design, fabrication and test results of a 12-bit NbN SFQ counting A/D converter operating at 9 to 10 K and its insertion into a test IR focal plane array sensor system. The NbN IC is based on a linearized SQUID front-end which generates SFQ pulses at a frequency proportional to the signal. A gated SFQ counter integrates the signal over the sample time and the data is driven off chip through a serializing latching voltage state logic (MVTL) output shift register. The TRW A/D converter chip has been packaged and inserted into an IR focal plane array sensor test facility, or test bed, at the NASA Jet Propulsion Laboratory. The entire system has been successfully demonstrated producing IR images at 100 frames/s with the NbN A/D converter operating at 9 K, dissipating 0.3 mW. Performance of the A/D converter chip, the package including magnetic shielding and medium/high speed signal I/O, and the integrated test bed system are discussed.     

A 1-V, 1.2-mA fully integrated SoC for digital hearing aids

Both power and size are very important design issues for hearing aids. This paper proposes a fully integrated low-power SoC for today׳s digital hearing aids. The SoC integrates all the audio processing elements on single chip, including the analog front-end, digital signal processing (DSP) platform and class-D amplifier. Also, the low-dropout voltage regulators and internal clock generator are both integrated to minimize the system overall size. The 24-bit DSP platform comprises an application-specific instruction-set processor and several dedicated accelerators to achieve a trade-off between flexibility and power efficiency. Three critical hearing-aid algorithms (wide dynamic range compression, noise reduction and feedback cancellation) are performed by the low-power accelerators. The proposed SoC has been fabricated in SMIC 130 nm CMOS technology. The measurement results show that the analog front-end has up to 88 dB signal-to-noise ratio. And the DSP platform consumes about 0.86 mA current at 8 MHz clock frequency when executing the three algorithms. The total current consumption of SoC is only 1.2 mA at 1 V supply. In addition, the acoustic test results indicate that the SoC is one promising candidate for hearing-aid manufacturers.     

A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications

A low-distortion feed-forward MASH2_4b-2_4b sigma–delta analog-to-digital converter (ADC) for wireless local area network (WLAN) applications was presented. The converter exhibits improved performances than the ADCs which have been presented to date by adding a feedback factor in the second stage and employing a 2nd-order noise-shaping dynamic element matching (DEM) scheme. The feedback factor induces a zero in the noise transfer function (NTF) and therefore improves the in-band signal to noise and distortion ratio (SNDR) of the modulator. The mismatch-shaping DEM was introduced and applied to the 4-bit DACs in this paper to improve the resolution and linearity of the ADC. Fabricated in a 0.18 μm CMOS process with single 1.8 V supply voltage, the converter achieves a peak SNDR of 85.4 dB over a 10 MHz bandwidth which implies an effective number of bits (ENOB) of 13.90-bit. The spurious free dynamic range (SFDR) is –94 dB for a 1.25 MHz@–6dBFS input signal at 160 MHz sampling frequency. The occupied area is 0.44 mm² and dissipation power 23.4 mW.     

An NTF-enhanced incremental ΣΔ modulator using a SAR quantizer

In this paper, a noise transfer function (NTF) enhanced incremental sigma-delta (ΣΔ) modulator is presented. It employs a charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) in an error-feedback scheme to achieve an extra noise-shaping order. Using a multi-bit SAR quantizer not only improves the stability and power consumption but also facilitates the realization of both the adder situated in front of the quantizer and the whole error-feedback loop. As a design example, a multiplexed 2nd-order modulator based on the proposed architecture is simulated in TSMC 90 nm CMOS technology using Spectre with a 1 V single power supply. The simulation results show a signal-to-noise and distortion ratio (SNDR) of 85.3 dB within a signal bandwidth of 20 kHz (1 kHz/channel) at 5 MHz sampling frequency. The power consumption for each channel is 8.6 µW.     

A digital predistortion assisted hybrid supply modulator for envelope tracking power amplifiers

In this paper, a novel digital predistortion assisted supply modulator is presented. The proposed modulator is suitable for envelope tracking power amplifiers. In this topology, a digitally controlled linear power amplifier is used to compensate the switching noise ripples of the switching modulator. The proposed structure is evaluated with a 0.18 µm CMOS process technology. The results show up to 9% static efficiency improvement in comparison with previous one-phase and two-phase architectures. It is shown that for a 5 MHz WiMAX signal with a 6.7 dB PAPR at 26.8 dBm output power, a maximum average efficiency of 73.5% is achieved in the proposed design.     

Tunable mode converter using electromagnet-induced long-period grating in two-mode fiber

We present an in-fiber mode converter that changes the propagation ratio of two core modes. A dynamic long-period grating is constructed in a two-mode fiber by the combination of an electromagnet with a nonmagnetic spring coiled around a stiff iron rod. The fundamental mode is converted to the LP₁₁ mode according to the voltage applied on the electromagnet. The mode-conversion wavelength can be tuned by stretching the coil spring. Compared to the coupling result with leaky cladding modes, the mode-conversion bandwidth expands from 5 nm to 90 nm and the drive voltage decreases almost by half.     

A comprehensive,adjustable approach for linearizing and broadening the gain characteristic of variable gain amplifiers

In this paper a comprehensive approach is presented to linearize and adjust gain characteristic of variable gain amplifiers (VGAs). It is also capable of increasing the output linear dynamic range of VGAs and modifying variation range of control voltage. The approach is able to change the voltage gain characteristic of an amplifier, even after fabrication, to a desired one by means of a digital control signal and a digital to analog converter. Using this approach, the gain of basic differential amplifier is controlled by two different predistorters, and adjustable dB-linear characteristics in range of greater than 60 dB are achieved. The approach, also, is applied to two conventional VGAs, the gain characteristic of first VGA is linearized, and in the second VGA, the linear dynamic range is expanded about 26 dB. The controller uses 1.2 V voltage supply, and simulations are done using 0.13 µm CMOS process model. The other characteristics of each mode of control are reported completely.     

Design and implementation of micro-power temperature to duty cycle converter using differential temperature sensing

The CMOS based temperature detection circuit has been developed in a standard 180 nm CMOS technology. The proposed temperature sensor senses the temperature in terms of the duty cycle in the temperature range of −30 °C to +70 °C. The circuit is divided into three parts, the sensor core, the subtractor and the pulse width modulator. The sensor core consists of two individual circuits which generates voltages proportional (PTAT) and complementary (CTAT) to the absolute temperature. The mean temperature inaccuracy (°C) of PTAT generator is −0.15 °C to +0.35 °C. Similarly, CTAT generator has mean temperature accuracy of ±1 °C. To increase thermal responsivity, the CTAT voltage is subtracted from the PTAT voltage. The resultant voltage has the thermal responsivity of 6.18 mV/°C with the temperature inaccuracy of ±1.3 °C. A simple pulse width modulator (PWM) has been used to express the temperature in terms of the duty cycle. The measured temperature inaccuracy in the duty cycle is less than ±1.5 °C obtained after performing a single point calibration. The operating voltage of the proposed architecture is 1.80±10% V, with the maximum power consumption of 7.2 μW.     

Nano-gap micro-electro-mechanical bulk lateral resonators with high quality factors and low motional resistances on thin silicon-on-insulator

The design, fabrication and experimental investigation of 22–25 MHz fragmented-membrane MEM bulk lateral resonators (BLR) with 100 nm air-gaps on thin (1 and 6 μm) silicon-on-insulator (SOI) are reported. Quality factors as high as 120,000 and motional resistances of as little as 60 kΩ are measured under vacuum at room temperature, with 12 V DC bias and low AC power. The temperature influence on the resonance frequency and quality factor is studied and discussed between 80 K and 320 K. Significant quality factor increase and motional resistance reduction are reported at cryogenic temperature. The paper shows that high-quality factor MEM resonators can be integrated on partially depleted thin SOI, which can be a substrate of choice for the fabrication of future integrated hybrid MEMS–CMOS integrated circuits for communication applications.     

A mixed-signal pulse width modulator for portable SMPS applications

This paper presents a design for a mixed-signal pulse width modulator (MSPWM) integrated circuit that targets the digital control of high-frequency switched-mode DC–DC power supplies (SMPS). Previous designs consider digital pulse width modulators (DPWM) implementations that encounter important design issues, such as power consumption, non-linearity, layout dependency, trimming capability and temperature dependency. This work presents effective solutions, suitable for large-scale production of ICs, since it combines high-precision, high-linearity and temperature-independent standard analog circuits, which are commonly offered by the semiconductor industry, with the simplicity and reuse of digital PID compensation as input. The 8-bit prototype designed for a 0.18-μm CMOS process operates at switching frequency of 2 MHz, draws only 96.25 μA from a 1.8 V supply and takes 0.029 mm², including the non-overlapping control logic of SMPS power devices.     

An 8 bit, 100 kS/s,switch-capacitor DAC SAR ADC for RFID applications

An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is introduced to provide stabilized current. This invariable current from RDCM, charging or discharging the only capacitor in circuit is controlled by pulse width modulated signal to realize switch capacitor DAC. The switch control scheme is built using basic AND gates to generate the control signals for RDCM. Only one capacitor and reduced transistor count in digital part reduces the silicon area occupied by the ADC to only 0.0098 mm². The converter, designed in GPDK 90 nm CMOS, exhibits maximum sampling frequency of 100 kHz & consumes 6.75 µW at 1 V supply. Calculated signal to noise and distortion ratio (SNDR) at 1 V supply and 100 kS/s is 48.68 dB which relates to ENOB of 7.79 bits. The peak values of differential and integral nonlinearity are found to be +0.70/−0.89 LSB and +1.40/−0.10 LSB respectively. Evaluated figure of merit (FOM) is 3.87×10²⁰, which show that the proposed ADC acquires minimal silicon area and has sufficiently low power consumption compared to its counterparts in RFID applications.     

Ultraviolet photodetectors based on low temperature processed ZnO/PEDOT:PSS Schottky barrier diodes

In this work, vertical Schottky barrier diodes (SBDs) were fabricated using a thin film of ZnO (50 nm) and PEDOT:PSS deposited by RF Sputtering and micro-drop casting, respectively. ITO and Au were used as ohmic contacts to ZnO and PEDOT:PSS films, respectively. The final structure consisted on Glass/ITO/ZnO/PEDOT:PSS/Au. The SBDs performance was characterized under dark and four different wavelengths conditions. From current–voltage characteristics, under dark and ambient conditions, a diode ideality factor of 1.4; a saturation current density of 1×10⁻⁹ A/cm²; a Schottky barrier height of 0.9 eV and a rectification ratio of 5 orders of magnitude at ±1 V were obtained. A carrier density of 5×10¹⁷ cm⁻³ for the ZnO film was estimated from capacitance–voltage measurements. For their characterization as photodiodes, the SBDs were illuminated with an ultra-bright UV (~380 nm) LED. A maximum UV responsivity of 0.013 A/W was obtained. The transient response of the SBDs was also analyzed with the UV LED connected to a pulsed signal of 0.5 Hz, demonstrating rise and fall times in the order of 200 ms. With a low temperature processing (<80 °C), visible-blind and UV photon-detection characteristics, the fabricated SBDs are candidates for flexible optoelectronics devices such as optical receivers for digital signal processing and measurement of light intensity.     

A low power and small area digital self-calibration technique for pipeline ADC

A digital self-calibration implementation with discontinuity-error and gain-error corrections for a pipeline analog-to-digital converter (ADC) is presented. In the proposed calibration method, the error owing to each reference unit capacitor of the multiplying D/A converter is measured separately using a calibration capacitor and an enhanced resolution back-end pipeline ADC acting as an error quantizer. The offset and finite open loop DC-gain of the operational amplifier and capacitor mismatches, the reference voltage mismatch can all be calibrated. The calibration can be achieved by that only used addition and subtraction. Hence, it needs low power and area consuming. A prototype ADC with the proposed calibration was fabricated on a 0.5 μm double-poly triple-metal CMOS process. The power consumption and area of the calibration circuit are only 10.1 mW and 1.05 mm², respectively. At a sampling rate of 30 MS/s, the calibration improves the DNL and INL from 2.59 LSB and 14.98 LSB to 0.72 LSB and 1.82 LSB, respectively. For a 1.25 MHz sinusoidal signal, the calibration improves the signal-to-noise-distortion ratio and spurious-free dynamic range from 43.1 dB and 52.1 dB to 75.51 dB and 83.61 dB, respectively. The 12.25 effective number of bits at 30 MS/s ADC consumes a total power of 136 mW.     

Experimental observation of the post-annealing effect on the dark current of InGaAs waveguide photodiodes

The post-annealing effect on the dark current of the InGaAs waveguide photodiodes, which are developed for 40-Gbps optical receiver applications, is experimentally investigated. The interesting experimental phenomena were observed that the dark current is significantly decreased and the breakdown voltage is slightly increased after annealing at 250 and 300 °C whereas the dark current and the breakdown voltage are almost constant after annealing at 200 °C. Based on the experimental results, the post-annealing is more effective for the dark current improvement than the conventional curing process.     

High performance top-emitting and transparent white organic light-emitting diodes based on Al/Cu/TcTa transparent electrodes for active matrix displays and lighting applications

It is challenging to obtain broadband emission covering as much of the visible light spectrum as possible in top-emitting white organic light-emitting diodes (TEWOLEDs) due to the well known microcavity effects. In this work, we achieved TEWOLED with three separate peak and negligible angular dependence by employing a high transmittance stack cathode Al (2 nm)/Cu (18)/TcTa (60 nm). The TEWOLED shows an efficiency of 25.6 cd/A, 20.1 Lm/W at 1000 cd/m², and low voltage of 4.2 V for 1222 cd/m². Synchronously, we achieved transparent white organic light-emitting diode (TWOLED) using this high transmittance stack cathode, the TWOLED exhibits similar spectrum and comparable luminance from both sides, and the maximum total efficiencies of the TWOLED are 28.6 cd/A, 24.9 Lm/W.     

High linearity,low power RF mixer design in 65 nm CMOS technology

A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB.     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².