A compact broadband MMIC sub-harmonic mixer using quasi-lumped transmission lines

A compact broadband monolithic microwave integrated circuit (MMIC) sub-harmonic mixer using an OMMIC 70 nm GaAs mHEMT technology is demonstrated for 60 GHz down-converter applications. The present mixer employs an anti-parallel diode pair (APDP) to fulfill a sub-harmonic mixing mechanism. Quasi-lumped components are employed to broaden the operational bandwidth and minimize the chip size to 1.5×0.77 mm². The conversion gain is optimized by a quasi-lumped 90° phase shift stub. Experimental results show that from 50 GHz to 70 GHz, the conversion gain varies between −12.1 dB and −15.2 dB with a LO power level of 10 dBm and 1 GHz IF. The LO-to-RF, LO-to-IF and RF-to-IF isolations are found to be greater than 19.5 dB, 21.3 dB and 25.8 dB, respectively. The second harmonic component of the LO signal is suppressed. The proposed mixer has an input 1 dB compression point of -2 dBm and exhibits outstanding figure-of-merits.     

A linear ultra wide band low noise amplifier using pre-distortion technique

This paper presents an Ultra Wide-Band (UWB) high linear low noise amplifier. The linearity of Common Gate (CG) structure is improved based on pre-distortion technique. An auxiliary transistor is used at the input to sink the nonlinear terms of source current, resulting linearity improvement. Furthermore, an inductor is used in the gate of the main amplifying transistor, which efficiently improves gain, input matching and noise performance at higher frequencies. Detailed mathematical analysis show the effectiveness of both linearity improvement and bandwidth extension techniques. Post-layout simulation results of the proposed LNA in TSMC 0.18 µm RF-CMOS process show a gain of 13.7 dB with −3 dB bandwidth of 0.8–10.4 GHz and minimum noise figure (NF) of 3 dB. Input Third Intercept Point (IIP3) of 10.3–13 dBm is achieved which shows 8 dB improvement compared to conventional common gate structure. The core circuit occupies an area of 0.19 mm² including bond pads, while consuming 4 mA from a 1.8-V supply.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

A broadband Low Noise Amplifier with built-in linearizer in 0.13-µm CMOS process

A linearized ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) is presented in this paper. The linearity performance is enhanced by exploiting PMOS–NMOS common-gate (CG) inverter as a built-in linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and magnitude of the third-order distortion. A second-order band-pass Chebyshev filter is utilized in the input port of common-source (CS) configuration to provide broadband input matching at 3.1–10.6 GHz frequency range to a 50-Ω antenna. Series and shunt peaking techniques are employed to extend the bandwidth (BW) and to flatten the gain response. Simulated in 0.13 µm CMOS technology, the CMOS LNA exhibits state of the art performance consuming 17.92 mW of dc power. The CMOS LNA features a maximum gain of 10.24 dB, 0.9–4.1 dB noise figure (NF), and a third-order input intercept point (IIP3) of 6.8 dBm at 6.3 GHz.     

Improved performance step impedance lowpass filter

Performances of the conventional Butterworth step impedance lowpass filters (LPF) are significantly improved by placing transmission zero either closer to the cut-off frequency (f_c) or away from it. It is achieved by using transverse resonance width of the capacitive line sections. We report method of designing transverse resonance type LPF (TR-LPF) for 5 to 11-pole filters. At f_c = 2.5 GHz, we obtained selectivity in the range 113.3–56.66 dB/GHz and 20–60 dB rejection BW in the range 9.61–7.29 GHz. The TR-LPF can suppress the stopband signal by 60 dB up to 5f_c. Insertion loss in passband is within 0.72 dB. Improved performance of TR-LPF can be designed for f_c up to 7.5 GHz.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

Low power dissipation SiGe HBT dual-band variable gain amplifier

A dual-band variable gain amplifier operating at 0.9 GHz and 2.4 GHz was designed based on high performance RF SiGe HBT for large amount of signals transmission and analysis. Current steering was adopted in gain-control circuit to get variable trans-conductance and then variable gain. Emitter degeneration and current reuse were considered in amplifying stage for low noise figure and low power dissipation respectively. A single-path circuit resonating at two frequency points simultaneously was designed for input impedance matching. PCB layout parasitic effects, especially the via parasitic inductor, were analyzed theoretically and experimentally and accounted for using electro-magnetic (EM) simulation. The measurement results show that a dynamic gain control of 26 dB/16 dB in a control voltage range of 0.0–1.4 V has been achieved at 0.9/2.4 GHz respectively. Both S₁₁ and S₂₂ are below than –10 dB in all the control voltage range. Noise figures at both 0.9 GHz and 2.4 GHz are lower than 5 dB. Total power dissipation of the dual-band VGA is about 16.5 mW at 3 V supply.     

MISO current mode bi-quadratic filter employing high performance inverting second generation current conveyor circuit

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths.Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption.The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results.     

3.1–10.6 GHz ultra-wideband LNA design using dual-resonant broadband matching technique

This paper presents an ultra-wideband low noise amplifier design using the dual-resonant broadband matching technique. The proposed LNA achieves a 10.2 dB gain with ±0.9 dB gain flatness over a frequency range of 3.1–10.6 GHz and a ?3-dB bandwidth of 2.4–11.6 GHz. The measured noise figure ranges from 3.2 to 4.7 dB over 3.1–10.6 GHz. At 6.5 GHz, the measured IIP3 and input-referred P1dB are +6 dBm and ?5 dBm, respectively. The proposed LNA occupies an active chip area of 0.56 mm² in a TSMC 0.18 μm RF-CMOS process and consumes 16 mW from a 1.8 V supply.     

Corrugated SIW K band horn antenna

In the recent years, the strong demand for high performance, low cost and high gain antennas for telecommunication, surveillance, and imaging applications has rapidly grown at microwave and higher frequencies. High speed wireless links require modular, compact size and high directivity with low cross polarization antennas. To demonstrate the proposed concepts and design features, in this paper, a substrate integrated waveguide (SIW) feeding technique has been created having well behaved gain and suitable −10 dB bandwidth from 23.8 GHz to 25.7 GHz (roughly 2 GHz bandwidth), while the impedance bandwidth for VSWR < 2.5 is nearly 3 GHz. The simulated antenna attains 12.5 ± 1 dB gain over majority of K band with an occupied size of 82 mm × 40 mm × 2.54 mm and has roughly 95% radiation efficiency. The proposed antenna is an excellent candidate for integrated low cost K band and even higher frequency systems. The simulations are done by two full wave packages i.e. ANSYS HFSS and CST MWS that associated with finite element method (FEM) and finite difference time domain (FDTD), respectively. The results show good agreements between these two methods.     

Nonlinear effect mitigation based on PAPR reduction using electronic pre-distortion technique in direct-detection optical OFDM system

The nonlinear effect induced by the Mach–Zehnder modulator (MZM) and optical self-phase modulation (SPM) in the presence of high peak-to-average power ratio (PAPR) is investigated theoretically. We theoretically and experimentally investigate the direct-detection optical orthogonal frequency-division multiplexing (DD-OOFDM) system with an electronic pre-distortion technique of companding transform (CT) to reduce the peak-to-average power ratio (PAPR) of OFDM signals and improve the receiver sensitivity. Experimental results show that the PAPR reduction can reach about 3 dB when the complementary cumulative distribution function is 1 × 10⁻⁴, which means the number of random OFDM signals is 1 × 10⁴, and the receiver sensitivity is improved by 0.7, 1.7, and 2.4 dB for the launch power of 2, 6 and 10 dB m, respectively, at the BER of 1 × 10⁻⁴ after transmission over 100-km single-mode fiber with the μ of 2. It shows that the PAPR reduction can mitigate not only the nonlinearity of MZM, but also the nonlinear phase noise in the fiber link when the optical power into fiber is high.     

Life test of an X-band MMIC multi-function chip for active phased array radar applications

A 1000-h steady state life test at a temperature of 125 °C was performed on ten X-band MMIC multifunction chips for use in active phase array radar systems. Internal switches, phase shifters, and attenuators were operated through an integrated serial-to-parallel converter under the five-second stepped external control signal for the life test period. None of the ten samples failed under the failure criteria based on the JEP118 standard. The calculated failure rate using the Chi Square Statistic was 1.6 e⁻⁶ failures/h for the 90% confidence level. Maximum DC current variation was +16% for an initial value. Maximum variations of small signal gain, phase shift, and attenuation were 0.96 dB, 2°, and 0.17 dB, respectively, over a frequency range of 8.5–10.5 GHz.     

A novel Hemispherical Dielectric Resonator Antenna on an Electromagnetic Band Gap substrate for broadband and high gain systems

In this paper we propose and investigate the application of Electromagnetic Band Gap (EBG) substrate for improving the performance of Hemispherical Dielectric Resonator Antenna (HDRA). Our designed EBG shows a band gap in the frequency range of 1.75–2.25 GHz and the HDRA is resonant at 2 GHz which falls within the bandgap of the EBG. When combined with the EBG substrate the −10 dB bandwidth shows an improvement from 11.25% to 30%. On engineering the height of the HDRA on EBG substrate the gain is improved from 6.13 dBi to 9 dBi. To validate the results, simulations are carried out on CST Microwave Studio and HFSS.     

Utility of RF MEMS miniature switched capacitors in phase shifting applications

This paper demonstrates research carried out towards the development of switched capacitors having miniature dimensions. Such devices are based on the Radio Frequency Micro Electro Mechanical Systems (RF MEMS) technique which has gained prominence in implementing a wide variety of microwave and millimetre devices till date. Switched capacitors having standard or conventional dimensions are prone to several limitations which are addressed by scaling down the standard dimensions by 150× times (in terms of area requirement). Such switched capacitors are employed to develop phase shifters working in K-band (22 GHz) frequency range to yield appreciable performance both in terms of electromechanical and RF characterizations. Such switched capacitors are utilized to develop phase shifters which find immense applications in the design of Phased Array RADARs. Switched capacitors fabricated on 500 µm thick quartz substrates, result in 30° phase shift (0.66 mm × 1 mm in dimension) with associated minimum −0.18 dB insertion loss and better than −21 dB reflection coefficient at 22 GHz frequency. Electromechanical characterization reports an actuation voltage of 14.6 V, mechanical vibration frequency of 2.5 MHz and a switching time of 620 ns respectively. Demonstrations showing complete realization of 180° phase shifter (4 mm × 1 mm) employing a cascaded arrangement of six similar 30° unit cells are also included in this paper.     

Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application

This work describes the design and implementation of an ultra-low voltage, ultra-low power fully differential low noise amplifier (LNA) integrated with a down-conversion mixer for 2.4 GHz ZigBee application. An inductive-degenerated cascoded LNA is adapted and integrated with a double-balanced mixer which is targeted for low-power application. The proposed design has been extracted and simulated in a 0.13 μm standard CMOS technology. With a power consumption of 905 μW at a voltage headroom of 0.5 V, the proposed LNA-mixer integration reaches out to an integrated noise figure (NF) of 7.2 dB, a gain of 22.3 dB, 1 dB compression point (P1 dB) of −22.3 dBm and input-referred third-order intercept point (IIP3) of −10.8 dBm.     

A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4 GHz wireless communications

This paper presents a low-voltage low-power transmitter front-end using current mode approach for 2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18 μm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique, which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4 GHz, the transmitter front-end provides 15.5 dB of power conversion gain, output P?1 dB of 3 dBm, and the output-referred third-order intercept point (OIP3) of 13.8 dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of 1.2 V. The chip area including the testing pads is only 0.9 mm×1.1 mm.     

Efficient biasing circuit strategies for inductorless wideband low noise amplifiers with feedback

This paper presents a comparative study among different biasing circuits of inductorless low-area Low Noise Amplifier (LNAs) with feedback. This study intends to determine the most suitable biasing circuit to achieve the best LNA performance for wideband applications. The main performance metrics are analyzed and a comparison is carried out based on electrical simulations. To this purpose, two different CMOS technology processes are considered: 130 nm and 90 nm. In both cases, the supply voltage is 1.2 V. The best LNA designed in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltage gain (A_v) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology designed in 90 nm technology has a bandwidth of 11.2 GHz, featuring a voltage gain of 16.6 dB and consuming 1.9 mW. Both LNAs are input-impedance matched and have a noise figure below 2.4 dB measured at 2.4 GHz. As a case study, the layout of the best-performance LNA circuit has been implemented in a 130 nm technology, achieving an area of 0.012 mm², which is near the size of a pad or an inductor. It is demonstrated that the bandwidth of this circuit can be notably increased by simply adding a small inductance in the feedback path.¹     

A digital predistortion assisted hybrid supply modulator for envelope tracking power amplifiers

In this paper, a novel digital predistortion assisted supply modulator is presented. The proposed modulator is suitable for envelope tracking power amplifiers. In this topology, a digitally controlled linear power amplifier is used to compensate the switching noise ripples of the switching modulator. The proposed structure is evaluated with a 0.18 µm CMOS process technology. The results show up to 9% static efficiency improvement in comparison with previous one-phase and two-phase architectures. It is shown that for a 5 MHz WiMAX signal with a 6.7 dB PAPR at 26.8 dBm output power, a maximum average efficiency of 73.5% is achieved in the proposed design.     

A tunable CMOS Wilkinson power divider using active inductors

This paper presents the design and implementation of a tunable CMOS Wilkinson power divider using active inductors. Compared to a conventional active inductor topology, the proposed active inductor features higher inductance tuning range, higher self-resonant frequency, and lower power consumption by introducing two additional transistors. Benefitting from the superior inductor, the low-loss Wilkinson power divider is practical while maintaining a wide tuning range. The design consuming 10.2 mW demonstrates an insertion loss of 0.67 dB, a return loss of 27 dB, and an isolation of 22.6 dB at 8 GHz. Moreover, the tuning range of the circuit is between 5.8 GHz and 10.4 GHz, rendering a 4.6 GHz bandwidth. The active chip size of the lumped design is merely 0.25 mm × 0.15 mm.     

A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques

In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain, -3 dB bandwidth (BW_−3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of +13.1 dBm and +42.8 dBm, respectively. The simulated S₁₁ is less than −11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.