Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.     

Thermal stability of Hf/sub x/Ta/sub y/N metal gate electrodes for advanced MOS devices

In this letter, the composition effects of hafnium (Hf) and tantalum (Ta) in Hf/sub x/Ta/sub y/N metal gate on the thermal stability of MOS devices were investigated. The work function of the Hf/sub x/Ta/sub y/N metal gate can reach a value of /spl sim/4.6 eV (midgap of silicon) by suitably adjusting the Hf and Ta compositions. In addition, with a small amount of Hf incorporated into a TaN metal gate, excellent thermal stability of electrical properties, including the work function, the equivalent oxide thickness, interface trap density and defect generation rate characteristics, can be achieved after a post-metal anneal up to 950/spl deg/C for 45 s. Experimental results indicate that Ta-rich Hf/sub x/Ta/sub y/N is a promising metal gate for advanced MOS devices.     

Al/sub 2/O/sub 3/-Ge-on-insulator n- and p-MOSFETs with fully NiSi and NiGe dual gates

High-/spl kappa/ Al/sub 2/O/sub 3//Ge-on-insulator (GOI) n- and p-MOSFETs with fully silicided NiSi and germanided NiGe dual gates were fabricated. At 1.7-nm equivalent-oxide-thickness (EOT), the Al/sub 2/O/sub 3/-GOI with metal-like NiSi and NiGe gates has comparable gate leakage current with Al/sub 2/O/sub 3/-Si MOSFETs. Additionally, Al/sub 2/O/sub 3/-GOI C-MOSFETs with fully NiSi and NiGe gates show 1.94 and 1.98 times higher electron and hole mobility, respectively, than Al/sub 2/O/sub 3/-Si devices, because the electron and hole effective masses of Ge are lower than those of Si. The process with maximum 500/spl deg/C rapid thermal annealing (RTA) is ideal for integrating metallic gates with high-/spl kappa/ to minimize interfacial reactions and crystallization of the high-/spl kappa/ material, and oxygen penetration in high-/spl kappa/ MOSFETs.     

Enhancing leakage suppression in carbon-rich silicon junctions

Carbon-incorporated devices exhibit an increase in junction leakage relative to pure Si devices. The authors demonstrate that a leakage suppression of /spl sim/ 50 times can be achieved in carbon-rich (Si:C) junctions. This is accomplished by a prolonged annealing for 1 to 10 min at 850 /spl deg/C (much lower than typical annealing temperature of >1000/spl deg/C) and is attributed to a decrease in interstitial carbon concentration. After a 10-min annealing, the Si:C junctions display a leakage of 4/spl times/10/sup -13/ A//spl mu/m, which is much lower than that of 1050 /spl deg/C spike annealed Si junctions and well within the I/sub off/ requirements of low-standby-power device at the 45-nm node. Carbon-incorporated transistors with a gate length of 0.18 /spl mu/m exhibit an I/sub off/ reduction of /spl sim/ 10 times, compared to pure Si transistors, and both transistors have a similar subthreshold slope of 81 mV/dec.     

Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.     

Thermally robust TaTb/sub x/N metal gate electrode for n-MOSFETs applications

In this letter, we study Terbium (Tb)-incorporated TaN (TaTb/sub x/N) as a thermally robust N-type metal gate electrode for the first time. The work function of the Ta/sub 0.94/Tb/sub 0.06/N/sub y/ metal gate is determined to be /spl sim/4.23 eV after rapid thermal anneal at 1000/spl deg/C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb/sub x/N-SiO/sub 2/ gate stack exhibits excellent thermal stability up to 1000/spl deg/C with no degradation to the equivalent oxide thickness, gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTb/sub x/N) could be a promising metal gate candidate for n-MOSFET in a dual-metal gate Si CMOS process.     

Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.     

The thermal stability of one-transistor ferroelectric memory with Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-poly-SiO/sub 2/-Si gate stack

The thermal stability of one-transistor ferroelectric nonvolatile memory devices with a gate stack of Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-Poly-SiO/sub 2/-Si was characterized in the temperature range of -10/spl deg/C to 150/spl deg/C. The memory windows decrease when the temperatures are higher than 60/spl deg/C. The drain currents (I/sub D/) after programming to on state decrease with increasing temperature. The drain currents (I/sub D/) after programming to off state increase with increasing temperature. The ratio of drain current (I/sub D/) at on state to that at off state drops from 7.5 orders of magnitude to 3.5 orders of magnitude when the temperature increases from room temperature to 150/spl deg/C. On the other hand, the memory window and the ratio of I/sub D/(on)/I/sub D/(off) of the one-transistor memory device displays practically no change when the temperature is reduced from room temperature to -10/spl deg/C. One-transistor (1T) memory devices also show excellent thermal imprint properties. Retention properties of 1T memory devices degrade with increasing temperature over 60/spl deg/C.     

Effect of the composition on the electrical properties of TaSi/sub x/N/sub y/ metal gate electrodes

In this letter, the effect of silicon and nitrogen on the electrical properties of TaSi/sub x/N/sub y/ gate electrode were investigated. The TaSi/sub x/N/sub y/ films were deposited on SiO/sub 2/ using reactive cosputtering of Ta and Si target in Ar and N/sub 2/ ambient. The thermal stability of TaSi/sub x/N/sub y//SiO/sub 2//p-type Si stacks was evaluated by measuring the flatband voltage and equivalent oxide thickness at 400/spl deg/C and 900/spl deg/C in Ar. It was found that under high temperature anneals, Si-rich TaSi/sub x/N/sub y/ films increased and this was attributed to the formation of a reaction layer at the electrode-dielectric interface. Reducing the Si content alone did not prevent the formation of this reaction layer while removing Si completely by utilizing TaN resulted in work functions that were too high. The presence of both Si and N was deemed necessary and their content was critical in obtaining optimized TaSi/sub x/N/sub y/ gates that are suitable for NMOS devices.     

Effect of Mg doping on the superconducting properties of Cu/sub 1-x/Tl/sub x/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta//

Superconducting properties of Cu/sub 1-x/Tl/sub x/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta// (Cu/sub 1-x/Tl/sub x/Mg/sub y/-1234) material have been studied in the composition range y=0,1.5,2.25. The zero resistivity critical temperature [T/sub c/(R=0)] was found to increase with the increased concentration of Mg in the unit cell; for y=1.5 [T/sub c/(R=0)]=131 K was achieved which is hitherto highest in Cu/sub 1-x/Tl/sub x/-based superconductors. The X-ray diffraction analyses have shown the formation of a predominant single phase of Cu/sub 0.5/Tl/sub 0.5/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta// superconductor with an inclusion of impurity phase. It is observed from the convex shape of the resistivity versus temperature measurements that our as-prepared material was in the region of carrier over-doping, and the number of carriers was optimized by postannealing experiments in air at 400/spl deg/C, 500/spl deg/C, and 600/spl deg/C. The T/sub c/(R=0) was found to increase with postannealing and the best postannealing temperature was found to be 600/spl deg/C. The mechanism of increased T/sub c/(R=0) is understood by carrying out infrared absorption measurements. It was observed through softening of Cu(2)-O/sub A/-Tl apical oxygen mode that improved interplane coupling was a possible source of enhancement of T/sub c/(R=0) to 131 K.     

Robust high-quality HfN-HfO/sub 2/ gate stack for advanced MOS device applications

In this letter, a thermally stable and high-quality HfN-HfO/sub 2/ gate stack for advanced MOS applications is reported for the first time. Negligible changes in both equivalent oxide thickness (EOT) and work function of HfN-HfO/sub 2/ gate stack are demonstrated even after 1000/spl deg/C postmetal annealing (PMA), which is attributed to the superior oxygen diffusion barrier property of HfN as well as the thermal stability of the HfN-HfO/sub 2/ interface. Therefore, even without surface nitridation prior to HfO/sub 2/ deposition, the EOT of HfN-HfO/sub 2/ gate stack can be successfully scaled down to less than 10 /spl Aring/ after 1000/spl deg/C PMA with excellent leakage and long-term reliability.     

Improving the electrical integrity of Cu-CoSi/sub 2/ contacted n/sup +/p junction diodes using nitrogen-incorporated Ta films as a diffusion barrier

The study on improving the electrical integrity of Cu-CoSi/sub 2/ contacted-junction diodes by using the reactively sputtered TaN/sub x/ as a diffusion barrier is presented in this paper. In this study, the Cu (300 nm)-CoSi/sub 2/ (50 nm)/n/sup +/p junction diodes were intact with respect to metallurgical reaction up to a 350/spl deg/C thermal annealing while the electrical characteristics started to degrade after annealing at 300/spl deg/C in N/sub 2/ ambient for 30 min. With the addition of a 50-nm-thick TaN/sub x/ diffusion barrier between Cu and CoSi/sub 2/, the junction diodes were able to sustain annealing up to 600/spl deg/C without losing the basic integrity of the device characteristics, and no metallurgical reaction could be observed even after a 750/spl deg/C annealing in a furnace. In addition, the structure of TaN/sub x/ layers deposited on CoSi/sub 2/ at various nitrogen flow rates has been investigated. The TaN/sub x/ film with small grain sizes deposited at nitrogen flow ratios exceeding 10% shows better barrier capability against Cu diffusion than the others.     

Electrical properties of RuO/sub 2/ gate electrodes for dual metal gate Si-CMOS

The rutile stoichiometric phase of RuO/sub 2/, deposited via reactive sputtering, was evaluated as a gate electrode for Si-PMOS devices. Thermal and chemical stability of the electrodes was studied at annealing temperatures of 400/spl deg/C and 600/spl deg/C in N/sub 2/. X-ray diffraction patterns were measured to study grain structure and interface reactions. Very low resistivity values were observed and were found to be a strong function of temperature. Electrical properties were evaluated on MOS capacitors, which indicated that the workfunction of RuO/sub 2/ was compatible with PMOS devices. Excellent stability of oxide thickness, flatband voltage and gate current as a function of temperature was also found. Breakdown fields were also measured for the samples before and after annealing.     

MIM capacitors using atomic-layer-deposited high-/spl kappa/ (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ dielectrics

Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.     

DRAM plate electrode bias optimization for reducing leakage current in UV-O/sub 3/ and O/sub 2/ annealed CVD deposited Ta/sub 2/O/sub 5/ dielectric films

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O/sub 3/ and O/sub 2/ annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of V/sub cc//2. Ta/sub 2/O/sub 5/ films with 3.9 nm effective gate oxide, 8.5 fF//spl mu/m/sup 2/ capacitance and <0.3 /spl mu/A/cm/sup 2/ leakage at 100/spl deg/C and 3.3 V supply are demonstrated.<>     

Si/SiGe resonant interband tunnel diode with f/sub r0/ 20.2 GHz and peak current density 218 kA/cm/sup 2/ for K-band mixed-signal applications

This letter presents the room-temperature high-frequency operation of Si/SiGe-based resonant interband tunnel diodes that were fabricated by low-temperature molecular beam epitaxy. The resulting devices show a resistive cutoff frequency f/sub r0/ of 20.2 GHz with a peak current density of 218 kA/cm/sup 2/, a speed index of 35.9 mV/ps, and a peak-to-valley current ratio of 1.47. A specific contact resistivity of 5.3/spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ extracted from RF measurements was achieved by Ni silicidation through a P /spl delta/-doped quantum well by rapid thermal sintering at 430/spl deg/C for 30 s. The resulting devices are very good candidates for RF high-power mixed-signal applications. The device structures presented here are compatible with a standard complementary metal-oxide-semiconductor or heterojunction bipolar transistor process.     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

Use of WN/sub X/ as the diffusion barrier for interconnect copper metallization of InGaP-GaAs HBTs

Use of WN/sub X/ as the diffusion barrier for interconnect copper metallization of InGaP-GaAs heterojunction bipolar transistors (HBTs) was studied. The WN/sub X/ (40 nm) and Cu (400 nm) films were deposited sequentially on the InGaP-GaAs HBT wafers as the diffusion barrier and interconnect metallization layer, respectively, using the sputtering method. As judged from the data of scanning electron microscopy, X-ray diffraction, Auger electron spectroscopy, and sheet resistance, the Cu--WN/sub X/--SiN and Cu--WN/sub X/--Au structures were very stable up to 550/spl deg/C and 400/spl deg/C annealing, respectively. Current accelerated stress test was conducted on the Cu--WN/sub X/ metallized HBTs with V/sub CE/=2 V, J/sub C/=140 kA/cm/sup 2/ and stressed for 55 h, the current gain (/spl beta/) of these HBTs showed no degradation and was still higher than 100 after the stress test. The Cu--WN/sub X/ metallized HBTs were also thermally annealed at 250/spl deg/C for 25 h and showed no degradation in the device characteristics after the annealing. For comparison, HBTs with Au interconnect metallization were also processed, and these two kinds of devices showed similar characteristics after the stress tests. From these results, it is demonstrated that WN/sub X/ is a good diffusion barrier for the interconnection copper metallization of GaAs HBTs.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

Room-temperature self-organised In/sub 0.5/Ga/sub 0.5/As quantum dot laser on silicon

The first room-temperature operation of In/sub 0.5/Ga/sub 0.5/As quantum dot lasers grown directly on Si substrates with a thin (/spl les/2 /spl mu/m) GaAs buffer layer is reported. The devices are characterised by J/sub th//spl sim/1500 A/cm/sup 2/, output power >50 mW, and large T/sub 0/ (244 K) and constant output slope efficiency (/spl ges/0.3 W/A) in the temperature range 5-95/spl deg/C.