共查询到18条相似文献,搜索用时 328 毫秒
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缺陷是影响集成电路成品率与可靠性的主要因素.本文在区分缺陷与故障两个概念的基础上,将缺陷区分为成品率缺陷(硬故障)、可靠性缺陷(软故障)和良性缺陷.利用关键区域的面积,给出了一个缺陷成为"硬故障"或"软故障"的概率,给出了精度较高的IC成品率预测模型.利用成品率缺陷与可靠性缺陷之间的关系,给出了工艺线生产的产品的失效率与该工艺线制造成品率之间的定量关系.在工艺线稳定的条件下,通过该工艺线的制造成品率可以利用该关系式可以有效的估计出产品的失效率,可以有效地缩短了新产品的研发周期. 相似文献
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集成电路局部缺陷模型及其相关的功能成品率分析 总被引:2,自引:0,他引:2
大规模集成电路(VLSI)使亚微米特征尺寸的大面积集成电路制造以及集成数百万个器件在一芯片上成为可能。然而,缺陷的存在致使电路版图的拓扑结构发生变化,产生IC电路连接错误,导致电路丧失功能,从而影响IC的成品率,特别是功能成品率。文章主要对缺陷的轮廓模型、空间分布模型和粒径分布模型作了介绍;对集成电路成品率的损失机理作了详细论述。最后,详细介绍了功能成品率的分析模型。 相似文献
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工艺变化下互连线分布参数随机建模与延迟分析 总被引:1,自引:0,他引:1
随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,电路制造过程中的工艺变化已经成为影响集成电路互连线传输性能的重要因素.文中引入高斯白噪声建立了互连线分布参数的随机模型,并提出基于Elmore延迟度量的工艺变化下的互连延迟估计式;通过简化工艺变化量与互连线参数之间的关系式,对延迟一阶变化量与二阶变化量进行了分析,给出一般工艺变化下互连延迟的统计特性计算方法;另,针对线宽工艺变化推导出互连延迟均值与方差的计算公式.最后通过仿真实验对工艺变化下互连线延迟分析方法及其统计特性计算公式的有效性进行了验证. 相似文献
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非直角互连——布线技术发展的新趋势 总被引:4,自引:1,他引:3
由于集成电路制造工艺的不断提高 ,集成电路的设计规模遵循Moore定律持续向前发展 ,并出现了系统级芯片 (SOC)这一新的集成电路设计概念 .同时遇到的困难之一是互连线成为影响电路性能的决定因素 :芯片速度变慢、功耗增大、噪声干扰加剧 .若采用以往基于直角互连结构的基础模型进行互连线性能的优化 ,其能力受到限制 .于是 ,人们试图采用其他互连结构作为突破途径 ,以实现高性能的集成电路 .在这种技术需求与目前工艺支持的背景下 ,从 2 0世纪 90年代初出现的关于非直角互连的零散的、试探性的研究 ,将成为国际上布线领域新的热点研究方向 . 相似文献
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集成电路的制造工艺比较复杂。实验发现,芯片内部结构中的问题,将使管芯大量报废,对成品率影响甚大,本文采用“电解水氧化”显微技术,能够对电路芯片结构进行有效的检测,通过分析,有利于提高芯片的成品率和可靠性。文中提供了有关双极型中规模集成电路芯片的剖面显微图象。 相似文献
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由于集成电路制造工艺的不断提高,集成电路的设计规模遵循Moore定律持续向前发展,并出现了系统级芯片(SOC)这一新的集成电路设计概念.同时遇到的困难之一是互连线成为影响电路性能的决定因素:芯片速度变慢、功耗增大、噪声干扰加剧.若采用以往基于直角互连结构的基础模型进行互连线性能的优化,其能力受到限制.于是,人们试图采用其他互连结构作为突破途径,以实现高性能的集成电路.在这种技术需求与目前工艺支持的背景下,从20世纪90年代初出现的关于非直角互连的零散的、试探性的研究,将成为国际上布线领域新的热点研究方向.文中将针对非直角布线方面以往零散的研究工作进行总结与分析,指出了目前需要解决的关键技术,并结合自己的研究工作基础提出了可行的技术路线与设想. 相似文献
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传统集成电路制造工艺主要采用铝作为金属互连材料,但是随着晶体管尺寸越来越小,在0.13μm及以上制程中,一般采用铜大马士革互连工艺来提高器件的可靠性。铜互连工艺中需要用氮化硅作为穿孔图形蚀刻的阻挡层,由于氮化硅材质具有很强的应力,再加上制程中的热反应和蚀刻效应就会造成氮化硅层从界面掀起从而形成一种鼓包状缺陷(bubble defect)。文章通过调整并控制铜金属连线层间氧化电介质层的蚀刻速率,改变有机介质层(BARC)的沉积方法,以及改进产品的电路设计的检验规则,从而解决鼓包状缺陷的产生,降低产品芯片的报废率,提高产品的良率。 相似文献
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The problem of interconnect failure is studied in the framework of percolation theory. The probability failure of a long interconnect due to statistical fluctuations of defects is found. It is demonstrated that two possible diapasons of length to width ratios exist. For extremely long wires, the percolation threshold is determined by rare accumulation of defects, breaking down the wire. For moderately long wires, the threshold concentration of defects is near the macroscopic percolation threshold. The lowering of threshold due to finite width of wire is found. The percolation threshold is found in a two-dimensional system, containing the individual vacancies and voids, caused by coalescence of vacancies. 相似文献
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With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs. 相似文献
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Christie P. Jose Pineda de Gyvez 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2003,11(1):55-59
Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges. 相似文献
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The yield of IC assembly manufacturing is dependent on wire bonding. Recently, the semiconductor industry demands smaller IC designs and higher performance requirements. As such, bonding wires must be stronger, finer, and more solid. The cost of gold is continuously appreciating, and this has become a key issue in IC assembly and design. Copper wire bonding is an alternative solution to this problem. It is expected to be superior over Au wires in terms of cost, quality, and fine-pitch bonding pad design. To obtain the best wire bonding quality, we employed Taguchi methods in optimizing the Cu wire bonding process. With Cu wire bonding technology, the production yield increased from 98.5% to 99.3% and brought approximately USD 0.7 million in savings. 相似文献