Large-signal and small-signal models for arbitrarily-doped four-terminal field-effect transistors

Models are derived for a four-terminal field-effect transistor (FTFET) with an arbitrary (one-dimensional) impurity distribution. The models apply for both four-terminal and conventional three-terminal devices operated in either the pinch-off or nonpinch-off modes; moreover, they describe behavior when either large or small signals are applied to the gates. The model parameters can be determined either from terminal measurements or from knowledge of the physical make-up. Because an arbitrary impurity distribution is assumed in their derivation, the models represent devices made with any of the common fabrication techniques. Measured step-function response of epitaxial, single-diffused and double-diffused FTFET's shows good agreement with calculated behavior for broad ranges of resistive source and load terminations.     

Comparison of input offset voltage of differential amplifiers using bipolar transistors and field-effect transistors

A field-effect transistor (whether junction type or MOS type) has very high input impedance. For those who desire to achieve a higher input impedance, it is often asked `Why aren't FET pairs used as input stages and bipolar transistors used as output stages, since compatible FET and bipolar transistor monolithic structures have been developed?' This correspondence is a study of this question.     

Four-terminal field-effect transistors

A derivation is presented for the transconductances of a four-terminal transistor of arbitrary channel doping profile. The derivation takes into account finite barrier potential and is specifically applied to the symmetrical, abrupt-junction, four-terminal, field-effect transistor. Curves are presented showing variations of normalized transconductance with applied gate-source EMF.     

Realization of electrically stable organic field-effect transistors using simple polymer blended dielectrics

Organic field-effect transistors (OFETs) were fabricated using polymer blended gate dielectrics in an effort to enhance the electrical stability against a gate bias stress. A poly(melamine-co-formaldehyde) acrylated (PMFA) gate dielectric layer with great insulating properties was blended with polypentafluorostyrene (PFS), a type of hydrophobic fluorinated polymer. Although the overall electrical performance dropped slightly due to the rough and hydrophobic surfaces of the blend films, at the blend ratio (10%), the OFET’s threshold voltage shift under a sustained gate bias stress applied over 3 h decreased remarkably compared with an OFET based on a PMFA dielectric alone. This behavior was attributed to the presence of the hydrophobic and electrically stable PFS polymer, which provided a low interfacial trap density between the gate dielectric and the semiconductor. A stretched exponential function model suggested that the energetic barrier to create trap states was high, and the distribution of energetic barrier heights was narrow in devices prepared with PFS.     

Amorphous-silicon silicon-nitride field-effect transistors

n-channel and p-channel amorphous-silicon field-effect transistors have been fabricated on a glassy substrate using undoped and impurity-doped a-Si films as the semiconductor and silicon nitride deposited from an SiH4-N2 mixture as the gate insulator. A change in the source-drain conductance of greater than four orders of magnitude is realised by changing the gate potential from 0 to 5 V.     

InP Schottky-gate field-effect transistors

MESFET's with gates 1 µm long were fabricated in LPE layers of InP on Cr-doped InP substrates. The quality of the LPE material is characterized by an electron concentration of 4 × 10¹⁵cm^-3with a mobility of 2.6 × 10⁴cm²V^-1s^-1at 77 K for growths from undoped melts. The devices have current gain cutoff frequencies of 20 GHZ or somewhat larger. This value is greater than that of the best analogous GaAs MESFET bya factor of 1.5. A factor of 1.3 is predicted on the basis of a simple theory. The highest power gain cutoff frequency, fmax, for the InP device is 33 GHz which is somewhat smaller than that of the best analogous GaAs device. The lowest minimum noise figure at 10 GHz for these first InP devices is 3.9 dB with an associated gain of 4.8 dB. The best result for the GaAs counterpart is 3.2 dB with an associated gain of 7.8 dB. The power gain of the InP device suffers compared to the GaAs device because of degenerative feedback resulting from a large gate-to-drain capacitance and because of a small output resistance. If the magnitudes of these two equivalent circuit elements were the same for MESFET's in the two materials, fmaxfor the InP device would be more than double its present value.     

Medium-power GaAs field-effect transistors

Results on medium-power GaAs m.e.s.f.e.t.s. are described. Output powers as high as 300 mW at 9 GHz at 1 dB gain compression with a linear gain of 5.2 dB and drain efficiency of 30% have been obtained with single-cell m.e.s.f.e.t.s. At 4 GHz, a power output of 665 mW at 1 dB gain compression, a linear gain of 8 dB and a drain efficiency of 44.5% were realised with a 3-cell m.e.s.f.e.t. Two-tone intermodulation characteristics at 4 GHz are also described. A major innovation has been the use of a high-resistivity chromium-doped epitaxial GaAs buffer layer to isolate the device active region from the bulk-grown substrate.     

Nonplanar power field-effect transistors

This paper reviews the criteria involved in the design of silicon power field-effect transistors. Particular emphasis is placed on recent nonplanar structures which will, in the near future, present a serious challenge to bipolar power transistors as linear amplifiers and high-speed switches.     

Applications of resonant-tunneling field-effect transistors

Flip-flop and frequency-doubling operations are demonstrated, using a simple circuit that combines a resistor with a three-terminal negative-resistance device. The device is a series integration of resonant-tunneling heterostructure with a field-effect transistors. Results, obtained at 77 K, are presented for two samples that were grown by metalorganic chemical vapor deposition     

Gallium arsenide traveling-wave field-effect transistors

The design, modeling, and fabrication of a GaAs traveling-wave field-effect transistor (TWF) is reported. The TWF described is a device with a single continuous 1-µm-long gate and a total width of 3 mm which shows flat band gain from 1 to 10 GHz with the potential of much wider band performance (1-40 GHz) and high gains. An advanced theoretical model is presented which performs a full coupled transmission line modal analysis for three lines (source gate and drain) using ab.initio calculations of interelectrode capacitance and inductance matrices. Good agreement is demonstrated between theory and experiment for frequency gain response measurements using balanced feed circuits.     

Ultrathin CdSe nanowire field-effect transistors

We report the fabrication, and electrical and optical characterization, of solution-liquid-solid (SLS) grown CdSe nanowire field-effect transistors. Ultrathin nanowires (7–12 nm diameters) with lengths between 1 μm and 10 μm were grown by the SLS technique. Al-CdSe-Al junctions are then defined over oxidized Si substrate using photolithography. The nanowires, which were very resistive in the dark, showed pronounced photoconductivity even with a visible light source with resistance decreasing by a factor of 2–100 for different devices. Field-effect devices fabricated by a global backgating technique showed threshold voltages between −7.5 V and −2.5 V and on-to-off channel current ratios between 10³ and 10⁶ at room temperature. Channel current modulation with gate voltage is observed with the current turning off for negative gate bias, suggesting unintentional n-type doping. Further, optical illumination resulted in the loss of gate control over the channel current of the field-effect transistor.     

Indium phosphide accumulation-mode field-effect transistors

Enhancement-type insulated gate field-effect transistors made of semi-insulating InP depend on the surface accumulation of electrons induced by a positive gate voltage and an equilibrium surface potential whose sign and magnitude are considered to be functions of the difference between charged surface donor and occupied acceptor states.     

Proposed vertical-type amorphous-silicon field-effect transistors

Novel amorphous-silicon field-effect transistors (a-Si FET's) with a vertical channel have been proposed and demonstrated for the first time. The channel length of the new FET's is not limited by the photoetching process and thus can be reduced a great deal. Prototype FET's with a channel length of 1 µm had an on-off current ratio of more than 10⁴and the on-resistance was proportional to the channel length, so far as it was longer than 1 µm.     

Novel microwave GaAs field-effect transistors

A technology is described for the fabrication of Schottky-barrier f.e.t.s with electrodes on either or both sides of a submicrometre thick single-crystal layer of GaAs. Preliminary d.c. and microwave results are given together with possible advantages of these novel f.e.t. structures.     

The cylindrical field-effect transistor

The characteristics of a cylindrical field-effect transistor are derived analytically on the basis of Shockley's theory of the planar field-effect transistor. It is found that the cylindrical device is capable of giving twice the (voltage) amplification factor of that of the planar device. Its frequency behavior should be comparable to that of the Shockley unit. Because of the loss of one degree of freedom, the transconductance and power characteristics of the cylindrical field-effect transistor are sharply limited. Experimental data support the analytical results.     

High-speed gallium-arsenide Schottky-barrier field-effect transistors

The letter shows that gallium arsenide is a well suited material for high-frequency field-effect transistors. From preliminary measurements on realised transistors, it is shown that the frequency limit for power amplification is considerably higher than for other known transistors. The processes involved are briefly described.     

Transient performance of four-terminal field-effect transistors

This paper extends previous work on the low-frequency operation of four-terminal field-effect transistors (FTFET's) by developing a model for the transient as well as the low-frequency performance of a symmetrical device, operating in the region beyond pinch-off. The model, which represents the FTFET in any of its possible modes of operation, is derived systematically from consideration of the physical makeup of the device. As a consequence, the element values are determined as explicit functions of the physical makeup and the bias voltages at the two gates; alternatively, they can be determined from a set of terminal measurements. In addition, in conjunction with the development of the model, expressions are derived for the functional dependence on gate biases of the gate-source capacitances present in any of the various modes of operation. Experimental results for the step-function response of the device are in good agreement with theory for broad ranges of source and load terminations. Good correlation has also been obtained for the functional dependence of the gate-source capacitances.     

Low-frequency operation of four-terminal field-effect transistors

Interesting and useful behavior is obtained by operating a two-gate field-effect transistor as a four-terminal device. This paper considers important aspects of the low-frequency four-terminal behavior of a transistor with symmetrical geometry. The functional dependence of the drain current upon gate bias voltages and material and structural constants is determined, and four general modes of operation of the device are defined. For each mode the dependence of relevant transconductances on gate biases is calculated. Special cases of interest are analyzed, including that in which the transconductance exhibits a linear variation with gate bias voltage. Experimental results are in good agreement with the theory.     

Output characteristics of short-channel field-effect transistors

A recent model for hot-electron MOS transistors [4], [5] is generalized for short-channel field-effect transistors. It is based on six to seven parameters for the carrier mobility under the influence of transverse and Iongitudinal electric fields, for the threshold voltage and its dependence on drain bias, and for a finite longitudinal field at pinch-off. Such important features of short-channel FET's like reduced available current and voltage gain are well represented, where the latter turns up as important limiting factor in submicron devices. Effects of zero-field mobility, impurities, and device geometry are stated explicitly. The results are confirmed by measured data on 0.9-µm silicon gate MOSFET's.