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1.
《Microelectronics Reliability》2014,54(12):2760-2765
A bottom-gate/top-drain/source contact ZnO nanoparticle thin-film transistor was fabricated using a low temperature annealing process (150 °C) suitable for flexible electronics. Additionally, a high-k resin filled with TiO2 nanoparticles was used as gate dielectric. After fabrication, the transistors presented almost no hysteresis in the IV curve, a threshold voltage (VT) of 2.2 V, a field-effect mobility on the order of 0.1 cm2/V s and an ION/IOFF ratio of about 104. However, the transistor is sensitive to aging effects due to interactions with the ambient air, resulting in current level reduction caused by trapped oxygen at the nanoparticle surface, and an anti-clockwise hysteresis in the transfer curve. It was demonstrated, conjointly, the possible desorption of oxygen by voltage stress and UV light exposure.  相似文献   

2.
《Applied Superconductivity》1996,4(10-11):487-493
Biaxially aligned yttria-stabilized zirconia (YSZ) films on Ni-based alloy substrates were realized with high deposition rate of 0.5 μm min−1 by the inclined substrate deposition (ISD) technique without ion beam assistance. The microstructure of YSZ was examined to study the growth mechanism of biaxial alignment by ISD. Columnar structures toward the plasma plume suggested a self-shadowing effect in the ISD process. To raise Ic values, YBCO thickness was increased up to 5 μm. Thick YBCO films with high Jc values were realized on the ISD-grown YSZ. Long YBCO tapes with biaxial alignment were successfully fabricated using continuous pulsed laser deposition and a high Ic value of 37.0 A (77.3 K, 0 T) at a 75 cm voltage tap spacing was achieved.  相似文献   

3.
Commercial bipolar junction transistor (2N 2219A, npn) irradiated with 150 MeV Cu11+-ions with fluence of the order 1012 ions cm?2, is studied for radiation induced gain degradation and deep level defects. IV measurements are made to study the gain degradation as a function of ion fluence. The properties such as activation energy, trap concentration and capture cross-section of deep levels are studied by deep level transient spectroscopy (DLTS). Minority carrier trap levels with energies ranging from EC ? 0.164 eV to EC ? 0.695 eV are observed in the base–collector junction of the transistor. Majority carrier trap levels are also observed with energies ranging from EV + 0.203 eV to EV + 0.526 eV. The irradiated transistor is subjected to isothermal and isochronal annealing. The defects are seen to anneal above 350 °C. The defects generated in the base region of the transistor by displacement damage appear to be responsible for transistor gain degradation.  相似文献   

4.
In this paper we describe a method for growing vertically aligned bundles of Mo6S9?xIx (4.5<x<6) nanowires perpendicular with respect to the substrate. In this efficient method, a one-step synthesis directly from molybdenum, sulphur and iodine in the temperature gradient conditions is used. Bundles with similar lengths could be grown on quartz or conductive materials like molybdenum foil at the temperature of around 1040 K. X-ray diffraction (XRD), scanning electron spectroscopy (SEM) and transmission electron microscopy (TEM) were used to characterize the obtained bundles of nanowires. Due to the similar lengths of the aligned bundles and their easiness to disperse in some polar solvents, this material could potentially be used also for applications like building blocks in nanodevices.  相似文献   

5.
We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (IDVG) curve due to the formation of a conducting channel layer. The specific contact resistance (ρC) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm2/V·s), ON/OFF current ratio (3.27×106), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm2 at VG=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.  相似文献   

6.
《Microelectronic Engineering》2007,84(9-10):2058-2062
In this article the impact of Si-substrate orientation on mobility performance is studied for p-MOSFET’s with both HfSiON and SiON based dielectrics. Consistent with previous studies, the Ion at fixed Ioff is 100% larger for Si(1 1 0) larger than for standard Si(1 0 0). A thorough analysis of the factors influencing Ion (EOT, mobility and Rseries) for short channel devices (until Lmet = 80 nm) indicates that a 200% increase of the mobility at high Vg is the source of this performance enhancement. The lower Ion increase (only 100%) compared to what is expected from the mobility is only explained by a larger impact of the Rseries (70% of the total resistance) for short channel devices. As a result additional room for Ion improvement can be reached by device and Rseries optimization.  相似文献   

7.
A Mo/n-type 6H-SiC/Ni Schottky barrier diode (SBD) was fabricated by sputtering Mo metal on n-type 6H-SiC semiconductor. Before the formation of Mo/n-type 6H-SiC SBD, an ohmic contact was formed by thermal evaporation of Ni on n-type 6H-SiC and annealing at 950 °C for 10 min. It was seen that the structure had excellent rectification. The electrical parameters were extracted using its current–voltage (IV) and capacitance–voltage (CV) measurements carried out at room temperature. Very high (1.10 eV) barrier height and 1.635 ideality factor values were reported for Mo/n-type 6H-SiC using ln IV plot. The barrier height and series resistance values of the diode were also calculated as 1.413 eV and 69 Ω from Norde׳s functions, respectively. Furthermore, 1.938 eV barrier height value of Mo/n-type 6H-SiC SBD calculated from CV measurements was larger than the one obtained from IV data.  相似文献   

8.
Si-based field-plate 0.13 μm gate length metal-oxide-semiconductor field effect transistor (Si MOSFET) with field-plate (FP) lengths of 0.1 μm, 0.2 μm, and 0.3 μm have been fabricated and investigated. The field-plate metals were connected to gate electrode in this study to improve device gate resistance (Rg) resulting in the better microwave performance. By increasing the length of field-plate metal extension (LFPE), the off-state drain-to-source surface leakage current can be suppressed. Besides, low surface traps in FP NMOS also leads to a higher drain-to-source current (Ids) especially at high current regime compared to standard device. The power added efficiency (PAE) was 56.3% for LFPE of 0.3 μm device, and these values where 54.7% and 53.8% for LFPE of 0.2 μm and 0.1 μm devices, respectively. Wider field-plate metal extension exhibits highly potential for low noise amplifier and high efficiency power amplifier applications.  相似文献   

9.
《Organic Electronics》2014,15(8):1799-1804
Copper phthalocyanine (CuPc)-based thin film transistors were fabricated using CuPc films grown under different deposition pressure (Pdep) (ranging from 1.8 × 10−4 Pa to 1.0 × 10−1 Pa). The transistor performance highly depended on Pdep. A field-effect mobility of 2.1 × 10−2 cm2/(V s) was achieved under 1.0 × 10−1 Pa. Detailed investigations revealed that Pdep modulates the molecular packing and orientation of the organic films grown on a SiO2/Si substrate and influences the charge transport. Furthermore, from a device physics point of view, contact resistance of the fabricated transistors decreased when Pdep increased, which was beneficial in reducing energy consumption.  相似文献   

10.
《Solid-state electronics》2006,50(9-10):1483-1488
A new self-aligned emitter–base metallization (SAEBM) technique with wet etch is developed for high-speed heterojunction bipolar transistors (HBTs) by reducing extrinsic base resistance. After mesa etch of the base layer using a photo-resist mask, the base and emitter metals are evaporated simultaneously to reduce the emitter–base gap (SEB) and base gap resistance (RGAP). The InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) fabricated using the technique has a reduced RGAP, from 16.48 Ω to 4.62 Ω comparing with the DHBT fabricated by conventional self-aligned base metallization (SABM) process. Furthermore, we adopt a novel collector undercut technique using selective etching nature of InP and InGaAs to reduce collector–base capacitance (CCB). Due to the reduced RGAP, the maximum oscillation frequency (fmax) for a 0.5 μm-emitter HBT is improved from 205 GHz to 295 GHz, while the cutoff frequency (fT) is maintained at around 300 GHz.  相似文献   

11.
《Organic Electronics》2014,15(1):35-39
The temperature dependence of poly(3-hexylthiophene-2,5-diyl) (P3HT)/polystyrene (PS) blend organic transistor current/voltage (IV) characteristics has been experimentally and theoretically studied. The planar transistors, realized by drop casting the P3HT/PS ink, exhibit high mobilities (over 5 × 10−3 cm2 V−1 s−1) and good overall characteristics. A transistor model accounting for transport mechanisms in disordered organic materials was used to fit the measured characteristics. Using a single set of parameters, the measured effective mobility versus gate bias, either increasing or decreasing with the gate bias depending on temperature, is well reproduced over a wide temperature range (130–343 K). A Gaussian density of states width of 0.045 eV was determined for this P3HT/PS blend. The transistor IV characteristics are very well described considering disordered material properties within a self-consistent transistor model.  相似文献   

12.
《Applied Superconductivity》1997,5(7-12):319-325
We have fabricated NbN Josephson junctions with NbNx barriers formed by plasma nitridation on the surface of the base superconductive NbN layer. Both nonhysteretic junctions (overdamped junctions) and small-hysteretic ones have been obtained at 4.2 K by changing plasma nitridation conditions. An overdamped junction showed a product of the critical current Ic and junction resistance Rn (an IcRn product) of 0.95 mV at 4.2 K and the Ic exponentially decreased with increasing temperature. On the other hand, a small-hysteretic junction showed Superconductor-Insulator-Superconductor (SIS)-like characteristics in the temperature dependence of Ic and its current–voltage characteristics changed to nonhysteretic ones at the temperature more than 8 K. The IcRn product for the junction was 0.91 mV at 8.2 K.  相似文献   

13.
Benzopyrazine-fused tetracene (TBPy) and its disulfide (TBPyS) bearing alkoxy groups (OCH3, OC8H17) were designed and synthesized to obtain π-expanded tetracene derivatives. These derivatives are featured with long-wavelength light absorption property (λonset: up to 820 nm), photooxidative stability (half-lives (τ1/2): 11 times longer than tetracene), and solubility for solution process. The methoxy compounds (TBPy-C1 and TBPyS-C1) were used for single-crystal X-ray crystallographic analysis and single-crystal organic field-effect transistor (OFET) devices showing relationship between packing structures and hole mobilities. The octyloxy compounds (TBPy-C8 and TBPyS-C8) were investigated on solution-processed thin-film formation and hole transport property in thin-film OFET devices. Crystalline mesophase of TBPy-C8 and TBPyS-C8 was characterized by differential scanning calorimetry analysis showing endothermic peaks at 98 and 198 °C on its second heating process and exothermic peaks at 177 and 76 °C on its second cooling process for TBPyS-C8, and played crucial roles in thin-films formation. Hole mobility of 1.7 × 10?2 cm2/V s (with Vth = ?30 V and ION/IOFF = 104) was obtained for the thin-film OFET device of TBPyS-C8.  相似文献   

14.
We report on a newly developed solution process using MoO3 for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoOx solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm2/V s. Most notably, the threshold voltage (Vth) shift under gated bias stress was less than 0.2 V after 105 s, which is comparable to that of conventional poly crystalline Si TFT.  相似文献   

15.
《Microelectronics Reliability》2014,54(11):2401-2405
A high-performance InGaZnO (IGZO) thin-film transistor (TFT) with ZrO2–Al2O3 bilayer gate insulator is fabricated. Compared to IGZO-TFT with ZrO2 single gate insulator, its electrical characteristics are significantly improved, specifically, enhancement of Ion/Ioff ratios by one order of magnitude, increase of the field-effect mobility (from 9.8 to 14 cm2/Vs), reduction of the subthreshold swing from 0.46 to 0.33 V/dec, the maximum density of surface states at the channel-insulator interface decreased from 4.3 × 1012 to 2.5 × 1012 cm2. The performance enhancements are attributed to the suppression of leakage current, smoother surface morphology, and suppression of charge trapping by using Al2O3 films to modify the high-k ZrO2 dielectric.  相似文献   

16.
Bidirectional negative differential resistance (NDR) at room temperature with high peak-to-valley current ratio (PVCR) of ~10 are observed from vertical organic light-emitting transistor indium-tin oxide (ITO)/N,N′-di(naphthalene-1-yl)-N,N′-diphenyl-benzidine) (α-NPD)(60 nm)/Al(30 nm)/α-NPD(60 nm)/tris-(8-hydroxyquinoline) aluminium (Alq3)(50 nm)/Al by narrowing the transport channels for charge carriers with a thick-enough middle Al gate electrode layer to block charge carriers transporting from source electrode to drain electrode. When the transport channel for charge carriers gets large enough, the controllability of gate bias on the drain–source current gets weaker and the device almost works as an organic light-emitting diode only. Therefore, it provides a very simple way to produce NDR device with dominant bidirectional NDR and high PVCR (~10) at room temperature by narrowing transport channels for charge carriers in optoelectronics.  相似文献   

17.
《Solid-state electronics》2006,50(9-10):1515-1521
Al0.26Ga0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μHall) of 1770 cm2/Vs with a low sheet resistance (ρs) of 365 Ω/sq. (2DEG density ns = 1.0 × 1013/cm2) at room temperature compared with those of a sample without the AlN interfacial layer (μHall = 1287 cm2/Vs, ρs = 539 Ω/sq., and ns = 0.9 × 1013/cm2). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs.  相似文献   

18.
All RF sputtering-deposited Pt/SiO2/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (IV) and capacitance–voltage (CV) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (IV) and 0.82 eV (CV) after annealing at 400 °C for 15 min in N2 ambient, compared to that of 0.67 eV (IV) and 0.79 eV (CV) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10−7 A for the as-deposited to 1.4×10−7 A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (Rs) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by CV measurement.  相似文献   

19.
The present study is on the optoelectronic properties of isotype CdTe/c-Si heterojunction photodetector made by deposition of CdTe by pulsed laser deposition (PLD) technique on clean monocrystalline Si. Optical, electrical and structural properties of grown CdTe film were investigated. The optical data show that the optical band gap of CdTe was around 1.45 eV at 300 K. The CdTe/Si junction exhibits fair diode rectification and the soft breakdown occurred at VB>9 V. Dark and illuminated IV characteristics of the CdTe/Si photodetector are examined at room temperature. The photodetector showed good photosensitivity in the visible and near-infrared regions with a value as high as 0.5A/W at 950 nm.  相似文献   

20.
Many applications that rely on organic electronic circuits still suffer from the limited switching speed of their basic elements – the organic thin film transistor (OTFT). For a given set of materials the OTFT speed scales inversely with the square of the channel length, the parasitic gate overlap capacitance, and the contact resistance. For maximising speed we pattern transistor channels with lengths from 10 μm down to the sub-micrometre regime by industrially scalable UV-nanoimprint lithography. The reduction of the overlap capacitance is achieved by minimising the source–drain to gate overlap lengths to values as low as 0.2 μm by self-aligned electrode definition using substrate reverse side exposure. Pentacene based organic thin film transistors with an exceptionally low line edge roughness <20 nm of the channels, a mobility of 0.1 cm2/Vs, and an on–off ratio of 104, are fabricated on 4″ × 4″ flexible substrates in a carrier-free process scheme. The stability and spatial distribution of the transistor channel lengths are assessed in detail with standard deviations of L ranging from 185 to 28 nm. Such high-performing self-aligned organic thin film transistors enabled a ring-oscillator circuit with an average stage delay below 4 μs at an operation voltage of 7.5 V.  相似文献   

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