A single poly EEPROM cell structure for use in standard CMOSprocesses

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a “floating gate”. The inversion layer as “control node (gate)”. Test chips which were fabricated in a 0.8 μm/150 Å standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits     

Embeded EEPROM Memory Achieving Lower Power - New design of EEPROM memory for RFID tag IC

A 2-kb embedded EEPROM memory, operating over a wide voltage range (typically 2.5 V-5 V), was designed and fabricated using the SMIC 0.35-mum 2P3M CMOS embedded EEPROM process. The chip size is about 0.6 mm². The method of adding control transistors improved the static power dissipation. The transient power consumption of the charge pump circuit was greatly reduced by using a slowly varying clock. The proposed SA using a voltage sensing method also significantly improved the read power dissipation. By employing these techniques, a low-power embedded EEPROM memory with 40 muA read current and 250 muA page write current was developed, that achieved much lower power than EEPROM memory designs reported in scientific journals or conferences. This EEPROM memory was used in the ISO/IEC 15693-compatible RFID tag IC project     

In-band clock distribution concept for ultra-high bit rates OTDM system

A novel clock distribution concept based on inband phase-modulated pilot insertion is demonstrated.This method avoids the need for an ultrafast phase comparator and a phase-locked loop in the receiver.Experimental results show that the clock can be successfully extracted from 160Gbit/s optical time-division multiplexing (OTDM) data signal and employed for demultiplexing of 40Gbit/s tributaries.The in-band clock distribution introduces 1.5dB of power penalty with an error-free performance.     

A 16-Mb flash EEPROM with a new self-data-refresh scheme for asector erase operation

A 16-Mb flash EEPROM has been developed based on the 0.6-μm triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 μm×1.7 μm, resulting in a die size of 7.7 mm×17.32 mm     

Electrical/thermal properties of nonplanar polyoxides and theconsequent effects for EEPROM cell operation

The electrical/thermal properties of nonplanar polyoxides and the resulting effects for EEPROM operational margins are reported. The polyoxide between floating gate (FG) and control gate (CG) of FLOTOX-type EEPROM cells is nonplanar because it always contains edges, where CG wraps over FG. At such edges a highly stable electrical passivation of Fowler-Nordheim (FN) leakage currents occurs, which can cause a degradation of EEPROM operational margins, due to an electron discharge mechanism from the FG of charged EEPROM cells during the first charging operation after conventional baking. The EEPROM cell study includes the dependence on repeated passivation/depassivation of the polyoxide, on baking temperature and baking time. It is found that the average magnitude of the electron discharge is reduced after each passivation/depassivation cycle, which points to a progressive increase of the number of electrons captured in deep neutral electron traps at the polyoxide edges. Analysis of the temperature dependence leads to an activation energy (thermal detrapping energy of the electrons) of 1.3 eV for the degradation mechanism of EEPROM cell operational margins as well as the nonplanar polyoxide depassivation     

Microchip将业务重心拓展到16位MCU

美国微芯科技公司（Microchip Technology）最近宣布，在其8位单片机（MCU）业务发展的基础上，将公司业务重心拓展到16位MCU市场，并推出了该公司首个16位MCU系列产品PIC24和第二个16位数字信号控制器（DSC）系列产品ds PIC33F。这两个系列产品的目标是为了满足设计人员对性能、存储器和外设等方面日益增长的需求。     

一种用于模拟电路修调的EEPROM电路

介绍了一种用在模拟电路中修调的EEPROM电路.该电路采用一种新型的单层多晶EEPROM结构,与传统的双栅EEPROM结构相比,该结构与数字CMOS工艺兼容,成本低、成品率高.使用在一个基准电压电路中时,其基准电压的调节范围达到±4.82%,调节精度达到4mV.EEPROM修调电路可广泛应用于各种高精度需求的电路中.     

Modeling for the 2nd-bit effect of a nitride-based trapping storage flash EEPROM cell under two-bit operation

In this letter, we propose a macromodeling approach for the nitride-based trapping storage Flash EEPROM cell with intriguing 2nd-bit effect. Both unusual I/sub D/-V/sub D/ and I/sub D/-V/sub G/ characteristics of this 2-bit Flash cell can be accurately modeled by the macromodel. It also provides insights into the special device characteristics of the programmed cell. Furthermore, we can use this model to correctly evaluate the read speed degradation resulting from 2nd-bit effect.     

New group demodulator for bandlimited and bit asynchronous FDMAsignals

The authors propose a group demodulator that employs the multisymbol chirp Fourier transform to demodulate pulse-shaped and time-asynchronous signals. Computer simulation results show that the bit error rate degradation of the proposed group demodulator at BER=10^-3 is less than 0.3 dB with a 7 symbol chirp Fourier transform     

New bit rate reduction techniques for block truncation coding

Two simple and fast block truncation coding algorithms which require reduced bit rates are presented in this paper. The proposed algorithms are compared with the modified block truncation coding technique (MBTC) with regard to the mean square error (MSE), bit rates and subjective quality of the reconstructed images. It is found that the results obtained with the proposed algorithms at reduced bit rates are comparable to those obtained with the MBTC. Further, it is shown that one of the proposed algorithms yields results which are comparable to those achieved with more complex hybrid algorithms     

New concept for multiple-valued optical memory

The authors propose and demonstrate a new concept for multiple-valued optical memory, instead of the usual binary optical memory, based on the recognition of an angle of the slender diffracted-light pattern from one of the slits or slender pits formed, in order, along a track of the optical disk. A photodiode array arranged in a clock face configuration is used for the light pattern recognition     

An EEPROM for microprocessors and custom logic

An EEPROM extension to a 2.5-/spl mu/ n-well CMOS technology has been developed. In this technology an EEPROM has been designed that is suitable for integration with (existing) microprocessors in a baseline 5 V technology. A 2K EEPROM memory module, usable as a building block in a cell library for custom logic, measures 3.2 mm/SUP 2/ with a memory cell area of 440 /spl mu/m/SUP 2/.     

An endurance evaluation method for flash EEPROM

Trap generation is hard to estimate in a Flash cell due to a dynamic stress field during program and erase. In this paper, a linear correlation is found between the erase state V/sub T/ rollup and cycling V/sub T/ window. With the knowledge of the time dependence of erase stress field based on Fowler-Nordheim (FN) tunneling, the V/sub T/ rollup during cycling is evaluated by incorporating field dependent oxide trap generation. The extracted /spl Delta/V/sub T/ degradation slope during constant FN stress can be applied quantitatively to predict the V/sub T/ window closure during Flash cell cycling.     

基于位运算与海明距离的Apriori算法改进

关联规则现在已成为数据挖掘领域中非常重要的研究课题,用于发现隐藏在大型数据集中的令人感兴趣的联系。Apriori算法作为第一个关联规则挖掘算法,开创性地使用了基于支持度的剪枝技术,系统地控制了候选项集的指数增长。但是,Apriori算法仍然存在着频繁扫描数据库和产生大量候选项集的缺点。鉴于此,提出了用一个整型或整型数组来代替一项事务集和一项候选项集,通过数据压缩,可以一次性将海量数据载入内存,减少了磁盘I/O负载,并通过位运算与计算海明距离达到计算支持度的目的,同时使用了若干优化方法。     

New adaptive-signal-processing concept

A new device is proposed that combines a surface-wave memory with an acoustoelectric convolver to yield an adaptive real-time correlator and convolver. The principal difficulty in combining these devices is obtaining short intense electron bursts in a small gap between a piezoelectric and a semiconductor.     

基于位运算与海明距离的Apriori算法改进

关联规则现在已成为数据挖掘领域中非常重要的研究课题,用于发现隐藏在大型数据集中的令人感兴趣的联系。Apriori算法作为第一个关联规则挖掘算法,开创性地使用了基于支持度的剪枝技术,系统地控制了候选项集的指数增长。但是,Apriori算法仍然存在着频繁扫描数据库和产生大量候选项集的缺点。鉴于此,提出了用一个整型或整型数组来代替一项事务集和一项候选项集,通过数据压缩,可以一次性将海量数据载入内存,减少了磁盘I/O负载,并通过位运算与计算海明距离达到计算支持度的目的,同时使用了若干优化方法。     

Analysis of balanced active doubler for broad-band operation - thefrequency-tuning concept

A comprehensive analysis of an active balanced frequency doubler is described and proposed as a new concept: tuning the center frequency at which the doubler exhibits its highest performance to extend the usable bandwidth of the device. The concept is validated using a fabricated V-band pseudomorphic high electron-mobility transistor frequency doubler. For this device, a substantial improvement in the usable bandwidth (more than double) is achieved, demonstrating that the proposed concept is particularly suitable for the realization of high spectral purity and widely tunable V-band frequency sources     

A new concept for high-efficiency operation of high-low-type GaAs IMPATT diodes

A new operation mode, the "surfing mode," is proposed as an explanation for the high-efficiency operation of high-low-type GaAs IMPATT diodes. This mode is characterized by the concept that the avalanche charge pulse drifts synchronously with the movement of the front edge of the depletion layer at a velocity higher than the saturation velocity. The design chart of high-low-type GaAs IMPATT diodes is determined on the basis of the concept of the "surfing mode." The high-low-type GaAs IMPATT diodes designed using this chart exhibited output powers of 15.3 W (Delta T_{j}= 210°C) at 6.1 GHz with 25-percent efficiency.     

New Mix codes for multiple bit upsets mitigation in fault-secure memories

Nowadays, multibit error correction codes (MECCs) are effective approaches to mitigate multiple bit upsets (MBUs) in memories. As technology scales, combinational circuits have become more susceptible to radiation induced single event transient (SET). Therefore, transient faults in encoding and decoding circuits are more frequent than before. Firstly, this paper proposes a new MECC, which is called Mix code, to mitigate MBUs in fault-secure memories. Considering the structure characteristic of MECC, Euclidean Geometry Low Density Parity Check (EG-LDPC) codes and Hamming codes are combined in the proposed Mix codes to protect memories against MBUs with low redundancy overheads. Then, the fault-secure scheme is presented, which can tolerate transient faults in both the storage cell and the encoding and decoding circuits. The proposed fault-secure scheme has remarkably lower redundancy overheads than the existing fault-secure schemes. Furthermore, the proposed scheme is suitable for ordinary accessed data width (e.g., 2ⁿ bits) between system bus and memory. Finally, the proposed scheme has been implemented in Verilog and validated through a wide set of simulations. The experiment results reveal that the proposed scheme can effectively mitigate multiple errors in whole memory systems. They can not only reduce the redundancy overheads of the storage array but also improve the performance of MECC circuits in fault-secure memory systems.     

New concept and hierarchy for telecommunications standards

The factors leading to the formulation of standards to meet the rapid expansion of telecommunications in China are discussed. The categories chosen for the standards and their use in managing the deployment of telecommunications networks in China are described. The standards development approach used creates standards that involve the adoption of a layered approach to networking and the definition of sets of open standards for each of these layers. The resulting integrated network is divided into three layers: the bearer layer, support layer, and service layer. To provide this layered approach, four types of telecommunications standards, appropriate to the functional needs of organizations using the standards, have been developed. The four functional types are: telecommunications basic technical standards, engineering and construction standards, operations and maintenance standards, and telecommunications general standards