Silicon-on-insulator power integrated circuits

A power integrated circuit process has been developed, based on silicon-on-insulator, which allows intelligent CMOS control circuitry to be placed alongside integrated high-voltage power devices. A breakdown voltage of 335 V has been obtained by using a silicon layer of 4 μm thickness together with a buried oxide layer of 3 μm thickness. The respective LDMOS specific on-resistance and LIGBT on-state voltage for this breakdown voltage were 148 mΩ cm² and 3.9 V, respectively.     

A p+/p-buffer/n-epi cmos compatible high-side RESURF LDMOS transistor for Power IC applications

Realising a higher voltage application utilising bridge topologies in CMOS Power IC CMOS technology presents integration and design issues that must be solved by careful selection of the manufacturing process architecture. In this paper, we present a solution that uses a p+/p-buffer/n-epi stack to implement a 100 V RESURF N-channel LDMOS high-side compatible power transistor. The device was developed and designed onto the new substrate using TCAD industrial standard softwares (TSuprem4 and Medici). Masks were designed using the Cadence Virtuoso tool set. The physical results show good transistor characteristics compatible for high-side applications. The specific resistance, RDSon, for the new device is 175 mΩ mm² and breakdown voltage for both high-side and low-side operations exceeds targeted 100 V. The design involved new starting material, and the test structures to measure latch-up susceptibility were also designed and manufactured. These structures were characterised and the results show minimal degradation in standard CMOS performance.     

Bimorph actuator with monolithically integrated CMOS OFET control

We present an electrostrictive polymer bimorph controllable with low voltage through an integrated CMOS OFET control system. We have actuated the device by applying voltages up to 400 V to the control system, and can actuate the control with 60 V switching. The electrostrictor material was used both as the substrate for the transistors and as the dielectric layer for the control circuitry. This allows for a reduction in the number of layers in the structure, minimizing the clamping effect that would compromise the strain capabilities of the device. We have characterized the macroscopic displacement of the structure through a radius of curvature measurement, ranging from 11.4 mm to 7.5 mm depending on the supply voltage provided. The architecture proposed can be scaled to larger system with higher supply voltages.     

High performance inkjet-printed C60 fullerene thin-film transistors: Toward a low-cost and reproducible solution process

We have demonstrated high performance inkjet-printed n-channel thin-film transistors (TFTs) using C₆₀ fullerene as a channel material. Highly uniform amorphous C₆₀ thin-film patterns were fabricated on a solution-wettable polymer gate dielectric layer by inkjet-printing and vacuum drying process. Fabricated C₆₀ TFTs shows great reproducibility and high performance; field-effect mobilities of 2.2–2.4 cm² V^?1 s^?1, threshold voltages of 0.4–0.6 V, subthreshold slopes of 0.11–0.16 V dec^?1 and current on/off ratio of 10⁷–10⁸ in a driving voltage of 5 V. This is due to the efficient annealing process that extracting the solvent residue and the formation of low trap-density gate dielectric surface.     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

A cascade energy band structure enhances the carrier energy in organic vertical-type triodes

Organic vertical-type triodes (OVTs) based on the cascade energy band structure as emitter layer are studied. The electric characteristics were dramatically enhanced while incorporating the cascade energy under current driving and voltage driving modes. The improvement is attributed to that injection carriers can obtain higher energy through a stepwise energy level. When the device has a layered structure of F₁₆CuPC (10 nm)/PTCDI (10 nm)/pentacene (100 nm) in emitter, it exhibits a common-base transport factor of 0.99 and a common-emitter current gain of 225 under current driving mode and exhibits a high current modulation-exceeding ?520 μA for a low collector voltage of ?5 V and a base voltage of ?5 V and the current on/off ratio of 10³ under voltage driving mode. Furthermore, we realized first organic current mirror that exhibited out/in current ratio of 0.75 and output resistance of 10⁵ Ω by using the OVTs.     

Modeling and fabrication of a microelectromechanical microwave switch

A microelectromechanical microwave switch manufactured by using a complementary metal oxide semiconductor (CMOS) post-process has been implemented. An equivalent circuit model is proposed to analyze the performance of the microwave switch. The components of the microwave switch consist of a coplanar waveguide (CPW), a suspended membrane and supported springs. The post-process requires only one wet etching to etch the sacrificial layer, and to release the suspended structures. Experimental results show that the switch has an insertion loss of −2 dB at 50 GHz and an isolation of −15 dB at 50 GHz. The driving voltage of the switch approximates to 19 V.     

High linearity,low power RF mixer design in 65 nm CMOS technology

A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB.     

All-inkjet printed organic transistors: Dielectric surface passivation techniques for improved operational stability and lifetime

We report about the use of a printed pentafluorothiophenol layer on top of the dielectric surface as a passivation coating to improve the operational stability of all-ink-jet printed transistors. Transistors with bottom-gate structure were fabricated using cross-linked poly-4-vinylphenol (c-PVP) as dielectric layer and an ink formulation of an amorphous triarylamine polymer as semiconductor. The resulting TFTs had low turn-on voltage (V_th < |5 V|) and a mobility ≈0.1 cm²/(V s). A comparison of identically fabricated transistors shows that devices with coated dielectric have a higher operational stability than those using bare c-PVP. This conclusion is supported by a quantitative study of the threshold voltage shift with time under continuous operation. Long exposure to the ambient atmosphere causes an increase in the threshold voltage strongly dependent on the used semiconducting ink formulation.     

Integration of a graphene ink as gate electrode for printed organic complementary thin-film transistors

We demonstrate a new electrode gate based on graphene ink for complementary printed organic metal oxide semiconductor (CMOS) technology on flexible plastic substrates. The goal is to replace the standard silver electrode gate. Devices made with graphene were enhanced and showed a high field-effect mobility of 3 cm² V⁻¹ s⁻¹ for P-type and 0.9 cm² V⁻¹ s⁻¹ for the N-type semiconductors. The improvement is attributed to the increase of the electrical capacitance of the organic dielectric (CYTOP) due to the graphene layer. A seven-stage ring oscillator was made with high oscillation frequencies of 2.1 kHz at 40 V corresponding to a delay/gate value of 34 μs. These performances are promising for use of low cost printed electronic applications.     

Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application

This work describes the design and implementation of an ultra-low voltage, ultra-low power fully differential low noise amplifier (LNA) integrated with a down-conversion mixer for 2.4 GHz ZigBee application. An inductive-degenerated cascoded LNA is adapted and integrated with a double-balanced mixer which is targeted for low-power application. The proposed design has been extracted and simulated in a 0.13 μm standard CMOS technology. With a power consumption of 905 μW at a voltage headroom of 0.5 V, the proposed LNA-mixer integration reaches out to an integrated noise figure (NF) of 7.2 dB, a gain of 22.3 dB, 1 dB compression point (P1 dB) of −22.3 dBm and input-referred third-order intercept point (IIP3) of −10.8 dBm.     

300-V class power n-channel LDMOS transistor implemented in 0.18-μm silicon-on-insulator (SOI) technology

A SOI platform is developed for a LDMOS transistor from 70 V to 300 V. It is one of the best cases covering the wide voltage range. By applying novel DTI technology, the pitch of a single LDMOS transistor cell is reduced. Thin silicon and oxide film help to reduce the process complexity and the cost of SOI wafer. The platform is compatible with standard CMOS technology, and is appreciable for broad power IC products.     

Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25 μm CMOS technology

This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25 μm/5 V CMOS technology. Breakdown voltages of 20 V for n-channel device with a specific on resistance of 1.06 mΩ cm² and −20 V for p-channel device with a specific on resistance of 2.83 mΩ cm² have been achieved without any modification of existing standard CMOS process.     

Low-voltage organic ferroelectric field effect transistors using Langmuir–Schaefer films of poly(vinylidene fluoride-trifluororethylene)

Langmuir–Schaefer transfer was used to fabricate ultrathin films of ferroelectric copolymer, poly(vinylidene fluoride-trifluoroethylene) (70–30 mol%), for non-volatile memory application at low operating voltage. Increasing the number of transferred monolayers up to 10 led to improved film crystallinity in the “in-plane” direction, which reduced surface roughness of the semicrystalline film. Treatment of the substrate surface by plasma results in different film coverage which was subsequently found to be governed by interaction of the deposited film and surface condition. Localized ferroelectric switching was substantially attained using piezo-force tip at 10 V on 10-monolayer films. Integrating this film as a dielectric layer into organic capacitor and field effect transistor yields a reasonably good leakage current (<10^?7 A/cm²) with hysteresis in capacitance and drain current with ON/OFF ratio of 10³ for organic ferroelectric memory application at significantly reduced operating voltage of |15| V.     

Electrical and optical characteristics of phosphorescent organic light-emitting device with thin-codoped layer insertion

In this paper, we demonstrated the changes of electrical and optical characteristics of a phosphorescent organic light-emitting device (OLED) with tris(phenylpyridine)iridium Ir(ppy)₃ thin layer (4 nm) slightly codoped (1%) inside the emitting layer (EML) close to the cathode side. Such a thin layer helped for electron injection and transport from the electron transporting layer into the EML, which reduced the driving voltage (0.40 V at 100 mA/cm²). Electroluminescence (EL) spectral shift at different driving voltage was observed in our blue OLED with [(4,6-di-fluoropheny)-pyridinato-N,C^2′]picolinate (FIrpic) emitter, which came from the recombination zone shift. With the incorporation of thin-codoped Ir(ppy)₃, such EL spectral shift was almost undetectable (color coordinate shift (0.000, 0.001) from 100 to 10,000 cd/m²), due to the compensation of Ir(ppy)₃ emission at low driving voltage. Such a methodology can be applied to a white OLED which stabilized the EL spectrum and the color coordinates ((0.012, 0.002) from 100 to 10,000 cd/m²).     

Low-operating-voltage polymeric transistor with solution-processed low-k polymer/high-k metal-oxide bilayer insulators

We have successfully demonstrated a polymeric semiconductor-based transistor with low-k polymer/high-k metal-oxide (TiO₂) bilayer as gate dielectric. The TiO₂ layers are readily processable from solution and cured at low temperature, instead of traditionally sputtering or high temperature sintering process, thus may suitable for a low-cost organic field effect transistors (FETs) manufacture. The low-k polymer capped on TiO₂ layer could further smooth the TiO₂ dielectric surface and suppress the leakage current from grain boundary of TiO₂ films. The resulting unpatented P3HT-OFETs could operate with supply voltage less than 10 V and the mobility and threshold voltage were 0.0140 cm²/V s and 1.14 V, respectively. The on/off ratio was 1.0 × 10³.     

Simulation and fabrication of HF microelectromechanical bandpass filter

A high-frequency (HF) micromechanical bandpass filter fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-process has been investigated in this study. The area of the filter is about 150×200 μm². The filter is composed of two resonators, which are joined by a coupling beam. Each resonator contains a membrane, four supported beams and two fixed electrodes, and the membrane is supported by four supported beams. The filter requires a post-process to etch the sacrificial layer, and to release the suspended structures. The post-process needs only one wet etching to etch silicon dioxide layer. The filter contains a sensing part and a driving part. When applying a driving voltage to the driving part, the sensing part generates a change in capacitance. The capacitance variation of the sensing part is converted into the output voltage by a sensing circuitry. Experiments show that the filter has a center frequency of about 39.6 MHz and a bandwidth of 330 kHz.     

1 Volt organic transistors with mixed self-assembled monolayer/Al2O3 gate dielectrics

Control of the threshold voltage and the subthreshold swing is critical for low voltage transistor operation. In this contribution, organic field-effect transistors (OFETs) operating at 1 V using ultra-thin (∼4 nm), self-assembled monolayer (SAM) modified aluminium oxide layers as the gate dielectric are demonstrated. A solution-processed donor–acceptor semiconducting polymer poly(3,6-di(2-thien-5-yl)-2,5-di(2-octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione)thieno[3,2-b]thiophene) (PDPP2TTT) is used as the active layer. It is shown that the threshold voltage of the fabricated transistors can be simply tuned by carefully controlling the composition of the applied SAM. The optimised OFETs display threshold voltages around 0 V, low subthreshold slopes (150 ± 5 mV/dec), operate with negligible hysteresis and show average saturated field-effect mobilities in excess of 0.1 cm²/V s at 1 V.     

Transimpedance amplifier with a compression stage for wide dynamic range optical applications

A high dynamic input transimpedance amplifier was implemented in 130 nm CMOS technology. The proposed TIA is an inverter with a diode connected NMOS and a gate controlled PMOS loads which is cascode connected with the inverter. The square law compression NMOS increases the input photocurrent up to 10 mA. The TIA has an integrated input referred noise current of 135 nA, 227 MHz bandwidth. The TIA shows a transimpedance gain of 59 dBΩ and a 97 dB dynamic range. The TIA consumes 2.3 mA from 1.5 V voltage supply.     

AlGaN/GaN Schottky barrier diodes on silicon substrates with various Fe doping concentrations in the buffer layers

This study demonstrated AlGaN/GaN Schottky barrier diodes (SBDs) for use in high-frequency, high-power, and high-temperature electronics applications. Four structures with various Fe doping concentrations in the buffer layers were investigated to suppress the leakage current and improve the breakdown voltage. The fabricated SBD with an Fe-doped AlGaN buffer layer of 8 × 10¹⁷ cm^− 3 realized the highest on-resistance (R_ON) and turn-on voltage (V_ON) because of the memory effect of Fe diffusion. The optimal device was the SBD with an Fe-doped buffer layer of 7 × 10¹⁷ cm^− 3, which exhibited a R_ON of 31.6 mΩ-cm², a V_ON of 1.2 V, a breakdown voltage of 803 V, and a buffer breakdown voltage of 758 V. Additionally, the low-frequency noise decreased when the Fe doping concentration in the buffer layer was increased. This was because the electron density in the channel exhibited the same trend as that of the Fe doping concentration in the buffer layer.