Whole-chip ESD protection design with efficient VDD-to-VSS ESDclamp circuits for submicron CMOS VLSI

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-μm CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-μm CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV     

Field failure mechanism and improvement of EOS failure of integrated IGBT inverter modules

In this paper, we have proved that the soft damage from human body ESD can actually cause EOS damage, while integrated IGBT inverter modules (or intelligent power modules) are operating. Failure mechanism was defined as a latchup phenomenon by ESD damage leakage. Failure modes of each failed IGBT inside two integrated IGBT inverter modules were soft and hard burnout, respectively. To determine the failure mechanism, we have done fault tree analysis. From this analysis, we could conclude the main factor as the ESD event between device ESD immunity and PCB assembly line. In addition, from the PCB assembly line, we have identified damage samples due to an ESD event. Based on this result, we have implied ESD on IGBT and intentionally caused a leakage, then applied the device to the system. After an aging test, we could reproduce soft burnout and hard burnout.     

浅谈电子制造过程中的静电及静电防护

静电释放(ESD)就是一定数量的电荷从一个物体(例如人体)传送到另外一个物体(例如芯片)的过程。这个过程能导致在极短的时间内有一个非常高的电流通过芯片,35%以上的芯片损坏都可以归咎于此。因此,在电子制造行业里保护芯片免受静电释放的损害是非常重要的。实际上,很多公司在各种不同电子应用中都遇到了如何应对急速增长的静电防护需求的问题。通过针对ESD机制和防护做了一个较全面的介绍,包括ESD原理,电流产生,危害,防静电工艺要求等。     

浅谈电子制造过程中的静电及静电防护

静电释放（ESD）就是一定数量的电荷从一个物体（例如人体）传送到另一个物体（例如芯片）的过程。这个过程能导致在极短的时间内有一个非常高的电流通过芯片,35％以上的芯片损坏都可以归咎于此。因此,在电子制造行业里保护芯片免受静电释放的损害是非常重要的。实际上,很多企业在各种不同电子应用中都遇到了如何应对急速增长的静电防护需求的问题。文章针对ESD机制和防护做了一个较全面的介绍,包括ESD原理、电流产生、危害、防静电工艺要求等。     

浅谈电子制造过程中的静电及静电防护

静电放电（ESD）就是一定数量的电荷从一个物体（例如人体）传送到另外一个物体（例如芯片）的过程。这个过程能导致在极短的时间内有一个非常高的电流通过芯片,35％以上的芯片损坏都可以归咎于此。因此,在电子制造行业里保护芯片免受静电放电的损害是非常重要的。实际上,很多公司在各种不同电子应用中都遇到了如何应对急速增长的静电防护需求的问题。针对ESD机制和防护作了一个较全面的介绍,包括ESD原理、电流产生、危害、防静电工艺要求等。     

浅谈电子制造过程中的静电及静电防护

静电释放(ESD)就是一定数量的电荷从一个物体(例如人体)传送到另外一个物体(例如芯片)的过程。这个过程能导致在极短的时间内有一个非常高的电流通过芯片,35%以上的芯片损坏都可以归咎于此。因此,在电子制造行业里保护芯片免受静电释放的损害是非常重要的。实际上,很多公司在各种不同电子应用中都遇到了如何应对急速增长的静电防护需求的问题。针对ESD机制和防护做了一个较全面的介绍,包括ESD原理,电流产生,危害,防静电工艺要求等。     

单片机的ESD EMP效应及加固技术研究

ESD EMP(静电放电产生的电磁脉冲)具有上升沿陡、频带宽和峰值大等特点,对电子系统具有很强的干扰和破坏作用。为研究ESD EMP对电子系统的影响,以单片机为实验对象,对单片机系统进行了ESD EMP辐照效应实验。实验表明,单片机系统在ESD EMP作用下,会出现10多种故障现象。文中在实验基础上研究了单片机加固技术。     

Internal chip ESD phenomena beyond the protection circuit

Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V_DD and V_SS are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects     

Hot-electron reliability and ESD latent damage

The impact of noncatastrophic electrostatic discharge (ESD) stress on hot-electron reliability as well as the effect of hot-electron (HE) injection on the ESD protection threshold are discussed. It is found that there is a factor-of-two-to-four deterioration in hot-electron reliability after low-level ESD stress. These two effects can be viewed as similar although HE is a low-current long-time process and ESD is a high-current short-time process. Therefore, techniques for characterizing hot-electron degradation were applied to measure quantitatively the damage due to ESD stress. This technique showed electrical evidence of current filaments during an ESD discharge     

Impact of ESD protection device trigger transient on the reliability of ultra-thin gate oxide

Common ESD protection devices have a snapback characteristic similar to a silicon-control rectifier. The transient voltage required to trigger these devices usually is not an important design criterion as long as it is not too high. In this work, it is demonstrated that the defect generation mechanism in oxide during electrical stress remains unchanged in the sub-nanosecond stress regime. As a result, the voltage transient can create far more defects in the gate oxide than the main ESD event clamped at the holding voltage. Due to difficulty in measurement, this oxide reliability degradation can lead to chip failure but not show up in simulated ESD test.     

IC设计中的ESD保护技术探讨

ESD是集成电路设计中最重要的可靠性问题之一。IC失效中约有40%与ESD/EOS(电学应力)失效有关。为了设计出高可靠性的IC,解决ESD问题是非常必要的。文中讲述一款芯片ESD版图设计,并且在0.35μm 1P3M 5V CMOS工艺中验证,成功通过HBM-3000V和MM-300V测试。这款芯片的端口可以被分成输入端口、输出端口、电源和地。为了达到人体放电模型(HBM)-3000V和机器放电模型(MM)-300V,首先要设计一个好的ESD保护网络。解决办法是先让ESD的电荷从端口流向电源或地,然后从电源或地流向其他端口。其次,给每种端口设计好的ESD保护电路,最后完成一张ESD保护电路版图。     

深亚微米CMOS IC全芯片ESD保护技术

CMOS工艺发展到深亚微米阶段,芯片的静电放电(ESD)保护能力受到了更大的限制。因此,需要采取更加有效而且可靠的ESD保护措施。基于改进的SCR器件和STFOD结构,本文提出了一种新颖的全芯片ESD保护架构,这种架构提高了整个芯片的抗ESD能力,节省了芯片面积,达到了对整个芯片提供全方位ESD保护的目的。     

ESD phenomena in GMR heads in the manufacturing process of HDD and GMR heads

It is well known that giant magnetoresistive (GMR) heads used for hard disk drives (HDD) are very sensitive to electrostatic discharge (ESD). In this paper, we describe a method of categorizing ESD damage modes from a standpoint of magnetic influences on the heads as observed by quasi-static test (QST) characteristics as well as electromagnetic characteristics like off-track profiles. In addition, we report an example of GMR stack interlayer diffusion which is one type of hard ESD damage. We also present an example of ESD damage that happened in an actual production process and its preventive measures as guidelines.     

High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation

This paper presents a novel Silicon Controlled Rectifier (SCR) for power line and local I/O ESD protection. The High holding current SCRs (HHI-SCR) exhibits a dual ESD clamp characteristic: low-current high-voltage clamping and high-current low-voltage clamping. These operation modes enable latch-up immune normal operation as well as superior full chip ESD protection. The minimum latch current can be controlled by specific SCR design. The HHI-SCR is demonstrated in a 0.10 μm-CMOS and in a 0.4 μm-BiCMOS technology. The design is area efficient.     

双界面智能卡芯片模拟前端ESD设计

双界面智能卡芯片静电放电(ESD)可靠性的关键是模拟前端(AFE)模块的ESD可靠性设计,如果按照代工厂发布的ESD设计规则设计,AFE模块的版图面积将非常大.针对双界面智能卡芯片AFE电路结构特点和失效机理,设计了一系列ESD测试结构.通过对这些结构的流片和测试分析,研究了器件设计参数和电路设计结构对双界面智能卡芯片ESD性能的影响.定制了适用于双界面智能卡芯片AFE模块设计的ESD设计规则,实现对ESD器件和AFE内核电路敏感结构的面积优化,最终成功缩小了AFE版图面积,降低了芯片加工成本,并且芯片通过了8 000 V人体模型(HBM) ESD测试.     

ESD与短脉冲EOS失效的微观形态分析及验证

静电放电(ESD)和过电应力(EOS)是引起芯片现场失效的最主要原因,这两种相似的失效模式使得对它们的失效机理的判断十分困难,尤其是短EOS脉冲作用时间只有几毫秒,造成的损坏与ESD损坏很相似。因此,借助扫描电子显微镜(SEM)和聚焦离子束(FIB)等成像仪器以及芯片去层处理技术分析这两种失效机理的差别非常重要。通过实例分析这两种失效的机理及微观差别,从理论角度解释ESD和EOS的失效机理,分析这两种失效在发生背景、失效位置、损坏深度和失效路径方面的差异,同时对这两种失效进行模拟验证。这种通过失效微观形态进行研究的方法,可以实现失效机理的甄别,对于提高ESD防护等级和EOS防护能力有着重要的参考作用。     

RFID的多功能ESD保护电路设计

设计了一个适用于RFID的多功能ESD保护电路，并对其工作原理和测试结果进行了论述。这个保护电路不仅能够进行传统的ESD保护。还可以避免内部电路因受到过大场强而产生的高电压造成的损坏，实现RFID限压功能．将狭义的ESD保护电路推广为广义的限压保护电路。仿真结果表明，此电路性能完全符合ISO／IEC 10373国际标准的要求。这种新的设计方法大大缩小了芯片版图面积，进而降低了芯片成本。     

Nitride-Based Schottky Barrier Sensor Module With High Electrostatic Discharge Reliability

In this study, we proposed and realized a nitride-based Schottky barrier sensor module with high electrostatic discharge (ESD) reliability. By including a Si-based ESD protection chip into the module, we can significantly enhance endurable ESD voltages under both forward and reverse human-body-mode (HBM) ESD stresses. It was found that the fabricated module can endure reverse HBM ESD stress of 7.5 KV and forward HBM ESD stress larger than 8 KV. It was also found that the inclusion of the Si-based ESD protection chip will not result in a decrease in detector responsivity     

Electrostatic discharge directly to the chip surface, caused by automatic post-wafer processing

Up to now, ESD damage is understood to be induced via device pads and to be avoided by means of appropriate protection structures located at these pads. The ESD susceptibility is classified by means of standardized stress tests. This paper shows, that with increasing importance a variety of post-wafer manufacturing and packaging processes may create a new type of evident and latent ESD damage in the device. We define this phenomenon as ESD-from-outside-to-surface (ESDFOS), as charged handlers cause discharges directly from outside into the device surface. Classical ESD tests do not cover this mechanism. The paper describes the phenomenon, its root causes, and gives practical hints for analysis and prevention.     

New ESD challenges in RFID manufacturing

The introduction of dual-band RFIDs (Radio Frequency Identification Devices) in chip cards created new ESD risks with unconventional discharge paths. On a plastic foil, a more or less grounded coil antenna for radio frequency (RF) is aluminium-printed on one half of the card. On the other half, an electrical floating, but thus, highly electrostatic charged folded dipole for ultrahigh frequency (UHF) is arranged. When the chip is placed by a flip-chip assembly process, a strong discharge takes place through the RF-UHF-path of the chip. Usual ESD protective structures are only of limited use in these cases. Discharge paths and specific risks are described in this paper as well as useful countermeasures in foil and assembly processes.