Hot-electron reliability and ESD latent damage

The impact of noncatastrophic electrostatic discharge (ESD) stress on hot-electron reliability as well as the effect of hot-electron (HE) injection on the ESD protection threshold are discussed. It is found that there is a factor-of-two-to-four deterioration in hot-electron reliability after low-level ESD stress. These two effects can be viewed as similar although HE is a low-current long-time process and ESD is a high-current short-time process. Therefore, techniques for characterizing hot-electron degradation were applied to measure quantitatively the damage due to ESD stress. This technique showed electrical evidence of current filaments during an ESD discharge     

Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions

Time-dependent dielectric breakdown of 2.2–4.7 nm gate oxides is investigated down to the nanosecond time regime. The so-called 1/E model best fits the time-to-breakdown data. Latent damage is also examined and it is seen that the trap generation rate, i.e., the damage rate, is pulse-width dependent, and, thus, d.c. data should not be used to predict the degradation rate under ESD-type stress conditions. Voltage overshoots and a slow turn-on time make low voltage triggered silicon controlled rectifiers bad candidates for protecting the ultra-thin gate oxide against CDM stress.     

Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress

The main purpose of this article is to present some silicon signatures induced by electro-static discharge (ESD) stresses and to propose to approach it with 2D and 3D TCAD simulations and under simplifying assumptions. All test chips are stressed by Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). Moreover each stress is performed on one chip only to avoid cumulative silicon signatures. It appears that the substrate current induced by any of these stresses leads to the same damage on silicon. Thus, HBM, MM and CDM have a common failure and silicon signature. Moreover the information of the Failure Analysis (FA) only cannot provide an exclusive conclusion in term of ESD stress. Also this kind of local stress can be considered as a latent default for the ESD reliability of devices by oxide overstress and/or charge trapping and/or contact impact and/or STI impact.     

Electrical overstress due to ESD induced displacement currents

In this paper a new failure mode is introduced, which is related to the large dV/dt of ESD pulses. It was observed after +4 kV HBM stress for a 90V-BCD technology device and resulted in a gate oxide defect of a low voltage PMOS transistor, which was hidden deeper in the IC's circuitry. The underlying failure mechanisms are discussed based on experimental and simulational findings and measures for early identification and protection of potentially sensible devices are proposed.     

A study of the mechanisms for ESD damage to reticles

Reticles were exposed to the fringing field from an electrode biased to a high voltage. The reticles in the study included reticles designed to benchmark the electrostatic damage (ESD) hazard of photobay and production reticles of a variety of feature sizes. It was found that without any electrical contact between the reticle and the electrode, reticle damage could be done. A wide bandwidth transient-electromagnetic interference (EMI) sensing antenna revealed that the reticle sparked when a voltage as low as 2000 V was applied to the electrode. The tests showed that the ESD threshold of reticles with smaller feature sizes was lower than for reticles with larger feature sizes. Reticles were scanned under optical and atomic force microscopes for reticle damage. It was found that when the voltage was ramped to 17 kV and returned to zero, damage to the reticle was observed. When a voltage of 7.5 kV was applied once, no damage was observed but when it was applied 100 times, reticle damage was observed. This study confirms that ESD damage is done to a reticle by charged objects in the vicinity of the reticle in contrast with the prevailing belief that reticle damage is done only by charge on reticles. The study also showed that reticles can be sufficiently damaged to cause printing errors due to the accumulated damage caused by repeated low level exposure to the fringing field of a charged object in the vicinity of the reticle     

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant

Electrical and SEM analysis of gate-silicided (GS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism changes from source-to-drain filamentation to drain-to-substrate short when a p-type ESD implant (ED) is used. Simulations show that the reason for change in failure mode is the different current and temperature distribution when the device is operated in bipolar mode due to the presence of ED. The size of the drain silicide blocking can be reduced from 3 to 0.75 μm by the use of ED while keeeping the same ESD failure current with the corresponding area saving benefit. When the ED implant extends under the drain contacts, the on-resistance (Ron) of the device can be reduced by 50% with respect to a design where ED is not located under the contacts.     

Analysis and Measurement of Signal Distortion due to ESD Protection Circuits

Electrostatic discharge (ESD) protection circuits typically contain a significant amount of nonlinear capacitance. At high frequencies and large amplitudes, this nonlinearity can degrade the signal integrity at the input pins of high performance mixed signal ICs, such as analog-to-digital converters (ADCs). This study provides a theoretical analysis of this problem as well as experimental results that quantify typical distortion levels introduced by state-of-the-art ESD structures. It is shown that with distortion targets nearing$- hbox100~dBc$at signal frequencies on the order of 100MHz, ESD circuits will become a limiting factor in the future. In addition to these results, this study offers some brief guidelines for designing ESD protection circuits suitable for high-speed, high-linearity applications.     

Radiation-induced depassivation of latent plasma damage

Plasma treatments are widely used in microelectronic industry but they may leave some residual passivated damage in the gate oxides at the end of the processing. The plasma-induced damage can be amplified by metal interconnects (antenna) attached to the gate during the plasma treatments. Ionising radiation reactivates this latent damage, which produces enhanced oxide charge and Si/SiO₂ interface state density. Two CMOS technologies have been investigated, with 5 and 7 nm gate oxides. Threshold voltage shifts, transconductance decrease, and interface traps build-up are always larger for plasma damaged devices than for reference devices.     

Depassivation of latent plasma damage in devices

While plasma-induced charging damage has been widely studied in recent years, much of the work has concentrated upon the impact on n-channel MOSFET reliability [1–6]. This work focuses the impact of plasma damage on pMOS devices from the viewpoint of oxide trapped charge and interface states with the experimental featuring two parameters Q_p and ΔN_p, linked respectively to the oxide charge and the interface state density. This experimental method is valid for pMOS devices in two different technologies and permits to fully compare devices with different oxide thickness. Furthermore, we demonstrate that, for a given antenna, the plasma damage roughly has the same net impact on transistor characteristics, regardless of oxide thickness.     

ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's

This paper reports an ESD internal gate-oxide damage occurred on the digital-analog interface of a mixed-mode CMOS IC. A new ESD protection method is proposed to rescue this internal gate-oxide damage by adding ESD-protection devices on the long metal line between digital-analog interfaces. Experimental verification has confirmed that the IC product can be rescued to pass 2-KV ESD stress from the digital/analog VDD to digital/analog VSS pads without causing any internal damage again.     

电子设备静电放电危害及防护技术研究

随着科学技术的进步,电器和电子设备广泛运用到人们的日常生产和生活中,静电造成的危害已受到世界各国的高度重视。文章对电子设备静电放电危害及防护技术进行了研究,希望能对人们日常用电防护提供部分对策。     

基于失效特征的静电损伤分析研究

静电放电损伤失效分析是电子制造企业分析产品质量问题和提高产品质量可靠性的难点和关键技术之一。总结梳理生产制造过程中常见的静电源和释放通路,研究元器件静电放电损伤的敏感结构,研究静电放电损伤的失效机理及其典型形貌特征,探讨静电损伤(ESD)、过电损伤(EOS)和缺陷诱发失效的鉴别方法。最后将这些方法应用在具体的失效案例中,为企业开展静电放电失效分析工作提供一种有效的鉴别分析方法。     

Possible improvement in television-signal prediction due to interframe correlation

An analysis of t.v. signals as a 3rd-order Markoff source has been made. Possible improvements achieved by a 3rd-order prediction is also examined.     

Low-frequency noise characterization of latent damage in thinoxides subjected to high-field impulse stressing

Latent damage in thin oxides, caused by high-field impulse stressing, can lead to increased trap generation in the device during the subsequent hot-carrier stressing. Monitoring of such damage is typically carried out by detecting the change in an appropriate electrical parameter of the device or by extracting the generated interface states and trapped charges. It was found that low-frequency noise measurements could provide a more sensitive alternative for characterizing the electrostatic discharge stress-induced latent damage in thin oxides     

Soft-breakdown damage in MOSFET's due to high-density plasmaetching exposure

Gate leakage current densities on the order of nA/μm² at operating voltage levels have been observed in MOSFET's that were processed in a high-density plasma (HDP) oxide etch tool, yet these transistors have performance parameters that are within 10% of controls. These high gate leakage currents seen in the HDP etched devices were not observed in controls. Direct observation shows that these HDP exposed devices have light emission at higher voltages in the region where the gate poly-Si crosses the birds beak. Light emission in this region is also not observed in controls     

一种CMOS新型ESD保护电路设计

金属氧化物半导体(MOS)器件的缩放技术使集成电路芯片面临着严重的静电放电(ESD)威胁,而目前采用的ESD保护电路由于电流集边效应等原因,普遍存在着抗静电能力有限、占用较大芯片面积等问题。根据全芯片ESD防护机理,基于SMIC 0.18μm工艺设计并实现了一种新型ESD保护电路,其具有结构简单、占用芯片面积小、抗ESD能力强等特点。对电路的测试结果表明,相对于相同尺寸栅极接地结构ESD保护电路,新型ESD保护电路在降低35%芯片面积的同时,抗ESD击穿电压提升了32%,能够有效保护芯片内部电路免受ESD造成的损伤和降低ESD保护电路的成本。     

Impact of new chip technologies on telecommunications

Microelectronics has revolutionized the architecture and design concepts of telecommunications products dramatically. Its strength is based on the combination of three different disciplines: technology, design automation and device architecture. The evolution in all these topics will be described and illustrated with several examples of telecommunications applications. At present vlsi circuits are used in three important business segments of the telecommunications market: switching, transmission and end-user systems. The technology requirements for these applications are followed by a brief discussion on reliability requirements and future technology trends.     

Excess dark current due to saw damage in semi-insulating GaAs

Logarithmic plots of current or carrier concentration vs inverse temperature in semi-insulating GaAs samples are nearly always well characterized by straight lines with a donor activation energy of 0.76±0.02 eV, as long as the surfaces are well polished or etched and the edges are cleaved. However, edges cut with common dicing saws produce an excess conductance which can dominate the bulk conductance at room temperature and below. This excess conductance is due to carrier hopping between defects in a surface layer of approximately 2000Å thickness, which can be easily removed by etching. Some polished surfaces also exhibit this same effect.     

High-barrier Schottky diodes on p-type silicon due to dry-etching damage

It is known that the barrier height of Schottky diodes made to dry-etched silicon surfaces deviate from the barrier height values obtained for diodes fabricated on wet chemically etched or cleaved silicon. This effect, in cases where neither a substantial residue layer nor a surface film is formed, can be exploited to yield diodes on p-type Si that display barrier enhancement together with excellent diode ideality factors. It is shown that the barrier heights produced on p-type Si, by exploiting this effect of dry etching, can achieve a value of ∼0.75 eV which is ∼0.15 eV better than the best value reported for wet chemically etched or cleaved p-Si. When this barrier height value is attained, it is found to be independent of metallization. The same barrier height is achieved by two very different dry etching techniques: Ar⁺ion-beam etching (IBE) and CCl4reactive ion etching (RIE).     

Failure mechanism models for material aging due to interdiffusion

This tutorial illustrates design situations where material aging due to interdiffusion in some components can compromise system performance over time, thereby acting as a wearout failure mechanism. Microstructural diffusion mechanisms, continuum diffusion models, and interdiffusion analysis techniques are presented to design against such failures. An example illustrates the application of the mechanisms, models, and techniques in electronic packaging