Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs

Low-temperature electrical characteristics of n-type gate-all-around vertically-stacked silicon nanowire (SNW) field-effect transistors (FETs) with high-k/metal gate have been investigated and are compared to those with Fin and fully-depleted silicon-on-insulator (FD SOI) FETs. In particular, the effective electron mobilities behaviors are discussed. Nanowires with a rectangular cross section of 15 nm in width and 19 nm in height have shown a strongly degraded mobility as compared to those with Fin and FD SOI FETs. Low-temperature measurements have revealed that the mobility degradation is due to higher surface-roughness limited mobility. On the other hand, no significant difference in the interface trap densities among the kinds of FETs measured in the study have been observed from the temperature dependence in the subthreshold slope.     

On the device design assessment of multigate FETs (MuGFETs) using full process and device simulation with 3D TCAD

A design evaluation is reported for multigate FETs (MuGFETs) by implementing a full process flow using a commercial three-dimensional technology CAD (TCAD) tool within the context of optimizing the device design and underlying fabrication processes. The simulation is based on and refers to the development of the SOI-based 30 nm MuGFET devices. Using our real process flow, various process simulation parameters from diffusion and activation models are first calibrated to the experimental data. Device simulations are then performed with varying fin doping, fin width, fin height, L_dd and halo implant tilt, and box thickness. For a given fin thickness and increasing fin height, the threshold voltage, off-current, delay and short channel effects (SCEs) remain approximately insensitive, while the on-current and transconductance increases approximately linearly with the increase in fin height. On the other hand drain-induced barrier lowering (DIBL), subthreshold slope (S) and off-current I_OFF are quite sensitive to the variations in fin width (at fixed fin height). We found that the lower L_dd and halo implant tilt angle (20–30°) are beneficial in reducing the SCEs and off-current. Finally, a comparison of the simulation results with electrical measurement data is presented, which shows fairly good agreement.     

Performance and potential of ultrathin accumulation-mode SIMOXMOSFET's

A systematic experimental investigation of the influence of the silicon film thickness on the properties of accumulation-mode SOI MOSFET's has been performed, and the relevant original results are presented. Interface coupling mechanisms and their effects on the major device parameters (threshold voltages, subthreshold swing, and transconductance) are analyzed. The feasibility of ultrathin accumulation-mode SIMOX MOSFET's for future submicrometer applications is demonstrated and discussed. Floating-body effects, which stand as critical aspects for SOI devices, are also investigated and the benefit of the silicon film thinning on the breakdown behavior of accumulation-mode devices is clearly established     

Direct measurements of interfacial contact resistance, end contact resistance, and interfacial contact layer uniformity

A four-terminal microelectronic test structure and test method are described for electrically determining the degree of uniformity of the interfacial layer in metal-semiconductor contacts and for directly measuring the interfacial contact resistance. A two-dimensional resistor network model is used to obtain the relationship between the specific contact resistance and the measured interfacial contact resistance for contacts with a uniform interfacial layer. A new six-terminal test structure is used for the direct measurement of end contact resistance and the subsequent determination of front contact resistance. A methodology is described for reducing the effects of both contact-window mask misalignment and parasitic resistance associated with these measurements. Measurement results are given for 98.5-percent Al/1.5- percent Si and 100-percent Al contacts on n-type silicon.     

Performance Comparison of Graphene Nanoribbon FETs With Schottky Contacts and Doped Reservoirs

We present an atomistic 3-D simulation study of the performance of graphene-nanoribbon (GNR) Schottky-barrier field-effect transistors (SBFETs) and transistors with doped reservoirs (MOSFETs) by means of the self-consistent solution of the Poisson and SchrÖdinger equations within the nonequilibrium Green's function (NEGF) formalism. Ideal MOSFETs show slightly better electrical performance for both digital and terahertz applications. The impact of nonidealities on device performance has been investigated, taking into account the presence of single vacancy, edge roughness, and ionized impurities along the channel. In general, MOSFETs show more robust characteristics than SBFETs. Edge roughness and single-vacancy defect largely affect the performance of both device types.      

Analysis of the parasitic S/D resistance in multiple-gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.     

Robust engineering of S/D diffusion doping and metal contact layouts for multifin triple-gate FETs

This letter describes the impact of major source/drain (S/D) diffusion and extension layouts on the performance of single-fin and multifin triple-gate (TG) FETs. The fundamental tradeoff between drive current and short-channel effects is clearly demonstrated. Two guidelines are introduced for designing multifin TG-FETs: 1) In order to suppress short-channel effects, the extension region should be shallow. However, the extension should be formed along the gate-electrode edge, otherwise, the large overall S/D resistance would become an obstacle to high drivability. 2) In order to realize high drivability, the cross-sectional area of the major S/D diffusion region, which carriers go through, should be large, to suppress the significant drain-induced barrier-lowering effect, and the region should not touch the buried oxide layer.     

Relation between injection barrier and contact resistance in top-contact organic thin-film transistors

We theoretically investigate the carrier injection into top-contact bottom-gate organic thin film transistors. By means of a two-dimensional drift–diffusion model, we explicitly consider thermionic and tunneling injection in combination with subsequent carrier transport into the device. Based on numerical simulations with this model, we determine the contact resistance as a function of the nominal hole injection barrier height and temperature. Depending on the barrier height or the operating temperature, we find three distinct injection regimes. Our work reveals that in all three regimes self-regulating processes exist due to which the influx of current is adjusted according to the needs of the channel at the given point of operation.     

Improvement of the contact resistance between ITO and pentacene using various metal-oxide interlayers

Ultra-thin Al₂O₃, Ta₂O₅, and TiO₂ films were deposited on the indium tin oxide (ITO) surfaces in organic thin film transistors using the atomic layer deposition (ALD) process at room temperature, and the contact resistance was significantly improved with the increase of the dielectric constant of the interlayer. The electronic band diagrams of the pentacene/ITO structures after ALD treatment on ITO surface with various metal-oxides were measured using in situ ultra-violet photoelectron spectroscopy during the step-by-step deposition of pentacene, and these results explained the decrease of the hole injection barriers and the resulting improvement of the contact resistance between pentacene/ITO interface.     

毛刷电接触对的接触电阻研究

基于R.holm电接触理论建立了毛刷电接触对的接触电阻模型。采用有限元仿真确定了毛刷电接触对在插拔过程中只有弹性变形,并得到了接触电阻模型中的M值为1/2,进行了毛刷电接触对不同插拔深度上的接触电阻试验,通过试验数据拟合确定了毛刷电接触接触电阻模型中的K值为248。进行了毛刷、麻花针、线簧孔接触对在不同插拔深度的接触电阻对比试验,得到了毛刷电接触插拔深度的最优范围为2~2.2 mm,进行了毛刷电接触在2~2.2mm插拔深度时接触电阻寿命试验,基于接触电阻寿命曲线提出了预插拔工艺以提高接触电阻及插拔力的稳定性。毛刷电接触接触电阻研究为毛刷电接触的扩展设计、制造提供了参考。     

The effects of contact size and non-zero metal resistance on the determination of specific contact resistance

This paper presents theoretical and experimental results concerning two sources of error in the determination of specific contact resistance of ohmic contacts to semiconductor device structures that utilize circular test patterns with varying gap length. It is shown that the potential drop vs gap length data cannot be usually represented by a straight line and a non-zero metal overlay sheet resistance can significantly alter the effective contact resistance value.     

Stability and contact resistance failure criteria

Specific levels of change in contact resistance are proposed as failure criteria for both power and signal applications. The results presented in this analysis are based on threshold behavior for contact stability. Moreover, the approach taken is to define the criteria according to each application. The basis for signal contact criteria is the stability threshold for intermittent behavior as related to change in contact resistance. In the case of power, the change in voltage drop at rated current is used to establish criteria based on heating and thermal runaway. An analysis and supporting data are provided to validate these recommendations. These criteria are summarized in a single chart where change in resistance criteria is plotted as a function of current. This chart provides a universal method of establishing failure criteria for the spectrum of applications that exist today.     

Magnetic-field dependence of contact resistance

Measurements at an InSb-brass contact indicate that the application of a magnetic field perpendicular to the contact surfaces increases the contact resistance. This can be understood by assuming every conducting point to act as a Corbino disc. The effect also depends strongly on the mechanical load, which can be attributed to deformations of the contact surfaces.     

触点初始接触电阻的分布特征与寿命相关性研究

为实现用初始信息来预测继电器产品的寿命,在继电器电寿命试验的基础上,提出用核概率密度估计法和多项式拟合法对触点初始接触电阻的分布特征进行分析,并研究了初始接触电阻与寿命的相关性。研究结果表明:各个继电器初始接触电阻的变化趋势不同,起伏不定。当初始接触电阻连续出现大电阻值后,即使接触电阻随后重新回到正常值,继电器仍会很快发生失效,寿命较短;继电器初始接触电阻拟合曲线的最大值与寿命之间呈现近似线性关系。     

Relationships between common source, common gate, and common drain FETs

This paper comprehensively analyzes the relationship between common source (CS), common gate (CG), and common drain (CD) field-effect transistors (FETs). The signal and noise parameters of the CG and CD configuration can be obtained directly by using a simple set of formulas from CS signal and noise parameters. All the relationships provide a bi-directional bridge for the transformation between CS, CG, and CD FETs. This technique is based on the combination of an equivalent-circuit model and conventional two-port network signal/noise correlation matrix technique. The derived relationships have universal validity, but they have been verified at 2/spl times/40 /spl mu/m gatewidth (number of gate fingers /spl times/ unit gatewidth) double-heterojunction /spl delta/-doped AlGaAs/InGaAs/GaAs pseudomorphic high electron-mobility transistor with 0.25-/spl mu/m gate length. Good agreement has been obtained between calculated and measured results.     

铝电解电容器电极箔与引线间接触电阻的改进

铝电解电容器的内部电阻直接影响产品电性能,生产过程中必须降低并稳定电极箔与引线间的接触电阻。通过对铆接过程的分析和研究,提出改进铆接工艺的方法,即采用电极箔预冲孔的铆接工艺。实物测试表明,电极箔与引线间的接触电阻较工艺改进前降低8%～15%,其阻值离散度显著缩小,且后续制造工序及产品使用中的阻值也更稳定,有利于保证产品质量,延长产品寿命。     

Determining specific contact resistivity from contact end resistance measurements

A method is described to determine specific contact resistivity from contact end resistance measurements using a transmission line model. A test pattern is described which minimizes the effect of current fringing around contact corners and yields an accurate determination of contact width. With this pattern, the specific contact resistivities measured on 1.3 wt % Si/Al contacts to n+ silicon junctions with different dopings show very consistent values and are independent of contact geometries. The dependence of measured specific contact resistivities on doping concentration is also in good agreement with the predictions of tunneling theory. Surprisingly, the dependence on surface concentration extends well beyond the usual range of electrically active solid solubility.     

Development and characterisation of nanowire-based FETs

Development of Si nanowire-based FETs, suitable for sensor applications is reported. Process sequences for SOI and bulk p-channel FinFETs are described. SEM observations of the fabricated devices (180 nm wide, 87 nm or 175 nm high) are presented and discussed. Electrical characteristics measurements and basic characterisation results obtained for these devices are described. A procedure for serial resistance extraction has been mentioned in more detail, due to its high value inherent in the process used. Several aspects of the device sensitivity to front- and back-gate control have been discussed from the point of view of its application in biochemical detectors.     

Effect of contact resistance on Gunn-diode risetimes

It is shown that the dominant mechanism limiting the risetime of pulsed Gunn-effect oscillators is a parasitic resistance within the device. If this resistance is reduced by careful control of the contact metallisation, or alternatively by the use of n+ contacts, risetimes of 1 ns or less can be obtained. The cavity parameters are shown to have a 2nd-order effect only.     

A direct measurement of interfacial contact resistance

A method is described for directly measuring interfacial contact resistance and estimating the degree of uniformity of the interfacial layer in metal-semiconductor contacts. A two-dimensional resistor network model is used to obtain a relationship between the specific contact resistance and the measured interfacial contact resistance for contacts with a homogeneous interfacial layer. Measurement results are given for 98.5% Al/1.5% Si and 100 % Al contacts on n-type silicon.