Drive current of accumulation-mode p-channel SOI-based wrap-gated Fin-FETs

Comparisons are performed to study the drive current of accumulation-mode(AM) p-channel wrap-gated Fin-FETs.The drive current of the AM p-channel FET is 15%-26%larger than that of the inversion-mode (IM) p-channel FET with the same wrap-gated fin channel,because of the body current component in the AM FET, which becomes less dominative as the gate overdrive becomes larger.The drive currents of the AM p-channel wrap-gated Fin-FETs are 50%larger than those of the AM p-channel planar FETs,which arises from effective conducting surface broadening and volume accumulation in the AM wrap-gated Fin-FETs.The effective conducting surface broadening is due to wrap-gate-induced multi-surface conduction,while the volume accumulation,namely the majority carrier concentration anywhere in the fin cross section exceeding the fin doping density,is due to the coupling of electric fields from different parts of the wrap gate.Moreover,for AM p-channel wrap-gated Fin-FETs, the current in channel along <110> is larger than that in channel along <100>,which arises from the surface mobility difference due to different transport directions and surface orientations.That is more obvious as the gate overdrive becomes larger,when the surface current component plays a more dominative role in the total current.     

积累模式p沟道SOI基围栅Fin-FET驱动电流的研究

通过比较,研究了积累模式p沟道围栅Fin-FET的驱动电流。积累模式p沟道围栅Fin-FET的驱动电流比具有同样结构的反型模式p沟道Fin-FET的驱动电流大15% ~ 26%,这是因为前者存在体输运,但随着栅极偏压的增大体输运电流的比重逐渐减小。积累模式p沟道围栅Fin-FET的驱动电流比积累模式p沟道平面FET的驱动电流大50%,这起因于前者有效输运表面的展宽和体积累。其中有效输运表面展宽源于围栅结构感应的多表面输运,而体积累（即Fin截面中任何位置的多子浓度超过了掺杂浓度）源于围栅结构不同方向上电场的耦合。另外,对于积累模式p沟道围栅Fin-FET,由于不同输运方向和输运表面迁移率的差别,沟道沿<110>方向比沿<100>方向有较大的驱动电流,这在较大的栅极偏压使表面输运电流在总电流中占主导时变得更为明显。     

Experimental demonstration and analysis of high performance and low 1/f noise Tri-gate MOSFETs by optimizing device structure

In this paper, we experimentally investigate the performance of multi-gate MOSFETs (MUGFETs) using the advanced radical gate oxide and the accumulation-mode (AM) FD-SOI MOSFETs. Firstly, we experimentally demonstrate that the drain current in AM multi-gate MOSFET is improved about 1.3 times compared with conventional inversion-mode (IM) MOSFETs with the same gate oxide. Secondly, we indicate that 1/f noise levels in AM MUGFETs are obviously suppressed compared with the conventional IM MUGFETs. The advantages resulted from the AM device structure for MUGFETs are demonstrated in this experiment.     

Gate-self-aligned p-channel germanium MISFETs

The authors have fabricated the first gate-self-aligned germanium MISFETs and have obtained record transconductance for germanium FETs. The devices fabricated are p-channel, inversion-mode germanium MISFETs. A germanium-oxynitride gate dielectric is used and aluminum gates, serve as the mask for self-aligned source and drain implants. A maximum room-temperature transconductance of 104 mS/mm was measured for a 0.6-μm gate length. A hole inversion channel mobility of 640 cm² /V-s was calculated using transconductance and capacitance data from long-channel devices. This large hole channel mobility suggests that germanium may be an attractive candidate for CMOS technology     

Characterization and modeling of SOI varactors at various temperatures

Capacitance and quality factor of accumulation-mode and inversion-mode MOS varactors in silicon-on-insulator CMOS process were measured over a temperature range of 0/spl deg/C/spl les/T/spl les/150/spl deg/C. The temperature coefficient of capacitance of inversion-mode devices is larger than that of accumulation-mode devices in the normal operating range, because the threshold voltage is sensitive to temperature. Besides, the quality factor decreases with increasing temperature for these two types of varactors due to the increase of parasitic resistance. A device model based on BSIM3v3 model is proposed to simulate the temperature effect. The modeling results of capacitance, series resistance and quality factor for SOI varactors have excellent agreement with measured results.     

薄膜积累型SOI pMOSFET

对薄膜积累型SOI pMOSFET的制备和特性进行了研究.把一些特性和反掺杂型SOI pMOSFET进行了比较.其亚阈值斜率只有69mV/decade,而且几乎没有DIBL效应.漏击穿电压为10.5V,与反掺杂型相比,提高了40%.饱和电流为130μA/μm,比反掺杂型提高了27%以上.在3V工作电压下,101级SOI CMOS环形振荡器的单级门延迟为56ps.     

On the use of MOS varactors in RF VCOs

This paper presents two 1.8 GHz CMOS voltage-controlled oscillators (VCOs), tuned by an inversion-mode MOS varactor and an accumulation-mode MOS varactor, respectively. Both VCOs show a lower power consumption and a lower phase noise than a reference VCO tuned by a more commonly used diode varactor. The best overall performance is displayed by the accumulation-mode MOS varactor VCO. The VCOs were implemented in a standard 0.6 μm CMOS process     

Linearization of oscillation frequency for integrated LC-VCO with inversion-mode varactor

Metal-oxide semiconductor (MOS) varactors are widely used in voltage-controlled oscillators (VCOs) due to the need for a tunable capacitance. Two types of varactors that have been integrated on-chip include the inversion-mode and accumulation-mode types. The inversion-mode varactor offers immunity to latch-up, but suffers from a non-linear C(V) characteristic which directly leads to a nonlinear oscillation frequency tuning curve. This paper proposes an oscillation frequency linearization technique for LC-VCO with an inversion-mode varactor. The linearity of the frequency tuning curve is improved by linearization of C(V) characteristics of the inversion-mode varactor. A new varactor configuration consisting of varactor units and resistor divider network is proposed. The single-switch integrated LC-VCO with the proposed varactor configuration is fabricated in TSMC 0.18 μm CMOS technology. The improvement of linearity of the frequency tuning curve has been verified using mathematical models and measurement results.     

Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

We analyze the impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS (DGMOS) transistors. We propose an analytical fringe capacitance model considering gate underlap and finite source/drain length. A comparison with the simulation results show that the model can accurately estimate the fringe capacitance of the device. We show that an optimum gate underlap can significantly reduce the fringe capacitance resulting in higher performance and lower power consumption. Also, the effects of process variation in gate underlap devices are discussed. Simulation results on a three-stage ring oscillator show that with optimum gate underlap 32% improvement in delay can be achieved.     

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.     

Off-state current and performance analysis for double-gate CMOS with non-self-aligned back gate

Numerical simulation-based study of double-gate (DG) field-effect transistors (FETs) leads to the possibly viable concept of extremely scaled but nonself-aligned DG CMOS. Predictions of off-state current, on-state current, and circuit performance, accounting for short-channel effects and energy-quantization effects, in 25-nm DG FETs suggest that moderate back-gate underlap does not severely undermine the superior performance and leakage current of nanoscale DG CMOS relative to those of bulk-Si CMOS. The reverse back-gate biasing scheme for leakage reduction in DG CMOS is shown to be much more efficient than the reverse body biasing scheme in bulk Si even with moderate back-gate underlap.     

Modeling of gate underlap junctionless double gate MOSFET as bio-sensor

In this work, the sensitivity of two types gate underlap Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL DG MOSFET) has been compared when the analytes bind in the underlap region. Gate underlap region considered at source end and drain end once at a time in the channel of JL DG MOSFET. Separate models have been derived for both types of gate underlap JL DG MOSFETs and verified through device simulation TCAD tool sprocess and sdevice. To detect the bio-molecules, Dielectric Modulation technique has been used. The shift in the threshold voltage has been pondered as the sensing parameter to detect the presence of biomolecules when they are bound in gate underlap channel region of the devices.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

n+ -GaAs/undoped GaAlAs/undoped GaAs field-effect transistor

The first self aligned accumulation-mode GaAs MIS-like FET having an n+ -GaAs/undoped GaAlAs/undoped GaAs structure is reported. The FETs fabricated show the threshold voltage of almost zero (V?th = 0.035 V) and very uniform (?Vth = 0.013 V) characteristics, as expected. The transconductance is as high as 170 mS/mm, which is the highest value ever reported on GaAs MIS-like FETs.     

n-channel inversion-mode InP m.i.s.f.e.t.

Capacitance/voltage and m.i.s.f.e.t. inversion-mode f.e.t. data are reported for p-type InP. It is shown that the surface of this material appears to be inverted at zero gate bias and that good inversion-mode (normally-off) device behaviour is possible.     

关于短沟道双栅无结型晶体管的仿真研究

We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.     

Application of charge-coupled devices to infrared detection and imaging

A review of infrared sensitive charge-coupled devices (IRCCD) is presented. Operational requirements of typical IRCCD applications are briefly introduced. IRCCD devices are divided into two major categories: a) Monolithic devices, which essentially extend the original CCD concept into the IR. Monolithic IRCCD's discussed include inversion-mode devices (with narrow bandgap semiconductor substrate), accumulation-mode devices (extrinsic wide bandgap semiconductor substrate), and Schottky-barrier devices (internal photoemission), b) Hybrid devices, in which the functions of detection and signal processing are performed in separate but integratable components by an array of IR detectors and a silicon CCD shift register unit. Hybrid IRCCD's discussed include both direct injection devices (in conjunction with photovoltaic IR detectors) and indirect injection devices (in conjunction with pyroelectric and photoconductive devices).     

Large-signal analysis of MOS varactors in CMOS -G/sub m/ LC VCOs

MOS varactors are used extensively as tunable elements in the tank circuits of RF voltage-controlled oscillators (VCOs) based on submicrometer CMOS technologies. MOS varactor topologies include conventional D = S = B connected, inversion-mode (I-MOS), and accumulation-mode (A-MOS) structures. When incorporated into the VCO tank circuit, the large-signal swing of the VCO output oscillation modulates the varactor capacitance in time, resulting in a VCO tuning curve that deviates from the dc tuning curve of the particular varactor structure. This paper presents a detailed analysis of this large-signal effect. Simulated results are compared to measurements for an example 2.5-GHz complementary -G/sub m/ LC VCO using I-MOS varactors implemented in 0.35-/spl mu/m CMOS technology.     

Inversion-mode insulated gate Ga0.47In0.53As field-effect transistors

It is demonstrated that inversion-mode n-channel insulated gate field-effect transistors can be made of p-type heteroepitaxially-grown Ga0.47In0.53As layers on semi-insulating InP.     

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.